1 @c Copyright (C) 2000-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARC Dependent Features
12 @node Machine Dependencies
13 @chapter ARC Dependent Features
16 @set ARC_CORE_DEFAULT 6
20 * ARC Options:: Options
22 * ARC Directives:: ARC Machine Directives
23 * ARC Modifiers:: ARC Assembler Modifiers
24 * ARC Symbols:: ARC Pre-defined Symbols
25 * ARC Opcodes:: Opcodes
31 @cindex options for ARC
33 The following options control the type of CPU for which code is
34 assembled, and generic constraints on the code generated:
39 @cindex @code{-mcpu=@var{cpu}} command line option, ARC
40 Set architecture type and register usage for @var{cpu}. There are
41 also shortcut alias options available for backward compatibility and
42 convenience. Supported values for @var{cpu} are
45 @cindex @code{mA6} command line option, ARC
46 @cindex @code{marc600} command line option, ARC
48 Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}.
51 @cindex @code{mARC601} command line option, ARC
52 Assemble for ARC 601. Alias: @code{-mARC601}.
55 @cindex @code{mA7} command line option, ARC
56 @cindex @code{mARC700} command line option, ARC
57 Assemble for ARC 700. Aliases: @code{-mA7}, @code{-mARC700}.
63 @cindex @code{mEM} command line option, ARC
64 Assemble for ARC EM. Aliases: @code{-mEM}
67 @cindex @code{mHS} command line option, ARC
68 Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}.
72 Note: the @code{.cpu} directive (@pxref{ARC Directives}) can
73 to be used to select a core variant from within assembly code.
75 @cindex @code{-EB} command line option, ARC
77 This option specifies that the output generated by the assembler should
78 be marked as being encoded for a big-endian processor.
80 @cindex @code{-EL} command line option, ARC
82 This option specifies that the output generated by the assembler should
83 be marked as being encoded for a little-endian processor - this is the
86 @cindex @code{-mcode-density} command line option, ARC
88 This option turns on Code Density instructions. Only valid for ARC EM
91 @cindex @code{-mrelax} command line option, ARC
93 Enable support for assembly-time relaxation. The assembler will
94 replace a longer version of an instruction with a shorter one,
95 whenever it is possible.
102 * ARC-Chars:: Special Characters
103 * ARC-Regs:: Register Names
107 @subsection Special Characters
111 @cindex register name prefix character, ARC
112 @cindex ARC register name prefix character
113 A register name can optionally be prefixed by a @samp{%} character. So
114 register @code{%r0} is equivalent to @code{r0} in the assembly code.
117 @cindex line comment character, ARC
118 @cindex ARC line comment character
119 The presence of a @samp{#} character within a line (but not at the
120 start of a line) indicates the start of a comment that extends to the
121 end of the current line.
123 @emph{Note:} if a line starts with a @samp{#} character then it can
124 also be a logical line number directive (@pxref{Comments}) or a
125 preprocessor control command (@pxref{Preprocessing}).
128 @cindex symbol prefix character, ARC
129 @cindex ARC symbol prefix character
130 Prefixing an operand with an @samp{@@} specifies that the operand is a
131 symbol and not a register. This is how the assembler disambiguates
132 the use of an ARC register name as a symbol. So the instruction
136 moves the address of symbol @code{r0} into register @code{r0}.
139 @cindex line separator, ARC
140 @cindex statement separator, ARC
141 @cindex ARC line separator
142 The @samp{`} (backtick) character is used to separate statements on a
147 @cindex C preprocessor macro separator, ARC
148 @cindex ARC C preprocessor macro separator
149 Used as a separator to obtain a sequence of commands from a C
155 @subsection Register Names
157 @cindex ARC register names
158 @cindex register names, ARC
159 The ARC assembler uses the following register names for its core
164 @cindex core general registers, ARC
165 @cindex ARC core general registers
166 The core general registers. Registers @code{r26} through @code{r31}
167 have special functions, and are usually referred to by those synonyms.
170 @cindex global pointer, ARC
171 @cindex ARC global pointer
172 The global pointer and a synonym for @code{r26}.
175 @cindex frame pointer, ARC
176 @cindex ARC frame pointer
177 The frame pointer and a synonym for @code{r27}.
180 @cindex stack pointer, ARC
181 @cindex ARC stack pointer
182 The stack pointer and a synonym for @code{r28}.
185 @cindex level 1 interrupt link register, ARC
186 @cindex ARC level 1 interrupt link register
187 For ARC 600 and ARC 700, the level 1 interrupt link register and a
188 synonym for @code{r29}. Not supported for ARCv2.
191 @cindex interrupt link register, ARC
192 @cindex ARC interrupt link register
193 For ARCv2, the interrupt link register and a synonym for @code{r29}.
194 Not supported for ARC 600 and ARC 700.
197 @cindex level 2 interrupt link register, ARC
198 @cindex ARC level 2 interrupt link register
199 For ARC 600 and ARC 700, the level 2 interrupt link register and a
200 synonym for @code{r30}. Not supported for ARC v2.
203 @cindex link register, ARC
204 @cindex ARC link register
205 The link register and a synonym for @code{r31}.
208 @cindex extension core registers, ARC
209 @cindex ARC extension core registers
210 The extension core registers.
213 @cindex loop counter, ARC
214 @cindex ARC loop counter
215 The loop count register.
218 @cindex word aligned program counter, ARC
219 @cindex ARC word aligned program counter
220 The word aligned program counter.
224 In addition the ARC processor has a large number of @emph{auxiliary
225 registers}. The precise set depends on the extensions being
226 supported, but the following baseline set are always defined:
230 @cindex Processor Identification register, ARC
231 @cindex ARC Processor Identification register
232 Processor Identification register. Auxiliary register address 0x4.
235 @cindex Program Counter, ARC
236 @cindex ARC Program Counter
237 Program Counter. Auxiliary register address 0x6.
240 @cindex Status register, ARC
241 @cindex ARC Status register
242 Status register. Auxiliary register address 0x0a.
245 @cindex Branch Target Address, ARC
246 @cindex ARC Branch Target Address
247 Branch Target Address. Auxiliary register address 0x412.
250 @cindex Exception Cause Register, ARC
251 @cindex ARC Exception Cause Register
252 Exception Cause Register. Auxiliary register address 0x403.
254 @item int_vector_base
255 @cindex Interrupt Vector Base address, ARC
256 @cindex ARC Interrupt Vector Base address
257 Interrupt Vector Base address. Auxiliary register address 0x25.
260 @cindex Stored STATUS32 register on entry to level P0 interrupts, ARC
261 @cindex ARC Stored STATUS32 register on entry to level P0 interrupts
262 Stored STATUS32 register on entry to level P0 interrupts. Auxiliary
263 register address 0xb.
266 @cindex Saved User Stack Pointer, ARC
267 @cindex ARC Saved User Stack Pointer
268 Saved User Stack Pointer. Auxiliary register address 0xd.
271 @cindex Exception Return Address, ARC
272 @cindex ARC Exception Return Address
273 Exception Return Address. Auxiliary register address 0x400.
276 @cindex BTA saved on exception entry, ARC
277 @cindex ARC BTA saved on exception entry
278 BTA saved on exception entry. Auxiliary register address 0x401.
281 @cindex STATUS32 saved on exception, ARC
282 @cindex ARC STATUS32 saved on exception
283 STATUS32 saved on exception. Auxiliary register address 0x402.
286 @cindex Build Configuration Registers Version, ARC
287 @cindex ARC Build Configuration Registers Version
288 Build Configuration Registers Version. Auxiliary register address 0x60.
291 @cindex Build configuration for: BTA Registers, ARC
292 @cindex ARC Build configuration for: BTA Registers
293 Build configuration for: BTA Registers. Auxiliary register address 0x63.
295 @item vecbase_ac_build
296 @cindex Build configuration for: Interrupts, ARC
297 @cindex ARC Build configuration for: Interrupts
298 Build configuration for: Interrupts. Auxiliary register address 0x68.
301 @cindex Build configuration for: Core Registers, ARC
302 @cindex ARC Build configuration for: Core Registers
303 Build configuration for: Core Registers. Auxiliary register address 0x6e.
306 @cindex DCCM RAM Configuration Register, ARC
307 @cindex ARC DCCM RAM Configuration Register
308 DCCM RAM Configuration Register. Auxiliary register address 0xc1.
312 Additional auxiliary register names are defined according to the
313 processor architecture version and extensions selected by the options.
316 @section ARC Machine Directives
318 @cindex machine directives, ARC
319 @cindex ARC machine directives
320 The ARC version of @code{@value{AS}} supports the following additional
325 @cindex @code{lcomm} directive
326 @item .lcomm @var{symbol}, @var{length}[, @var{alignment}]
327 Reserve @var{length} (an absolute expression) bytes for a local common
328 denoted by @var{symbol}. The section and value of @var{symbol} are
329 those of the new local common. The addresses are allocated in the bss
330 section, so that at run-time the bytes start off zeroed. Since
331 @var{symbol} is not declared global, it is normally not visible to
332 @code{@value{LD}}. The optional third parameter, @var{alignment},
333 specifies the desired alignment of the symbol in the bss section,
334 specified as a byte boundary (for example, an alignment of 16 means
335 that the least significant 4 bits of the address should be zero). The
336 alignment must be an absolute expression, and it must be a power of
337 two. If no alignment is specified, as will set the alignment to the
338 largest power of two less than or equal to the size of the symbol, up
341 @cindex @code{lcommon} directive, ARC
342 @item .lcommon @var{symbol}, @var{length}[, @var{alignment}]
343 The same as @code{lcomm} directive.
345 @cindex @code{cpu} directive, ARC
347 The @code{.cpu} directive must be followed by the desired core
348 version. Permitted values for CPU are:
351 Assemble for the ARC600 instruction set.
354 Assemble for the ARC700 instruction set.
357 Assemble for the NPS400 instruction set.
360 Assemble for the ARC EM instruction set.
363 Assemble for the ARC HS instruction set.
367 Note: the @code{.cpu} directive overrides the command line option
368 @code{-mcpu=@var{cpu}}; a warning is emitted when the version is not
369 consistent between the two.
371 @item .extAuxRegister @var{name}, @var{addr}, @var{mode}
372 @cindex @code{extAuxRegister} directive, ARC
373 Auxiliary registers can be defined in the assembler source code by
374 using this directive. The first parameter, @var{name}, is the name of the
375 new auxiliary register. The second parameter, @var{addr}, is
376 address the of the auxiliary register. The third parameter,
377 @var{mode}, specifies whether the register is readable and/or writable
393 .extAuxRegister mulhi, 0x12, w
395 specifies a write only extension auxiliary register, @var{mulhi} at
398 @item .extCondCode @var{suffix}, @var{val}
399 @cindex @code{extCondCode} directive, ARC
400 ARC supports extensible condition codes. This directive defines a new
401 condition code, to be known by the suffix, @var{suffix} and will
402 depend on the value, @var{val} in the condition code.
406 .extCondCode is_busy,0x14
409 will only execute the @code{add} instruction if the condition code
412 @item .extCoreRegister @var{name}, @var{regnum}, @var{mode}, @var{shortcut}
413 @cindex @code{extCoreRegister} directive, ARC
414 Specifies an extension core register named @var{name} as a synonym for
415 the register numbered @var{regnum}. The register number must be
416 between 32 and 59. The third argument, @var{mode}, indicates whether
417 the register is readable and/or writable and is one of:
430 The final parameter, @var{shortcut} indicates whether the register has
431 a short cut in the pipeline. The valid values are:
434 The register has a short cut in the pipeline;
436 @item cannot_shortcut
437 The register does not have a short cut in the pipeline.
442 .extCoreRegister mlo, 57, r , can_shortcut
444 defines a read only extension core register, @code{mlo}, which is
445 register 57, and can short cut the pipeline.
447 @item .extInstruction @var{name}, @var{opcode}, @var{subopcode}, @var{suffixclass}, @var{syntaxclass}
448 @cindex @code{extInstruction} directive, ARC
449 ARC allows the user to specify extension instructions. These
450 extension instructions are not macros; the assembler creates encodings
451 for use of these instructions according to the specification by the
454 The first argument, @var{name}, gives the name of the instruction.
456 The second argument, @var{opcode}, is the opcode to be used (bits 31:27
459 The third argument, @var{subopcode}, is the sub-opcode to be used, but
460 the correct value also depends on the fifth argument,
463 The fourth argument, @var{suffixclass}, determines the kinds of
464 suffixes to be allowed. Valid values are:
467 No suffixes are permitted;
470 Conditional suffixes are permitted;
473 Flag setting suffixes are permitted.
475 @item SUFFIX_COND|SUFFIX_FLAG
476 Both conditional and flag setting suffices are permitted.
480 The fifth and final argument, @var{syntaxclass}, determines the syntax
481 class for the instruction. It can have the following values:
484 Two Operand Instruction;
487 Three Operand Instruction.
490 One Operand Instruction.
493 No Operand Instruction.
496 The syntax class may be followed by @samp{|} and one of the following
500 @item OP1_MUST_BE_IMM
501 Modifies syntax class @code{SYNTAX_3OP}, specifying that the first
502 operand of a three-operand instruction must be an immediate (i.e., the
503 result is discarded). This is usually used to set the flags using
504 specific instructions and not retain results.
506 @item OP1_IMM_IMPLIED
507 Modifies syntax class @code{SYNTAX_20P}, specifying that there is an
508 implied immediate destination operand which does not appear in the
511 For example, if the source code contains an instruction like:
515 the first argument is an implied immediate (that is, the result is
516 discarded). This is the same as though the source code were: inst
521 For example, defining a 64-bit multiplier with immediate operands:
523 .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
524 SYNTAX_3OP|OP1_MUST_BE_IMM
526 which specifies an extension instruction named @code{mp64} with 3
527 operands. It sets the flags and can be used with a condition code,
528 for which the first operand is an immediate, i.e. equivalent to
529 discarding the result of the operation.
531 A two operands instruction variant would be:
533 .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
534 SYNTAX_2OP|OP1_IMM_IMPLIED
536 which describes a two operand instruction with an implicit first
537 immediate operand. The result of this operation would be discarded.
542 @section ARC Assembler Modifiers
544 The following additional assembler modifiers have been added for
545 position-independent code. These modifiers are available only with
546 the ARC 700 and above processors and generate relocation entries,
547 which are interpreted by the linker as follows:
550 @item @@pcl(@var{symbol})
551 @cindex @@pcl(@var{symbol}), ARC modifier
552 Relative distance of @var{symbol}'s from the current program counter
555 @item @@gotpc(@var{symbol})
556 @cindex @@gotpc(@var{symbol}), ARC modifier
557 Relative distance of @var{symbol}'s Global Offset Table entry from the
558 current program counter location.
560 @item @@gotoff(@var{symbol})
561 @cindex @@gotoff(@var{symbol}), ARC modifier
562 Distance of @var{symbol} from the base of the Global Offset Table.
564 @item @@plt(@var{symbol})
565 @cindex @@plt(@var{symbol}), ARC modifier
566 Distance of @var{symbol}'s Procedure Linkage Table entry from the
567 current program counter. This is valid only with branch and link
568 instructions and PC-relative calls.
570 @item @@sda(@var{symbol})
571 @cindex @@sda(@var{symbol}), ARC modifier
572 Relative distance of @var{symbol} from the base of the Small Data
578 @section ARC Pre-defined Symbols
580 The following assembler symbols will prove useful when developing
581 position-independent code. These symbols are available only with the
582 ARC 700 and above processors.
585 @item __GLOBAL_OFFSET_TABLE__
586 @cindex __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol
587 Symbol referring to the base of the Global Offset Table.
590 @cindex __DYNAMIC__, ARC pre-defined symbol
591 An alias for the Global Offset Table
592 @code{Base__GLOBAL_OFFSET_TABLE__}. It can be used only with
593 @code{@@gotpc} modifiers.
601 @cindex opcodes for ARC
603 For information on the ARC instruction set, see @cite{ARC Programmers
604 Reference Manual}, available where you download the processor IP library.