1 @c Copyright (C) 1996-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
131 @code{cortex-m0plus},
132 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
133 @code{i80200} (Intel XScale processor)
134 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
137 The special name @code{all} may be used to allow the
138 assembler to accept instructions valid for any ARM processor.
140 In addition to the basic instruction set, the assembler can be told to
141 accept various extension mnemonics that extend the processor using the
142 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
143 is equivalent to specifying @code{-mcpu=ep9312}.
145 Multiple extensions may be specified, separated by a @code{+}. The
146 extensions should be specified in ascending alphabetical order.
148 Some extensions may be restricted to particular architectures; this is
149 documented in the list of extensions below.
151 Extension mnemonics may also be removed from those the assembler accepts.
152 This is done be prepending @code{no} to the option that adds the extension.
153 Extensions that are removed should be listed after all extensions which have
154 been added, again in ascending alphabetical order. For example,
155 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
158 The following extensions are currently supported:
159 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
160 @code{fp} (Floating Point Extensions for v8-A architecture),
161 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
165 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
166 @code{os} (Operating System for v6M architecture),
167 @code{sec} (Security Extensions for v6K and v7-A architectures),
168 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
169 @code{virt} (Virtualization Extensions for v7-A architecture, implies
174 @cindex @code{-march=} command line option, ARM
175 @item -march=@var{architecture}[+@var{extension}@dots{}]
176 This option specifies the target architecture. The assembler will issue
177 an error message if an attempt is made to assemble an instruction which
178 will not execute on the target architecture. The following architecture
179 names are recognized:
212 If both @code{-mcpu} and
213 @code{-march} are specified, the assembler will use
214 the setting for @code{-mcpu}.
216 The architecture option can be extended with the same instruction set
217 extension options as the @code{-mcpu} option.
219 @cindex @code{-mfpu=} command line option, ARM
220 @item -mfpu=@var{floating-point-format}
222 This option specifies the floating point format to assemble for. The
223 assembler will issue an error message if an attempt is made to assemble
224 an instruction which will not execute on the target floating point unit.
225 The following format options are recognized:
245 @code{vfpv3-d16-fp16},
260 @code{neon-fp-armv8},
262 @code{crypto-neon-fp-armv8}.
264 In addition to determining which instructions are assembled, this option
265 also affects the way in which the @code{.double} assembler directive behaves
266 when assembling little-endian code.
268 The default is dependent on the processor selected. For Architecture 5 or
269 later, the default is to assembler for VFP instructions; for earlier
270 architectures the default is to assemble for FPA instructions.
272 @cindex @code{-mthumb} command line option, ARM
274 This option specifies that the assembler should start assembling Thumb
275 instructions; that is, it should behave as though the file starts with a
276 @code{.code 16} directive.
278 @cindex @code{-mthumb-interwork} command line option, ARM
279 @item -mthumb-interwork
280 This option specifies that the output generated by the assembler should
281 be marked as supporting interworking.
283 @cindex @code{-mimplicit-it} command line option, ARM
284 @item -mimplicit-it=never
285 @itemx -mimplicit-it=always
286 @itemx -mimplicit-it=arm
287 @itemx -mimplicit-it=thumb
288 The @code{-mimplicit-it} option controls the behavior of the assembler when
289 conditional instructions are not enclosed in IT blocks.
290 There are four possible behaviors.
291 If @code{never} is specified, such constructs cause a warning in ARM
292 code and an error in Thumb-2 code.
293 If @code{always} is specified, such constructs are accepted in both
294 ARM and Thumb-2 code, where the IT instruction is added implicitly.
295 If @code{arm} is specified, such constructs are accepted in ARM code
296 and cause an error in Thumb-2 code.
297 If @code{thumb} is specified, such constructs cause a warning in ARM
298 code and are accepted in Thumb-2 code. If you omit this option, the
299 behavior is equivalent to @code{-mimplicit-it=arm}.
301 @cindex @code{-mapcs-26} command line option, ARM
302 @cindex @code{-mapcs-32} command line option, ARM
305 These options specify that the output generated by the assembler should
306 be marked as supporting the indicated version of the Arm Procedure.
309 @cindex @code{-matpcs} command line option, ARM
311 This option specifies that the output generated by the assembler should
312 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
313 enabled this option will cause the assembler to create an empty
314 debugging section in the object file called .arm.atpcs. Debuggers can
315 use this to determine the ABI being used by.
317 @cindex @code{-mapcs-float} command line option, ARM
319 This indicates the floating point variant of the APCS should be
320 used. In this variant floating point arguments are passed in FP
321 registers rather than integer registers.
323 @cindex @code{-mapcs-reentrant} command line option, ARM
324 @item -mapcs-reentrant
325 This indicates that the reentrant variant of the APCS should be used.
326 This variant supports position independent code.
328 @cindex @code{-mfloat-abi=} command line option, ARM
329 @item -mfloat-abi=@var{abi}
330 This option specifies that the output generated by the assembler should be
331 marked as using specified floating point ABI.
332 The following values are recognized:
338 @cindex @code{-eabi=} command line option, ARM
339 @item -meabi=@var{ver}
340 This option specifies which EABI version the produced object files should
342 The following values are recognized:
348 @cindex @code{-EB} command line option, ARM
350 This option specifies that the output generated by the assembler should
351 be marked as being encoded for a big-endian processor.
353 @cindex @code{-EL} command line option, ARM
355 This option specifies that the output generated by the assembler should
356 be marked as being encoded for a little-endian processor.
358 @cindex @code{-k} command line option, ARM
359 @cindex PIC code generation for ARM
361 This option specifies that the output of the assembler should be marked
362 as position-independent code (PIC).
364 @cindex @code{--fix-v4bx} command line option, ARM
366 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
367 the linker option of the same name.
369 @cindex @code{-mwarn-deprecated} command line option, ARM
370 @item -mwarn-deprecated
371 @itemx -mno-warn-deprecated
372 Enable or disable warnings about using deprecated options or
373 features. The default is to warn.
375 @cindex @code{-mccs} command line option, ARM
377 Turns on CodeComposer Studio assembly syntax compatibility mode.
385 * ARM-Instruction-Set:: Instruction Set
386 * ARM-Chars:: Special Characters
387 * ARM-Regs:: Register Names
388 * ARM-Relocations:: Relocations
389 * ARM-Neon-Alignment:: NEON Alignment Specifiers
392 @node ARM-Instruction-Set
393 @subsection Instruction Set Syntax
394 Two slightly different syntaxes are support for ARM and THUMB
395 instructions. The default, @code{divided}, uses the old style where
396 ARM and THUMB instructions had their own, separate syntaxes. The new,
397 @code{unified} syntax, which can be selected via the @code{.syntax}
398 directive, and has the following main features:
402 Immediate operands do not require a @code{#} prefix.
405 The @code{IT} instruction may appear, and if it does it is validated
406 against subsequent conditional affixes. In ARM mode it does not
407 generate machine code, in THUMB mode it does.
410 For ARM instructions the conditional affixes always appear at the end
411 of the instruction. For THUMB instructions conditional affixes can be
412 used, but only inside the scope of an @code{IT} instruction.
415 All of the instructions new to the V6T2 architecture (and later) are
416 available. (Only a few such instructions can be written in the
417 @code{divided} syntax).
420 The @code{.N} and @code{.W} suffixes are recognized and honored.
423 All instructions set the flags if and only if they have an @code{s}
428 @subsection Special Characters
430 @cindex line comment character, ARM
431 @cindex ARM line comment character
432 The presence of a @samp{@@} anywhere on a line indicates the start of
433 a comment that extends to the end of that line.
435 If a @samp{#} appears as the first character of a line then the whole
436 line is treated as a comment, but in this case the line could also be
437 a logical line number directive (@pxref{Comments}) or a preprocessor
438 control command (@pxref{Preprocessing}).
440 @cindex line separator, ARM
441 @cindex statement separator, ARM
442 @cindex ARM line separator
443 The @samp{;} character can be used instead of a newline to separate
446 @cindex immediate character, ARM
447 @cindex ARM immediate character
448 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
450 @cindex identifiers, ARM
451 @cindex ARM identifiers
452 *TODO* Explain about /data modifier on symbols.
455 @subsection Register Names
457 @cindex ARM register names
458 @cindex register names, ARM
459 *TODO* Explain about ARM register naming, and the predefined names.
461 @node ARM-Relocations
462 @subsection ARM relocation generation
464 @cindex data relocations, ARM
465 @cindex ARM data relocations
466 Specific data relocations can be generated by putting the relocation name
467 in parentheses after the symbol name. For example:
473 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
475 The following relocations are supported:
491 For compatibility with older toolchains the assembler also accepts
492 @code{(PLT)} after branch targets. On legacy targets this will
493 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
494 targets it will encode either the @samp{R_ARM_CALL} or
495 @samp{R_ARM_JUMP24} relocation, as appropriate.
497 @cindex MOVW and MOVT relocations, ARM
498 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
499 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
500 respectively. For example to load the 32-bit address of foo into r0:
503 MOVW r0, #:lower16:foo
504 MOVT r0, #:upper16:foo
507 @node ARM-Neon-Alignment
508 @subsection NEON Alignment Specifiers
510 @cindex alignment for NEON instructions
511 Some NEON load/store instructions allow an optional address
513 The ARM documentation specifies that this is indicated by
514 @samp{@@ @var{align}}. However GAS already interprets
515 the @samp{@@} character as a "line comment" start,
516 so @samp{: @var{align}} is used instead. For example:
519 vld1.8 @{q0@}, [r0, :128]
522 @node ARM Floating Point
523 @section Floating Point
525 @cindex floating point, ARM (@sc{ieee})
526 @cindex ARM floating point (@sc{ieee})
527 The ARM family uses @sc{ieee} floating-point numbers.
530 @section ARM Machine Directives
532 @cindex machine directives, ARM
533 @cindex ARM machine directives
536 @c AAAAAAAAAAAAAAAAAAAAAAAAA
538 @cindex @code{.2byte} directive, ARM
539 @cindex @code{.4byte} directive, ARM
540 @cindex @code{.8byte} directive, ARM
541 @item .2byte @var{expression} [, @var{expression}]*
542 @itemx .4byte @var{expression} [, @var{expression}]*
543 @itemx .8byte @var{expression} [, @var{expression}]*
544 These directives write 2, 4 or 8 byte values to the output section.
546 @cindex @code{.align} directive, ARM
547 @item .align @var{expression} [, @var{expression}]
548 This is the generic @var{.align} directive. For the ARM however if the
549 first argument is zero (ie no alignment is needed) the assembler will
550 behave as if the argument had been 2 (ie pad to the next four byte
551 boundary). This is for compatibility with ARM's own assembler.
553 @cindex @code{.arch} directive, ARM
554 @item .arch @var{name}
555 Select the target architecture. Valid values for @var{name} are the same as
556 for the @option{-march} commandline option.
558 Specifying @code{.arch} clears any previously selected architecture
561 @cindex @code{.arch_extension} directive, ARM
562 @item .arch_extension @var{name}
563 Add or remove an architecture extension to the target architecture. Valid
564 values for @var{name} are the same as those accepted as architectural
565 extensions by the @option{-mcpu} commandline option.
567 @code{.arch_extension} may be used multiple times to add or remove extensions
568 incrementally to the architecture being compiled for.
570 @cindex @code{.arm} directive, ARM
572 This performs the same action as @var{.code 32}.
574 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
576 @cindex @code{.bss} directive, ARM
578 This directive switches to the @code{.bss} section.
580 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
582 @cindex @code{.cantunwind} directive, ARM
584 Prevents unwinding through the current function. No personality routine
585 or exception table data is required or permitted.
587 @cindex @code{.code} directive, ARM
588 @item .code @code{[16|32]}
589 This directive selects the instruction set being generated. The value 16
590 selects Thumb, with the value 32 selecting ARM.
592 @cindex @code{.cpu} directive, ARM
593 @item .cpu @var{name}
594 Select the target processor. Valid values for @var{name} are the same as
595 for the @option{-mcpu} commandline option.
597 Specifying @code{.cpu} clears any previously selected architecture
600 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
602 @cindex @code{.dn} and @code{.qn} directives, ARM
603 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
604 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
606 The @code{dn} and @code{qn} directives are used to create typed
607 and/or indexed register aliases for use in Advanced SIMD Extension
608 (Neon) instructions. The former should be used to create aliases
609 of double-precision registers, and the latter to create aliases of
610 quad-precision registers.
612 If these directives are used to create typed aliases, those aliases can
613 be used in Neon instructions instead of writing types after the mnemonic
614 or after each operand. For example:
623 This is equivalent to writing the following:
629 Aliases created using @code{dn} or @code{qn} can be destroyed using
632 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
634 @cindex @code{.eabi_attribute} directive, ARM
635 @item .eabi_attribute @var{tag}, @var{value}
636 Set the EABI object attribute @var{tag} to @var{value}.
638 The @var{tag} is either an attribute number, or one of the following:
639 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
640 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
641 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
642 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
643 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
644 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
645 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
646 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
647 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
648 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
649 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
650 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
651 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
652 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
653 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
654 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
655 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
656 @code{Tag_conformance}, @code{Tag_T2EE_use},
657 @code{Tag_Virtualization_use}
659 The @var{value} is either a @code{number}, @code{"string"}, or
660 @code{number, "string"} depending on the tag.
662 Note - the following legacy values are also accepted by @var{tag}:
663 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
664 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
666 @cindex @code{.even} directive, ARM
668 This directive aligns to an even-numbered address.
670 @cindex @code{.extend} directive, ARM
671 @cindex @code{.ldouble} directive, ARM
672 @item .extend @var{expression} [, @var{expression}]*
673 @itemx .ldouble @var{expression} [, @var{expression}]*
674 These directives write 12byte long double floating-point values to the
675 output section. These are not compatible with current ARM processors
678 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
681 @cindex @code{.fnend} directive, ARM
683 Marks the end of a function with an unwind table entry. The unwind index
684 table entry is created when this directive is processed.
686 If no personality routine has been specified then standard personality
687 routine 0 or 1 will be used, depending on the number of unwind opcodes
691 @cindex @code{.fnstart} directive, ARM
693 Marks the start of a function with an unwind table entry.
695 @cindex @code{.force_thumb} directive, ARM
697 This directive forces the selection of Thumb instructions, even if the
698 target processor does not support those instructions
700 @cindex @code{.fpu} directive, ARM
701 @item .fpu @var{name}
702 Select the floating-point unit to assemble for. Valid values for @var{name}
703 are the same as for the @option{-mfpu} commandline option.
705 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
706 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
708 @cindex @code{.handlerdata} directive, ARM
710 Marks the end of the current function, and the start of the exception table
711 entry for that function. Anything between this directive and the
712 @code{.fnend} directive will be added to the exception table entry.
714 Must be preceded by a @code{.personality} or @code{.personalityindex}
717 @c IIIIIIIIIIIIIIIIIIIIIIIIII
719 @cindex @code{.inst} directive, ARM
720 @item .inst @var{opcode} [ , @dots{} ]
721 @itemx .inst.n @var{opcode} [ , @dots{} ]
722 @itemx .inst.w @var{opcode} [ , @dots{} ]
723 Generates the instruction corresponding to the numerical value @var{opcode}.
724 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
725 specified explicitly, overriding the normal encoding rules.
727 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
728 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
729 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
731 @item .ldouble @var{expression} [, @var{expression}]*
734 @cindex @code{.ltorg} directive, ARM
736 This directive causes the current contents of the literal pool to be
737 dumped into the current section (which is assumed to be the .text
738 section) at the current location (aligned to a word boundary).
739 @code{GAS} maintains a separate literal pool for each section and each
740 sub-section. The @code{.ltorg} directive will only affect the literal
741 pool of the current section and sub-section. At the end of assembly
742 all remaining, un-empty literal pools will automatically be dumped.
744 Note - older versions of @code{GAS} would dump the current literal
745 pool any time a section change occurred. This is no longer done, since
746 it prevents accurate control of the placement of literal pools.
748 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
750 @cindex @code{.movsp} directive, ARM
751 @item .movsp @var{reg} [, #@var{offset}]
752 Tell the unwinder that @var{reg} contains an offset from the current
753 stack pointer. If @var{offset} is not specified then it is assumed to be
756 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
757 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
759 @cindex @code{.object_arch} directive, ARM
760 @item .object_arch @var{name}
761 Override the architecture recorded in the EABI object attribute section.
762 Valid values for @var{name} are the same as for the @code{.arch} directive.
763 Typically this is useful when code uses runtime detection of CPU features.
765 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
767 @cindex @code{.packed} directive, ARM
768 @item .packed @var{expression} [, @var{expression}]*
769 This directive writes 12-byte packed floating-point values to the
770 output section. These are not compatible with current ARM processors
774 @cindex @code{.pad} directive, ARM
775 @item .pad #@var{count}
776 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
777 A positive value indicates the function prologue allocated stack space by
778 decrementing the stack pointer.
780 @cindex @code{.personality} directive, ARM
781 @item .personality @var{name}
782 Sets the personality routine for the current function to @var{name}.
784 @cindex @code{.personalityindex} directive, ARM
785 @item .personalityindex @var{index}
786 Sets the personality routine for the current function to the EABI standard
787 routine number @var{index}
789 @cindex @code{.pool} directive, ARM
791 This is a synonym for .ltorg.
793 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
794 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
796 @cindex @code{.req} directive, ARM
797 @item @var{name} .req @var{register name}
798 This creates an alias for @var{register name} called @var{name}. For
805 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
808 @cindex @code{.save} directive, ARM
809 @item .save @var{reglist}
810 Generate unwinder annotations to restore the registers in @var{reglist}.
811 The format of @var{reglist} is the same as the corresponding store-multiple
815 @exdent @emph{core registers}
816 .save @{r4, r5, r6, lr@}
817 stmfd sp!, @{r4, r5, r6, lr@}
818 @exdent @emph{FPA registers}
821 @exdent @emph{VFP registers}
822 .save @{d8, d9, d10@}
823 fstmdx sp!, @{d8, d9, d10@}
824 @exdent @emph{iWMMXt registers}
826 wstrd wr11, [sp, #-8]!
827 wstrd wr10, [sp, #-8]!
830 wstrd wr11, [sp, #-8]!
832 wstrd wr10, [sp, #-8]!
836 @cindex @code{.setfp} directive, ARM
837 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
838 Make all unwinder annotations relative to a frame pointer. Without this
839 the unwinder will use offsets from the stack pointer.
841 The syntax of this directive is the same as the @code{add} or @code{mov}
842 instruction used to set the frame pointer. @var{spreg} must be either
843 @code{sp} or mentioned in a previous @code{.movsp} directive.
853 @cindex @code{.secrel32} directive, ARM
854 @item .secrel32 @var{expression} [, @var{expression}]*
855 This directive emits relocations that evaluate to the section-relative
856 offset of each expression's symbol. This directive is only supported
859 @cindex @code{.syntax} directive, ARM
860 @item .syntax [@code{unified} | @code{divided}]
861 This directive sets the Instruction Set Syntax as described in the
862 @ref{ARM-Instruction-Set} section.
864 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
866 @cindex @code{.thumb} directive, ARM
868 This performs the same action as @var{.code 16}.
870 @cindex @code{.thumb_func} directive, ARM
872 This directive specifies that the following symbol is the name of a
873 Thumb encoded function. This information is necessary in order to allow
874 the assembler and linker to generate correct code for interworking
875 between Arm and Thumb instructions and should be used even if
876 interworking is not going to be performed. The presence of this
877 directive also implies @code{.thumb}
879 This directive is not neccessary when generating EABI objects. On these
880 targets the encoding is implicit when generating Thumb code.
882 @cindex @code{.thumb_set} directive, ARM
884 This performs the equivalent of a @code{.set} directive in that it
885 creates a symbol which is an alias for another symbol (possibly not yet
886 defined). This directive also has the added property in that it marks
887 the aliased symbol as being a thumb function entry point, in the same
888 way that the @code{.thumb_func} directive does.
890 @cindex @code{.tlsdescseq} directive, ARM
891 @item .tlsdescseq @var{tls-variable}
892 This directive is used to annotate parts of an inlined TLS descriptor
893 trampoline. Normally the trampoline is provided by the linker, and
894 this directive is not needed.
896 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
898 @cindex @code{.unreq} directive, ARM
899 @item .unreq @var{alias-name}
900 This undefines a register alias which was previously defined using the
901 @code{req}, @code{dn} or @code{qn} directives. For example:
908 An error occurs if the name is undefined. Note - this pseudo op can
909 be used to delete builtin in register name aliases (eg 'r0'). This
910 should only be done if it is really necessary.
912 @cindex @code{.unwind_raw} directive, ARM
913 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
914 Insert one of more arbitary unwind opcode bytes, which are known to adjust
915 the stack pointer by @var{offset} bytes.
917 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
920 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
922 @cindex @code{.vsave} directive, ARM
923 @item .vsave @var{vfp-reglist}
924 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
925 using FLDMD. Also works for VFPv3 registers
926 that are to be restored using VLDM.
927 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
931 @exdent @emph{VFP registers}
932 .vsave @{d8, d9, d10@}
933 fstmdd sp!, @{d8, d9, d10@}
934 @exdent @emph{VFPv3 registers}
935 .vsave @{d15, d16, d17@}
936 vstm sp!, @{d15, d16, d17@}
939 Since FLDMX and FSTMX are now deprecated, this directive should be
940 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
942 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
943 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
944 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
945 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
953 @cindex opcodes for ARM
954 @code{@value{AS}} implements all the standard ARM opcodes. It also
955 implements several pseudo opcodes, including several synthetic load
960 @cindex @code{NOP} pseudo op, ARM
966 This pseudo op will always evaluate to a legal ARM instruction that does
967 nothing. Currently it will evaluate to MOV r0, r0.
969 @cindex @code{LDR reg,=<label>} pseudo op, ARM
972 ldr <register> , = <expression>
975 If expression evaluates to a numeric constant then a MOV or MVN
976 instruction will be used in place of the LDR instruction, if the
977 constant can be generated by either of these instructions. Otherwise
978 the constant will be placed into the nearest literal pool (if it not
979 already there) and a PC relative LDR instruction will be generated.
981 @cindex @code{ADR reg,<label>} pseudo op, ARM
984 adr <register> <label>
987 This instruction will load the address of @var{label} into the indicated
988 register. The instruction will evaluate to a PC relative ADD or SUB
989 instruction depending upon where the label is located. If the label is
990 out of range, or if it is not defined in the same file (and section) as
991 the ADR instruction, then an error will be generated. This instruction
992 will not make use of the literal pool.
994 @cindex @code{ADRL reg,<label>} pseudo op, ARM
997 adrl <register> <label>
1000 This instruction will load the address of @var{label} into the indicated
1001 register. The instruction will evaluate to one or two PC relative ADD
1002 or SUB instructions depending upon where the label is located. If a
1003 second instruction is not needed a NOP instruction will be generated in
1004 its place, so that this instruction is always 8 bytes long.
1006 If the label is out of range, or if it is not defined in the same file
1007 (and section) as the ADRL instruction, then an error will be generated.
1008 This instruction will not make use of the literal pool.
1012 For information on the ARM or Thumb instruction sets, see @cite{ARM
1013 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1016 @node ARM Mapping Symbols
1017 @section Mapping Symbols
1019 The ARM ELF specification requires that special symbols be inserted
1020 into object files to mark certain features:
1026 At the start of a region of code containing ARM instructions.
1030 At the start of a region of code containing THUMB instructions.
1034 At the start of a region of data.
1038 The assembler will automatically insert these symbols for you - there
1039 is no need to code them yourself. Support for tagging symbols ($b,
1040 $f, $p and $m) which is also mentioned in the current ARM ELF
1041 specification is not implemented. This is because they have been
1042 dropped from the new EABI and so tools cannot rely upon their
1045 @node ARM Unwinding Tutorial
1048 The ABI for the ARM Architecture specifies a standard format for
1049 exception unwind information. This information is used when an
1050 exception is thrown to determine where control should be transferred.
1051 In particular, the unwind information is used to determine which
1052 function called the function that threw the exception, and which
1053 function called that one, and so forth. This information is also used
1054 to restore the values of callee-saved registers in the function
1055 catching the exception.
1057 If you are writing functions in assembly code, and those functions
1058 call other functions that throw exceptions, you must use assembly
1059 pseudo ops to ensure that appropriate exception unwind information is
1060 generated. Otherwise, if one of the functions called by your assembly
1061 code throws an exception, the run-time library will be unable to
1062 unwind the stack through your assembly code and your program will not
1065 To illustrate the use of these pseudo ops, we will examine the code
1066 that G++ generates for the following C++ input:
1069 void callee (int *);
1080 This example does not show how to throw or catch an exception from
1081 assembly code. That is a much more complex operation and should
1082 always be done in a high-level language, such as C++, that directly
1083 supports exceptions.
1085 The code generated by one particular version of G++ when compiling the
1092 @ Function supports interworking.
1093 @ args = 0, pretend = 0, frame = 8
1094 @ frame_needed = 1, uses_anonymous_args = 0
1116 Of course, the sequence of instructions varies based on the options
1117 you pass to GCC and on the version of GCC in use. The exact
1118 instructions are not important since we are focusing on the pseudo ops
1119 that are used to generate unwind information.
1121 An important assumption made by the unwinder is that the stack frame
1122 does not change during the body of the function. In particular, since
1123 we assume that the assembly code does not itself throw an exception,
1124 the only point where an exception can be thrown is from a call, such
1125 as the @code{bl} instruction above. At each call site, the same saved
1126 registers (including @code{lr}, which indicates the return address)
1127 must be located in the same locations relative to the frame pointer.
1129 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1130 op appears immediately before the first instruction of the function
1131 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1132 op appears immediately after the last instruction of the function.
1133 These pseudo ops specify the range of the function.
1135 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1136 @code{.pad}) matters; their exact locations are irrelevant. In the
1137 example above, the compiler emits the pseudo ops with particular
1138 instructions. That makes it easier to understand the code, but it is
1139 not required for correctness. It would work just as well to emit all
1140 of the pseudo ops other than @code{.fnend} in the same order, but
1141 immediately after @code{.fnstart}.
1143 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1144 indicates registers that have been saved to the stack so that they can
1145 be restored before the function returns. The argument to the
1146 @code{.save} pseudo op is a list of registers to save. If a register
1147 is ``callee-saved'' (as specified by the ABI) and is modified by the
1148 function you are writing, then your code must save the value before it
1149 is modified and restore the original value before the function
1150 returns. If an exception is thrown, the run-time library restores the
1151 values of these registers from their locations on the stack before
1152 returning control to the exception handler. (Of course, if an
1153 exception is not thrown, the function that contains the @code{.save}
1154 pseudo op restores these registers in the function epilogue, as is
1155 done with the @code{ldmfd} instruction above.)
1157 You do not have to save callee-saved registers at the very beginning
1158 of the function and you do not need to use the @code{.save} pseudo op
1159 immediately following the point at which the registers are saved.
1160 However, if you modify a callee-saved register, you must save it on
1161 the stack before modifying it and before calling any functions which
1162 might throw an exception. And, you must use the @code{.save} pseudo
1163 op to indicate that you have done so.
1165 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1166 modification of the stack pointer that does not save any registers.
1167 The argument is the number of bytes (in decimal) that are subtracted
1168 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1169 subtracting from the stack pointer increases the size of the stack.)
1171 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1172 indicates the register that contains the frame pointer. The first
1173 argument is the register that is set, which is typically @code{fp}.
1174 The second argument indicates the register from which the frame
1175 pointer takes its value. The third argument, if present, is the value
1176 (in decimal) added to the register specified by the second argument to
1177 compute the value of the frame pointer. You should not modify the
1178 frame pointer in the body of the function.
1180 If you do not use a frame pointer, then you should not use the
1181 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1182 should avoid modifying the stack pointer outside of the function
1183 prologue. Otherwise, the run-time library will be unable to find
1184 saved registers when it is unwinding the stack.
1186 The pseudo ops described above are sufficient for writing assembly
1187 code that calls functions which may throw exceptions. If you need to
1188 know more about the object-file format used to represent unwind
1189 information, you may consult the @cite{Exception Handling ABI for the
1190 ARM Architecture} available from @uref{http://infocenter.arm.com}.
projects / deliverable / binutils-gdb.git / blob