1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
29 @cindex ARM options (none)
30 @cindex options for ARM (none)
34 @cindex @code{-marm} command line option, ARM
35 @item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor.
41 @cindex @code{-marmv} command line option, ARM
42 @item -marmv@code{[2|2a|3|3m|4|4t|5|5t|5te]}
43 This option specifies the target architecture. The assembler will issue
44 an error message if an attempt is made to assemble an instruction which
45 will not execute on the target architecture.
46 The option @code{-marmv5te} specifies that v5t architecture should be
47 used with the El Segundo extensions enabled.
49 @cindex @code{-mthumb} command line option, ARM
51 This option specifies that only Thumb instructions should be assembled.
53 @cindex @code{-mall} command line option, ARM
55 This option specifies that any Arm or Thumb instruction should be assembled.
57 @cindex @code{-mfpa} command line option, ARM
58 @item -mfpa @code{[10|11]}
59 This option specifies the floating point architecture in use on the
62 @cindex @code{-mfpe-old} command line option, ARM
64 Do not allow the assembly of floating point multiple instructions.
66 @cindex @code{-mno-fpu} command line option, ARM
68 Do not allow the assembly of any floating point instructions.
70 @cindex @code{-mthumb-interwork} command line option, ARM
71 @item -mthumb-interwork
72 This option specifies that the output generated by the assembler should
73 be marked as supporting interworking.
75 @cindex @code{-mapcs} command line option, ARM
76 @item -mapcs @code{[26|32]}
77 This option specifies that the output generated by the assembler should
78 be marked as supporting the indicated version of the Arm Procedure.
81 @cindex @code{-matpcs} command line option, ARM
83 This option specifies that the output generated by the assembler should
84 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
85 enabled this option will cause the assembler to create an empty
86 debugging section in the object file called .arm.atpcs. Debuggers can
87 use this to determine the ABI being used by.
89 @cindex @code{-mapcs-float} command line option, ARM
91 This indicates the the floating point variant of the APCS should be
92 used. In this variant floating point arguments are passed in FP
93 registers rather than integer registers.
95 @cindex @code{-mapcs-reentrant} command line option, ARM
96 @item -mapcs-reentrant
97 This indicates that the reentrant variant of the APCS should be used.
98 This variant supports position independent code.
100 @cindex @code{-EB} command line option, ARM
102 This option specifies that the output generated by the assembler should
103 be marked as being encoded for a big-endian processor.
105 @cindex @code{-EL} command line option, ARM
107 This option specifies that the output generated by the assembler should
108 be marked as being encoded for a little-endian processor.
110 @cindex @code{-k} command line option, ARM
111 @cindex PIC code generation for ARM
113 This option specifies that the output of the assembler should be marked
114 as position-independent code (PIC).
116 @cindex @code{-moabi} command line option, ARM
118 This indicates that the code should be assembled using the old ARM ELF
119 conventions, based on a beta release release of the ARM-ELF
120 specifications, rather than the default conventions which are based on
121 the final release of the ARM-ELF specifications.
129 * ARM-Chars:: Special Characters
130 * ARM-Regs:: Register Names
134 @subsection Special Characters
136 @cindex line comment character, ARM
137 @cindex ARM line comment character
138 The presence of a @samp{@@} on a line indicates the start of a comment
139 that extends to the end of the current line. If a @samp{#} appears as
140 the first character of a line, the whole line is treated as a comment.
142 @cindex line separator, ARM
143 @cindex statement separator, ARM
144 @cindex ARM line separator
145 The @samp{;} character can be used instead of a newline to separate
148 @cindex immediate character, ARM
149 @cindex ARM immediate character
150 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
152 @cindex identifiers, ARM
153 @cindex ARM identifiers
154 *TODO* Explain about /data modifier on symbols.
157 @subsection Register Names
159 @cindex ARM register names
160 @cindex register names, ARM
161 *TODO* Explain about ARM register naming, and the predefined names.
163 @node ARM Floating Point
164 @section Floating Point
166 @cindex floating point, ARM (@sc{ieee})
167 @cindex ARM floating point (@sc{ieee})
168 The ARM family uses @sc{ieee} floating-point numbers.
173 @section ARM Machine Directives
175 @cindex machine directives, ARM
176 @cindex ARM machine directives
179 @cindex @code{align} directive, ARM
180 @item .align @var{expression} [, @var{expression}]
181 This is the generic @var{.align} directive. For the ARM however if the
182 first argument is zero (ie no alignment is needed) the assembler will
183 behave as if the argument had been 2 (ie pad to the next four byte
184 boundary). This is for compatability with ARM's own assembler.
186 @cindex @code{req} directive, ARM
187 @item @var{name} .req @var{register name}
188 This creates an alias for @var{register name} called @var{name}. For
195 @cindex @code{code} directive, ARM
196 @item .code @code{[16|32]}
197 This directive selects the instruction set being generated. The value 16
198 selects Thumb, with the value 32 selecting ARM.
200 @cindex @code{thumb} directive, ARM
202 This performs the same action as @var{.code 16}.
204 @cindex @code{arm} directive, ARM
206 This performs the same action as @var{.code 32}.
208 @cindex @code{force_thumb} directive, ARM
210 This directive forces the selection of Thumb instructions, even if the
211 target processor does not support those instructions
213 @cindex @code{thumb_func} directive, ARM
215 This directive specifies that the following symbol is the name of a
216 Thumb encoded function. This information is necessary in order to allow
217 the assembler and linker to generate correct code for interworking
218 between Arm and Thumb instructions and should be used even if
219 interworking is not going to be performed. The presence of this
220 directive also implies @code{.thumb}
222 @cindex @code{thumb_set} directive, ARM
224 This performs the equivalent of a @code{.set} directive in that it
225 creates a symbol which is an alias for another symbol (possibly not yet
226 defined). This directive also has the added property in that it marks
227 the aliased symbol as being a thumb function entry point, in the same
228 way that the @code{.thumb_func} directive does.
230 @cindex @code{.ltorg} directive, ARM
232 This directive causes the current contents of the literal pool to be
233 dumped into the current section (which is assumed to be the .text
234 section) at the current location (aligned to a word boundary).
236 @cindex @code{.pool} directive, ARM
238 This is a synonym for .ltorg.
246 @cindex opcodes for ARM
247 @code{@value{AS}} implements all the standard ARM opcodes. It also
248 implements several pseudo opcodes, including several synthetic load
253 @cindex @code{NOP} pseudo op, ARM
259 This pseudo op will always evaluate to a legal ARM instruction that does
260 nothing. Currently it will evaluate to MOV r0, r0.
262 @cindex @code{LDR reg,=<label>} pseudo op, ARM
265 ldr <register> , = <expression>
268 If expression evaluates to a numeric constant then a MOV or MVN
269 instruction will be used in place of the LDR instruction, if the
270 constant can be generated by either of these instructions. Otherwise
271 the constant will be placed into the nearest literal pool (if it not
272 already there) and a PC relative LDR instruction will be generated.
274 @cindex @code{ADR reg,<label>} pseudo op, ARM
277 adr <register> <label>
280 This instruction will load the address of @var{label} into the indicated
281 register. The instruction will evaluate to a PC relative ADD or SUB
282 instruction depending upon where the label is located. If the label is
283 out of range, or if it is not defined in the same file (and section) as
284 the ADR instruction, then an error will be generated. This instruction
285 will not make use of the literal pool.
287 @cindex @code{ADRL reg,<label>} pseudo op, ARM
290 adrl <register> <label>
293 This instruction will load the address of @var{label} into the indicated
294 register. The instruction will evaluate to one or two PC relative ADD
295 or SUB instructions depending upon where the label is located. If a
296 second instruction is not needed a NOP instruction will be generated in
297 its place, so that this instruction is always 8 bytes long.
299 If the label is out of range, or if it is not defined in the same file
300 (and section) as the ADRL instruction, then an error will be generated.
301 This instruction will not make use of the literal pool.
305 For information on the ARM or Thumb instruction sets, see @cite{ARM
306 Software Development Toolkit Reference Manual}, Advanced RISC Machines