1 @c Copyright (C) 1996-2018 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
145 @code{cortex-m0plus},
148 @code{marvell-whitney},
151 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
152 @code{i80200} (Intel XScale processor)
153 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
156 The special name @code{all} may be used to allow the
157 assembler to accept instructions valid for any ARM processor.
159 In addition to the basic instruction set, the assembler can be told to
160 accept various extension mnemonics that extend the processor using the
161 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
162 is equivalent to specifying @code{-mcpu=ep9312}.
164 Multiple extensions may be specified, separated by a @code{+}. The
165 extensions should be specified in ascending alphabetical order.
167 Some extensions may be restricted to particular architectures; this is
168 documented in the list of extensions below.
170 Extension mnemonics may also be removed from those the assembler accepts.
171 This is done be prepending @code{no} to the option that adds the extension.
172 Extensions that are removed should be listed after all extensions which have
173 been added, again in ascending alphabetical order. For example,
174 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
177 The following extensions are currently supported:
179 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
180 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
181 @code{fp} (Floating Point Extensions for v8-A architecture),
182 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
183 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
184 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
189 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
191 @code{os} (Operating System for v6M architecture),
192 @code{sec} (Security Extensions for v6K and v7-A architectures),
193 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
194 @code{virt} (Virtualization Extensions for v7-A architecture, implies
196 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
197 @code{ras} (Reliability, Availability and Serviceability extensions
198 for v8-A architecture),
199 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
204 @cindex @code{-march=} command-line option, ARM
205 @item -march=@var{architecture}[+@var{extension}@dots{}]
206 This option specifies the target architecture. The assembler will issue
207 an error message if an attempt is made to assemble an instruction which
208 will not execute on the target architecture. The following architecture
209 names are recognized:
249 If both @code{-mcpu} and
250 @code{-march} are specified, the assembler will use
251 the setting for @code{-mcpu}.
253 The architecture option can be extended with the same instruction set
254 extension options as the @code{-mcpu} option.
256 @cindex @code{-mfpu=} command-line option, ARM
257 @item -mfpu=@var{floating-point-format}
259 This option specifies the floating point format to assemble for. The
260 assembler will issue an error message if an attempt is made to assemble
261 an instruction which will not execute on the target floating point unit.
262 The following format options are recognized:
282 @code{vfpv3-d16-fp16},
299 @code{neon-fp-armv8},
300 @code{crypto-neon-fp-armv8},
301 @code{neon-fp-armv8.1}
303 @code{crypto-neon-fp-armv8.1}.
305 In addition to determining which instructions are assembled, this option
306 also affects the way in which the @code{.double} assembler directive behaves
307 when assembling little-endian code.
309 The default is dependent on the processor selected. For Architecture 5 or
310 later, the default is to assemble for VFP instructions; for earlier
311 architectures the default is to assemble for FPA instructions.
313 @cindex @code{-mthumb} command-line option, ARM
315 This option specifies that the assembler should start assembling Thumb
316 instructions; that is, it should behave as though the file starts with a
317 @code{.code 16} directive.
319 @cindex @code{-mthumb-interwork} command-line option, ARM
320 @item -mthumb-interwork
321 This option specifies that the output generated by the assembler should
322 be marked as supporting interworking. It also affects the behaviour
323 of the @code{ADR} and @code{ADRL} pseudo opcodes.
325 @cindex @code{-mimplicit-it} command-line option, ARM
326 @item -mimplicit-it=never
327 @itemx -mimplicit-it=always
328 @itemx -mimplicit-it=arm
329 @itemx -mimplicit-it=thumb
330 The @code{-mimplicit-it} option controls the behavior of the assembler when
331 conditional instructions are not enclosed in IT blocks.
332 There are four possible behaviors.
333 If @code{never} is specified, such constructs cause a warning in ARM
334 code and an error in Thumb-2 code.
335 If @code{always} is specified, such constructs are accepted in both
336 ARM and Thumb-2 code, where the IT instruction is added implicitly.
337 If @code{arm} is specified, such constructs are accepted in ARM code
338 and cause an error in Thumb-2 code.
339 If @code{thumb} is specified, such constructs cause a warning in ARM
340 code and are accepted in Thumb-2 code. If you omit this option, the
341 behavior is equivalent to @code{-mimplicit-it=arm}.
343 @cindex @code{-mapcs-26} command-line option, ARM
344 @cindex @code{-mapcs-32} command-line option, ARM
347 These options specify that the output generated by the assembler should
348 be marked as supporting the indicated version of the Arm Procedure.
351 @cindex @code{-matpcs} command-line option, ARM
353 This option specifies that the output generated by the assembler should
354 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
355 enabled this option will cause the assembler to create an empty
356 debugging section in the object file called .arm.atpcs. Debuggers can
357 use this to determine the ABI being used by.
359 @cindex @code{-mapcs-float} command-line option, ARM
361 This indicates the floating point variant of the APCS should be
362 used. In this variant floating point arguments are passed in FP
363 registers rather than integer registers.
365 @cindex @code{-mapcs-reentrant} command-line option, ARM
366 @item -mapcs-reentrant
367 This indicates that the reentrant variant of the APCS should be used.
368 This variant supports position independent code.
370 @cindex @code{-mfloat-abi=} command-line option, ARM
371 @item -mfloat-abi=@var{abi}
372 This option specifies that the output generated by the assembler should be
373 marked as using specified floating point ABI.
374 The following values are recognized:
380 @cindex @code{-eabi=} command-line option, ARM
381 @item -meabi=@var{ver}
382 This option specifies which EABI version the produced object files should
384 The following values are recognized:
390 @cindex @code{-EB} command-line option, ARM
392 This option specifies that the output generated by the assembler should
393 be marked as being encoded for a big-endian processor.
395 Note: If a program is being built for a system with big-endian data
396 and little-endian instructions then it should be assembled with the
397 @option{-EB} option, (all of it, code and data) and then linked with
398 the @option{--be8} option. This will reverse the endianness of the
399 instructions back to little-endian, but leave the data as big-endian.
401 @cindex @code{-EL} command-line option, ARM
403 This option specifies that the output generated by the assembler should
404 be marked as being encoded for a little-endian processor.
406 @cindex @code{-k} command-line option, ARM
407 @cindex PIC code generation for ARM
409 This option specifies that the output of the assembler should be marked
410 as position-independent code (PIC).
412 @cindex @code{--fix-v4bx} command-line option, ARM
414 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
415 the linker option of the same name.
417 @cindex @code{-mwarn-deprecated} command-line option, ARM
418 @item -mwarn-deprecated
419 @itemx -mno-warn-deprecated
420 Enable or disable warnings about using deprecated options or
421 features. The default is to warn.
423 @cindex @code{-mccs} command-line option, ARM
425 Turns on CodeComposer Studio assembly syntax compatibility mode.
427 @cindex @code{-mwarn-syms} command-line option, ARM
429 @itemx -mno-warn-syms
430 Enable or disable warnings about symbols that match the names of ARM
431 instructions. The default is to warn.
439 * ARM-Instruction-Set:: Instruction Set
440 * ARM-Chars:: Special Characters
441 * ARM-Regs:: Register Names
442 * ARM-Relocations:: Relocations
443 * ARM-Neon-Alignment:: NEON Alignment Specifiers
446 @node ARM-Instruction-Set
447 @subsection Instruction Set Syntax
448 Two slightly different syntaxes are support for ARM and THUMB
449 instructions. The default, @code{divided}, uses the old style where
450 ARM and THUMB instructions had their own, separate syntaxes. The new,
451 @code{unified} syntax, which can be selected via the @code{.syntax}
452 directive, and has the following main features:
456 Immediate operands do not require a @code{#} prefix.
459 The @code{IT} instruction may appear, and if it does it is validated
460 against subsequent conditional affixes. In ARM mode it does not
461 generate machine code, in THUMB mode it does.
464 For ARM instructions the conditional affixes always appear at the end
465 of the instruction. For THUMB instructions conditional affixes can be
466 used, but only inside the scope of an @code{IT} instruction.
469 All of the instructions new to the V6T2 architecture (and later) are
470 available. (Only a few such instructions can be written in the
471 @code{divided} syntax).
474 The @code{.N} and @code{.W} suffixes are recognized and honored.
477 All instructions set the flags if and only if they have an @code{s}
482 @subsection Special Characters
484 @cindex line comment character, ARM
485 @cindex ARM line comment character
486 The presence of a @samp{@@} anywhere on a line indicates the start of
487 a comment that extends to the end of that line.
489 If a @samp{#} appears as the first character of a line then the whole
490 line is treated as a comment, but in this case the line could also be
491 a logical line number directive (@pxref{Comments}) or a preprocessor
492 control command (@pxref{Preprocessing}).
494 @cindex line separator, ARM
495 @cindex statement separator, ARM
496 @cindex ARM line separator
497 The @samp{;} character can be used instead of a newline to separate
500 @cindex immediate character, ARM
501 @cindex ARM immediate character
502 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
504 @cindex identifiers, ARM
505 @cindex ARM identifiers
506 *TODO* Explain about /data modifier on symbols.
509 @subsection Register Names
511 @cindex ARM register names
512 @cindex register names, ARM
513 *TODO* Explain about ARM register naming, and the predefined names.
515 @node ARM-Relocations
516 @subsection ARM relocation generation
518 @cindex data relocations, ARM
519 @cindex ARM data relocations
520 Specific data relocations can be generated by putting the relocation name
521 in parentheses after the symbol name. For example:
527 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
529 The following relocations are supported:
545 For compatibility with older toolchains the assembler also accepts
546 @code{(PLT)} after branch targets. On legacy targets this will
547 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
548 targets it will encode either the @samp{R_ARM_CALL} or
549 @samp{R_ARM_JUMP24} relocation, as appropriate.
551 @cindex MOVW and MOVT relocations, ARM
552 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
553 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
554 respectively. For example to load the 32-bit address of foo into r0:
557 MOVW r0, #:lower16:foo
558 MOVT r0, #:upper16:foo
561 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
562 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
563 generated by prefixing the value with @samp{#:lower0_7:#},
564 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
565 respectively. For example to load the 32-bit address of foo into r0:
568 MOVS r0, #:upper8_15:#foo
570 ADDS r0, #:upper0_7:#foo
572 ADDS r0, #:lower8_15:#foo
574 ADDS r0, #:lower0_7:#foo
577 @node ARM-Neon-Alignment
578 @subsection NEON Alignment Specifiers
580 @cindex alignment for NEON instructions
581 Some NEON load/store instructions allow an optional address
583 The ARM documentation specifies that this is indicated by
584 @samp{@@ @var{align}}. However GAS already interprets
585 the @samp{@@} character as a "line comment" start,
586 so @samp{: @var{align}} is used instead. For example:
589 vld1.8 @{q0@}, [r0, :128]
592 @node ARM Floating Point
593 @section Floating Point
595 @cindex floating point, ARM (@sc{ieee})
596 @cindex ARM floating point (@sc{ieee})
597 The ARM family uses @sc{ieee} floating-point numbers.
600 @section ARM Machine Directives
602 @cindex machine directives, ARM
603 @cindex ARM machine directives
606 @c AAAAAAAAAAAAAAAAAAAAAAAAA
609 @cindex @code{.2byte} directive, ARM
610 @cindex @code{.4byte} directive, ARM
611 @cindex @code{.8byte} directive, ARM
612 @item .2byte @var{expression} [, @var{expression}]*
613 @itemx .4byte @var{expression} [, @var{expression}]*
614 @itemx .8byte @var{expression} [, @var{expression}]*
615 These directives write 2, 4 or 8 byte values to the output section.
618 @cindex @code{.align} directive, ARM
619 @item .align @var{expression} [, @var{expression}]
620 This is the generic @var{.align} directive. For the ARM however if the
621 first argument is zero (ie no alignment is needed) the assembler will
622 behave as if the argument had been 2 (ie pad to the next four byte
623 boundary). This is for compatibility with ARM's own assembler.
625 @cindex @code{.arch} directive, ARM
626 @item .arch @var{name}
627 Select the target architecture. Valid values for @var{name} are the same as
628 for the @option{-march} command-line option without the instruction set
631 Specifying @code{.arch} clears any previously selected architecture
634 @cindex @code{.arch_extension} directive, ARM
635 @item .arch_extension @var{name}
636 Add or remove an architecture extension to the target architecture. Valid
637 values for @var{name} are the same as those accepted as architectural
638 extensions by the @option{-mcpu} and @option{-march} command-line options.
640 @code{.arch_extension} may be used multiple times to add or remove extensions
641 incrementally to the architecture being compiled for.
643 @cindex @code{.arm} directive, ARM
645 This performs the same action as @var{.code 32}.
647 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
649 @cindex @code{.bss} directive, ARM
651 This directive switches to the @code{.bss} section.
653 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
655 @cindex @code{.cantunwind} directive, ARM
657 Prevents unwinding through the current function. No personality routine
658 or exception table data is required or permitted.
660 @cindex @code{.code} directive, ARM
661 @item .code @code{[16|32]}
662 This directive selects the instruction set being generated. The value 16
663 selects Thumb, with the value 32 selecting ARM.
665 @cindex @code{.cpu} directive, ARM
666 @item .cpu @var{name}
667 Select the target processor. Valid values for @var{name} are the same as
668 for the @option{-mcpu} command-line option without the instruction set
671 Specifying @code{.cpu} clears any previously selected architecture
674 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
676 @cindex @code{.dn} and @code{.qn} directives, ARM
677 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
678 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
680 The @code{dn} and @code{qn} directives are used to create typed
681 and/or indexed register aliases for use in Advanced SIMD Extension
682 (Neon) instructions. The former should be used to create aliases
683 of double-precision registers, and the latter to create aliases of
684 quad-precision registers.
686 If these directives are used to create typed aliases, those aliases can
687 be used in Neon instructions instead of writing types after the mnemonic
688 or after each operand. For example:
697 This is equivalent to writing the following:
703 Aliases created using @code{dn} or @code{qn} can be destroyed using
706 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
708 @cindex @code{.eabi_attribute} directive, ARM
709 @item .eabi_attribute @var{tag}, @var{value}
710 Set the EABI object attribute @var{tag} to @var{value}.
712 The @var{tag} is either an attribute number, or one of the following:
713 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
714 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
715 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
716 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
717 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
718 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
719 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
720 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
721 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
722 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
723 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
724 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
725 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
726 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
727 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
728 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
729 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
730 @code{Tag_conformance}, @code{Tag_T2EE_use},
731 @code{Tag_Virtualization_use}
733 The @var{value} is either a @code{number}, @code{"string"}, or
734 @code{number, "string"} depending on the tag.
736 Note - the following legacy values are also accepted by @var{tag}:
737 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
738 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
740 @cindex @code{.even} directive, ARM
742 This directive aligns to an even-numbered address.
744 @cindex @code{.extend} directive, ARM
745 @cindex @code{.ldouble} directive, ARM
746 @item .extend @var{expression} [, @var{expression}]*
747 @itemx .ldouble @var{expression} [, @var{expression}]*
748 These directives write 12byte long double floating-point values to the
749 output section. These are not compatible with current ARM processors
752 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
755 @cindex @code{.fnend} directive, ARM
757 Marks the end of a function with an unwind table entry. The unwind index
758 table entry is created when this directive is processed.
760 If no personality routine has been specified then standard personality
761 routine 0 or 1 will be used, depending on the number of unwind opcodes
765 @cindex @code{.fnstart} directive, ARM
767 Marks the start of a function with an unwind table entry.
769 @cindex @code{.force_thumb} directive, ARM
771 This directive forces the selection of Thumb instructions, even if the
772 target processor does not support those instructions
774 @cindex @code{.fpu} directive, ARM
775 @item .fpu @var{name}
776 Select the floating-point unit to assemble for. Valid values for @var{name}
777 are the same as for the @option{-mfpu} command-line option.
779 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
780 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
782 @cindex @code{.handlerdata} directive, ARM
784 Marks the end of the current function, and the start of the exception table
785 entry for that function. Anything between this directive and the
786 @code{.fnend} directive will be added to the exception table entry.
788 Must be preceded by a @code{.personality} or @code{.personalityindex}
791 @c IIIIIIIIIIIIIIIIIIIIIIIIII
793 @cindex @code{.inst} directive, ARM
794 @item .inst @var{opcode} [ , @dots{} ]
795 @itemx .inst.n @var{opcode} [ , @dots{} ]
796 @itemx .inst.w @var{opcode} [ , @dots{} ]
797 Generates the instruction corresponding to the numerical value @var{opcode}.
798 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
799 specified explicitly, overriding the normal encoding rules.
801 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
802 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
803 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
805 @item .ldouble @var{expression} [, @var{expression}]*
808 @cindex @code{.ltorg} directive, ARM
810 This directive causes the current contents of the literal pool to be
811 dumped into the current section (which is assumed to be the .text
812 section) at the current location (aligned to a word boundary).
813 @code{GAS} maintains a separate literal pool for each section and each
814 sub-section. The @code{.ltorg} directive will only affect the literal
815 pool of the current section and sub-section. At the end of assembly
816 all remaining, un-empty literal pools will automatically be dumped.
818 Note - older versions of @code{GAS} would dump the current literal
819 pool any time a section change occurred. This is no longer done, since
820 it prevents accurate control of the placement of literal pools.
822 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
824 @cindex @code{.movsp} directive, ARM
825 @item .movsp @var{reg} [, #@var{offset}]
826 Tell the unwinder that @var{reg} contains an offset from the current
827 stack pointer. If @var{offset} is not specified then it is assumed to be
830 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
831 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
833 @cindex @code{.object_arch} directive, ARM
834 @item .object_arch @var{name}
835 Override the architecture recorded in the EABI object attribute section.
836 Valid values for @var{name} are the same as for the @code{.arch} directive.
837 Typically this is useful when code uses runtime detection of CPU features.
839 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
841 @cindex @code{.packed} directive, ARM
842 @item .packed @var{expression} [, @var{expression}]*
843 This directive writes 12-byte packed floating-point values to the
844 output section. These are not compatible with current ARM processors
848 @cindex @code{.pad} directive, ARM
849 @item .pad #@var{count}
850 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
851 A positive value indicates the function prologue allocated stack space by
852 decrementing the stack pointer.
854 @cindex @code{.personality} directive, ARM
855 @item .personality @var{name}
856 Sets the personality routine for the current function to @var{name}.
858 @cindex @code{.personalityindex} directive, ARM
859 @item .personalityindex @var{index}
860 Sets the personality routine for the current function to the EABI standard
861 routine number @var{index}
863 @cindex @code{.pool} directive, ARM
865 This is a synonym for .ltorg.
867 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
868 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
870 @cindex @code{.req} directive, ARM
871 @item @var{name} .req @var{register name}
872 This creates an alias for @var{register name} called @var{name}. For
879 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
882 @cindex @code{.save} directive, ARM
883 @item .save @var{reglist}
884 Generate unwinder annotations to restore the registers in @var{reglist}.
885 The format of @var{reglist} is the same as the corresponding store-multiple
889 @exdent @emph{core registers}
890 .save @{r4, r5, r6, lr@}
891 stmfd sp!, @{r4, r5, r6, lr@}
892 @exdent @emph{FPA registers}
895 @exdent @emph{VFP registers}
896 .save @{d8, d9, d10@}
897 fstmdx sp!, @{d8, d9, d10@}
898 @exdent @emph{iWMMXt registers}
900 wstrd wr11, [sp, #-8]!
901 wstrd wr10, [sp, #-8]!
904 wstrd wr11, [sp, #-8]!
906 wstrd wr10, [sp, #-8]!
910 @cindex @code{.setfp} directive, ARM
911 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
912 Make all unwinder annotations relative to a frame pointer. Without this
913 the unwinder will use offsets from the stack pointer.
915 The syntax of this directive is the same as the @code{add} or @code{mov}
916 instruction used to set the frame pointer. @var{spreg} must be either
917 @code{sp} or mentioned in a previous @code{.movsp} directive.
927 @cindex @code{.secrel32} directive, ARM
928 @item .secrel32 @var{expression} [, @var{expression}]*
929 This directive emits relocations that evaluate to the section-relative
930 offset of each expression's symbol. This directive is only supported
933 @cindex @code{.syntax} directive, ARM
934 @item .syntax [@code{unified} | @code{divided}]
935 This directive sets the Instruction Set Syntax as described in the
936 @ref{ARM-Instruction-Set} section.
938 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
940 @cindex @code{.thumb} directive, ARM
942 This performs the same action as @var{.code 16}.
944 @cindex @code{.thumb_func} directive, ARM
946 This directive specifies that the following symbol is the name of a
947 Thumb encoded function. This information is necessary in order to allow
948 the assembler and linker to generate correct code for interworking
949 between Arm and Thumb instructions and should be used even if
950 interworking is not going to be performed. The presence of this
951 directive also implies @code{.thumb}
953 This directive is not necessary when generating EABI objects. On these
954 targets the encoding is implicit when generating Thumb code.
956 @cindex @code{.thumb_set} directive, ARM
958 This performs the equivalent of a @code{.set} directive in that it
959 creates a symbol which is an alias for another symbol (possibly not yet
960 defined). This directive also has the added property in that it marks
961 the aliased symbol as being a thumb function entry point, in the same
962 way that the @code{.thumb_func} directive does.
964 @cindex @code{.tlsdescseq} directive, ARM
965 @item .tlsdescseq @var{tls-variable}
966 This directive is used to annotate parts of an inlined TLS descriptor
967 trampoline. Normally the trampoline is provided by the linker, and
968 this directive is not needed.
970 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
972 @cindex @code{.unreq} directive, ARM
973 @item .unreq @var{alias-name}
974 This undefines a register alias which was previously defined using the
975 @code{req}, @code{dn} or @code{qn} directives. For example:
982 An error occurs if the name is undefined. Note - this pseudo op can
983 be used to delete builtin in register name aliases (eg 'r0'). This
984 should only be done if it is really necessary.
986 @cindex @code{.unwind_raw} directive, ARM
987 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
988 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
989 the stack pointer by @var{offset} bytes.
991 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
994 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
996 @cindex @code{.vsave} directive, ARM
997 @item .vsave @var{vfp-reglist}
998 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
999 using FLDMD. Also works for VFPv3 registers
1000 that are to be restored using VLDM.
1001 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1005 @exdent @emph{VFP registers}
1006 .vsave @{d8, d9, d10@}
1007 fstmdd sp!, @{d8, d9, d10@}
1008 @exdent @emph{VFPv3 registers}
1009 .vsave @{d15, d16, d17@}
1010 vstm sp!, @{d15, d16, d17@}
1013 Since FLDMX and FSTMX are now deprecated, this directive should be
1014 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1016 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1017 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1018 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1019 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1027 @cindex opcodes for ARM
1028 @code{@value{AS}} implements all the standard ARM opcodes. It also
1029 implements several pseudo opcodes, including several synthetic load
1034 @cindex @code{NOP} pseudo op, ARM
1040 This pseudo op will always evaluate to a legal ARM instruction that does
1041 nothing. Currently it will evaluate to MOV r0, r0.
1043 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1046 ldr <register> , = <expression>
1049 If expression evaluates to a numeric constant then a MOV or MVN
1050 instruction will be used in place of the LDR instruction, if the
1051 constant can be generated by either of these instructions. Otherwise
1052 the constant will be placed into the nearest literal pool (if it not
1053 already there) and a PC relative LDR instruction will be generated.
1055 @cindex @code{ADR reg,<label>} pseudo op, ARM
1058 adr <register> <label>
1061 This instruction will load the address of @var{label} into the indicated
1062 register. The instruction will evaluate to a PC relative ADD or SUB
1063 instruction depending upon where the label is located. If the label is
1064 out of range, or if it is not defined in the same file (and section) as
1065 the ADR instruction, then an error will be generated. This instruction
1066 will not make use of the literal pool.
1068 If @var{label} is a thumb function symbol, and thumb interworking has
1069 been enabled via the @option{-mthumb-interwork} option then the bottom
1070 bit of the value stored into @var{register} will be set. This allows
1071 the following sequence to work as expected:
1074 adr r0, thumb_function
1078 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1081 adrl <register> <label>
1084 This instruction will load the address of @var{label} into the indicated
1085 register. The instruction will evaluate to one or two PC relative ADD
1086 or SUB instructions depending upon where the label is located. If a
1087 second instruction is not needed a NOP instruction will be generated in
1088 its place, so that this instruction is always 8 bytes long.
1090 If the label is out of range, or if it is not defined in the same file
1091 (and section) as the ADRL instruction, then an error will be generated.
1092 This instruction will not make use of the literal pool.
1094 If @var{label} is a thumb function symbol, and thumb interworking has
1095 been enabled via the @option{-mthumb-interwork} option then the bottom
1096 bit of the value stored into @var{register} will be set.
1100 For information on the ARM or Thumb instruction sets, see @cite{ARM
1101 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1104 @node ARM Mapping Symbols
1105 @section Mapping Symbols
1107 The ARM ELF specification requires that special symbols be inserted
1108 into object files to mark certain features:
1114 At the start of a region of code containing ARM instructions.
1118 At the start of a region of code containing THUMB instructions.
1122 At the start of a region of data.
1126 The assembler will automatically insert these symbols for you - there
1127 is no need to code them yourself. Support for tagging symbols ($b,
1128 $f, $p and $m) which is also mentioned in the current ARM ELF
1129 specification is not implemented. This is because they have been
1130 dropped from the new EABI and so tools cannot rely upon their
1133 @node ARM Unwinding Tutorial
1136 The ABI for the ARM Architecture specifies a standard format for
1137 exception unwind information. This information is used when an
1138 exception is thrown to determine where control should be transferred.
1139 In particular, the unwind information is used to determine which
1140 function called the function that threw the exception, and which
1141 function called that one, and so forth. This information is also used
1142 to restore the values of callee-saved registers in the function
1143 catching the exception.
1145 If you are writing functions in assembly code, and those functions
1146 call other functions that throw exceptions, you must use assembly
1147 pseudo ops to ensure that appropriate exception unwind information is
1148 generated. Otherwise, if one of the functions called by your assembly
1149 code throws an exception, the run-time library will be unable to
1150 unwind the stack through your assembly code and your program will not
1153 To illustrate the use of these pseudo ops, we will examine the code
1154 that G++ generates for the following C++ input:
1157 void callee (int *);
1168 This example does not show how to throw or catch an exception from
1169 assembly code. That is a much more complex operation and should
1170 always be done in a high-level language, such as C++, that directly
1171 supports exceptions.
1173 The code generated by one particular version of G++ when compiling the
1180 @ Function supports interworking.
1181 @ args = 0, pretend = 0, frame = 8
1182 @ frame_needed = 1, uses_anonymous_args = 0
1204 Of course, the sequence of instructions varies based on the options
1205 you pass to GCC and on the version of GCC in use. The exact
1206 instructions are not important since we are focusing on the pseudo ops
1207 that are used to generate unwind information.
1209 An important assumption made by the unwinder is that the stack frame
1210 does not change during the body of the function. In particular, since
1211 we assume that the assembly code does not itself throw an exception,
1212 the only point where an exception can be thrown is from a call, such
1213 as the @code{bl} instruction above. At each call site, the same saved
1214 registers (including @code{lr}, which indicates the return address)
1215 must be located in the same locations relative to the frame pointer.
1217 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1218 op appears immediately before the first instruction of the function
1219 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1220 op appears immediately after the last instruction of the function.
1221 These pseudo ops specify the range of the function.
1223 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1224 @code{.pad}) matters; their exact locations are irrelevant. In the
1225 example above, the compiler emits the pseudo ops with particular
1226 instructions. That makes it easier to understand the code, but it is
1227 not required for correctness. It would work just as well to emit all
1228 of the pseudo ops other than @code{.fnend} in the same order, but
1229 immediately after @code{.fnstart}.
1231 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1232 indicates registers that have been saved to the stack so that they can
1233 be restored before the function returns. The argument to the
1234 @code{.save} pseudo op is a list of registers to save. If a register
1235 is ``callee-saved'' (as specified by the ABI) and is modified by the
1236 function you are writing, then your code must save the value before it
1237 is modified and restore the original value before the function
1238 returns. If an exception is thrown, the run-time library restores the
1239 values of these registers from their locations on the stack before
1240 returning control to the exception handler. (Of course, if an
1241 exception is not thrown, the function that contains the @code{.save}
1242 pseudo op restores these registers in the function epilogue, as is
1243 done with the @code{ldmfd} instruction above.)
1245 You do not have to save callee-saved registers at the very beginning
1246 of the function and you do not need to use the @code{.save} pseudo op
1247 immediately following the point at which the registers are saved.
1248 However, if you modify a callee-saved register, you must save it on
1249 the stack before modifying it and before calling any functions which
1250 might throw an exception. And, you must use the @code{.save} pseudo
1251 op to indicate that you have done so.
1253 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1254 modification of the stack pointer that does not save any registers.
1255 The argument is the number of bytes (in decimal) that are subtracted
1256 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1257 subtracting from the stack pointer increases the size of the stack.)
1259 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1260 indicates the register that contains the frame pointer. The first
1261 argument is the register that is set, which is typically @code{fp}.
1262 The second argument indicates the register from which the frame
1263 pointer takes its value. The third argument, if present, is the value
1264 (in decimal) added to the register specified by the second argument to
1265 compute the value of the frame pointer. You should not modify the
1266 frame pointer in the body of the function.
1268 If you do not use a frame pointer, then you should not use the
1269 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1270 should avoid modifying the stack pointer outside of the function
1271 prologue. Otherwise, the run-time library will be unable to find
1272 saved registers when it is unwinding the stack.
1274 The pseudo ops described above are sufficient for writing assembly
1275 code that calls functions which may throw exceptions. If you need to
1276 know more about the object-file format used to represent unwind
1277 information, you may consult the @cite{Exception Handling ABI for the
1278 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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