1 @c Copyright (C) 1996-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
134 @code{cortex-m0plus},
137 @code{marvell-whitney},
141 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
142 @code{i80200} (Intel XScale processor)
143 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
146 The special name @code{all} may be used to allow the
147 assembler to accept instructions valid for any ARM processor.
149 In addition to the basic instruction set, the assembler can be told to
150 accept various extension mnemonics that extend the processor using the
151 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
152 is equivalent to specifying @code{-mcpu=ep9312}.
154 Multiple extensions may be specified, separated by a @code{+}. The
155 extensions should be specified in ascending alphabetical order.
157 Some extensions may be restricted to particular architectures; this is
158 documented in the list of extensions below.
160 Extension mnemonics may also be removed from those the assembler accepts.
161 This is done be prepending @code{no} to the option that adds the extension.
162 Extensions that are removed should be listed after all extensions which have
163 been added, again in ascending alphabetical order. For example,
164 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
167 The following extensions are currently supported:
169 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
170 @code{fp} (Floating Point Extensions for v8-A architecture),
171 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
176 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
178 @code{os} (Operating System for v6M architecture),
179 @code{sec} (Security Extensions for v6K and v7-A architectures),
180 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
181 @code{virt} (Virtualization Extensions for v7-A architecture, implies
183 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
184 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
189 @cindex @code{-march=} command line option, ARM
190 @item -march=@var{architecture}[+@var{extension}@dots{}]
191 This option specifies the target architecture. The assembler will issue
192 an error message if an attempt is made to assemble an instruction which
193 will not execute on the target architecture. The following architecture
194 names are recognized:
229 If both @code{-mcpu} and
230 @code{-march} are specified, the assembler will use
231 the setting for @code{-mcpu}.
233 The architecture option can be extended with the same instruction set
234 extension options as the @code{-mcpu} option.
236 @cindex @code{-mfpu=} command line option, ARM
237 @item -mfpu=@var{floating-point-format}
239 This option specifies the floating point format to assemble for. The
240 assembler will issue an error message if an attempt is made to assemble
241 an instruction which will not execute on the target floating point unit.
242 The following format options are recognized:
262 @code{vfpv3-d16-fp16},
277 @code{neon-fp-armv8},
278 @code{crypto-neon-fp-armv8},
279 @code{neon-fp-armv8.1}
281 @code{crypto-neon-fp-armv8.1}.
283 In addition to determining which instructions are assembled, this option
284 also affects the way in which the @code{.double} assembler directive behaves
285 when assembling little-endian code.
287 The default is dependent on the processor selected. For Architecture 5 or
288 later, the default is to assembler for VFP instructions; for earlier
289 architectures the default is to assemble for FPA instructions.
291 @cindex @code{-mthumb} command line option, ARM
293 This option specifies that the assembler should start assembling Thumb
294 instructions; that is, it should behave as though the file starts with a
295 @code{.code 16} directive.
297 @cindex @code{-mthumb-interwork} command line option, ARM
298 @item -mthumb-interwork
299 This option specifies that the output generated by the assembler should
300 be marked as supporting interworking.
302 @cindex @code{-mimplicit-it} command line option, ARM
303 @item -mimplicit-it=never
304 @itemx -mimplicit-it=always
305 @itemx -mimplicit-it=arm
306 @itemx -mimplicit-it=thumb
307 The @code{-mimplicit-it} option controls the behavior of the assembler when
308 conditional instructions are not enclosed in IT blocks.
309 There are four possible behaviors.
310 If @code{never} is specified, such constructs cause a warning in ARM
311 code and an error in Thumb-2 code.
312 If @code{always} is specified, such constructs are accepted in both
313 ARM and Thumb-2 code, where the IT instruction is added implicitly.
314 If @code{arm} is specified, such constructs are accepted in ARM code
315 and cause an error in Thumb-2 code.
316 If @code{thumb} is specified, such constructs cause a warning in ARM
317 code and are accepted in Thumb-2 code. If you omit this option, the
318 behavior is equivalent to @code{-mimplicit-it=arm}.
320 @cindex @code{-mapcs-26} command line option, ARM
321 @cindex @code{-mapcs-32} command line option, ARM
324 These options specify that the output generated by the assembler should
325 be marked as supporting the indicated version of the Arm Procedure.
328 @cindex @code{-matpcs} command line option, ARM
330 This option specifies that the output generated by the assembler should
331 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
332 enabled this option will cause the assembler to create an empty
333 debugging section in the object file called .arm.atpcs. Debuggers can
334 use this to determine the ABI being used by.
336 @cindex @code{-mapcs-float} command line option, ARM
338 This indicates the floating point variant of the APCS should be
339 used. In this variant floating point arguments are passed in FP
340 registers rather than integer registers.
342 @cindex @code{-mapcs-reentrant} command line option, ARM
343 @item -mapcs-reentrant
344 This indicates that the reentrant variant of the APCS should be used.
345 This variant supports position independent code.
347 @cindex @code{-mfloat-abi=} command line option, ARM
348 @item -mfloat-abi=@var{abi}
349 This option specifies that the output generated by the assembler should be
350 marked as using specified floating point ABI.
351 The following values are recognized:
357 @cindex @code{-eabi=} command line option, ARM
358 @item -meabi=@var{ver}
359 This option specifies which EABI version the produced object files should
361 The following values are recognized:
367 @cindex @code{-EB} command line option, ARM
369 This option specifies that the output generated by the assembler should
370 be marked as being encoded for a big-endian processor.
372 Note: If a program is being built for a system with big-endian data
373 and little-endian instructions then it should be assembled with the
374 @option{-EB} option, (all of it, code and data) and then linked with
375 the @option{--be8} option. This will reverse the endianness of the
376 instructions back to little-endian, but leave the data as big-endian.
378 @cindex @code{-EL} command line option, ARM
380 This option specifies that the output generated by the assembler should
381 be marked as being encoded for a little-endian processor.
383 @cindex @code{-k} command line option, ARM
384 @cindex PIC code generation for ARM
386 This option specifies that the output of the assembler should be marked
387 as position-independent code (PIC).
389 @cindex @code{--fix-v4bx} command line option, ARM
391 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
392 the linker option of the same name.
394 @cindex @code{-mwarn-deprecated} command line option, ARM
395 @item -mwarn-deprecated
396 @itemx -mno-warn-deprecated
397 Enable or disable warnings about using deprecated options or
398 features. The default is to warn.
400 @cindex @code{-mccs} command line option, ARM
402 Turns on CodeComposer Studio assembly syntax compatibility mode.
404 @cindex @code{-mwarn-syms} command line option, ARM
406 @itemx -mno-warn-syms
407 Enable or disable warnings about symbols that match the names of ARM
408 instructions. The default is to warn.
416 * ARM-Instruction-Set:: Instruction Set
417 * ARM-Chars:: Special Characters
418 * ARM-Regs:: Register Names
419 * ARM-Relocations:: Relocations
420 * ARM-Neon-Alignment:: NEON Alignment Specifiers
423 @node ARM-Instruction-Set
424 @subsection Instruction Set Syntax
425 Two slightly different syntaxes are support for ARM and THUMB
426 instructions. The default, @code{divided}, uses the old style where
427 ARM and THUMB instructions had their own, separate syntaxes. The new,
428 @code{unified} syntax, which can be selected via the @code{.syntax}
429 directive, and has the following main features:
433 Immediate operands do not require a @code{#} prefix.
436 The @code{IT} instruction may appear, and if it does it is validated
437 against subsequent conditional affixes. In ARM mode it does not
438 generate machine code, in THUMB mode it does.
441 For ARM instructions the conditional affixes always appear at the end
442 of the instruction. For THUMB instructions conditional affixes can be
443 used, but only inside the scope of an @code{IT} instruction.
446 All of the instructions new to the V6T2 architecture (and later) are
447 available. (Only a few such instructions can be written in the
448 @code{divided} syntax).
451 The @code{.N} and @code{.W} suffixes are recognized and honored.
454 All instructions set the flags if and only if they have an @code{s}
459 @subsection Special Characters
461 @cindex line comment character, ARM
462 @cindex ARM line comment character
463 The presence of a @samp{@@} anywhere on a line indicates the start of
464 a comment that extends to the end of that line.
466 If a @samp{#} appears as the first character of a line then the whole
467 line is treated as a comment, but in this case the line could also be
468 a logical line number directive (@pxref{Comments}) or a preprocessor
469 control command (@pxref{Preprocessing}).
471 @cindex line separator, ARM
472 @cindex statement separator, ARM
473 @cindex ARM line separator
474 The @samp{;} character can be used instead of a newline to separate
477 @cindex immediate character, ARM
478 @cindex ARM immediate character
479 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
481 @cindex identifiers, ARM
482 @cindex ARM identifiers
483 *TODO* Explain about /data modifier on symbols.
486 @subsection Register Names
488 @cindex ARM register names
489 @cindex register names, ARM
490 *TODO* Explain about ARM register naming, and the predefined names.
492 @node ARM-Relocations
493 @subsection ARM relocation generation
495 @cindex data relocations, ARM
496 @cindex ARM data relocations
497 Specific data relocations can be generated by putting the relocation name
498 in parentheses after the symbol name. For example:
504 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
506 The following relocations are supported:
522 For compatibility with older toolchains the assembler also accepts
523 @code{(PLT)} after branch targets. On legacy targets this will
524 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
525 targets it will encode either the @samp{R_ARM_CALL} or
526 @samp{R_ARM_JUMP24} relocation, as appropriate.
528 @cindex MOVW and MOVT relocations, ARM
529 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
530 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
531 respectively. For example to load the 32-bit address of foo into r0:
534 MOVW r0, #:lower16:foo
535 MOVT r0, #:upper16:foo
538 @node ARM-Neon-Alignment
539 @subsection NEON Alignment Specifiers
541 @cindex alignment for NEON instructions
542 Some NEON load/store instructions allow an optional address
544 The ARM documentation specifies that this is indicated by
545 @samp{@@ @var{align}}. However GAS already interprets
546 the @samp{@@} character as a "line comment" start,
547 so @samp{: @var{align}} is used instead. For example:
550 vld1.8 @{q0@}, [r0, :128]
553 @node ARM Floating Point
554 @section Floating Point
556 @cindex floating point, ARM (@sc{ieee})
557 @cindex ARM floating point (@sc{ieee})
558 The ARM family uses @sc{ieee} floating-point numbers.
561 @section ARM Machine Directives
563 @cindex machine directives, ARM
564 @cindex ARM machine directives
567 @c AAAAAAAAAAAAAAAAAAAAAAAAA
569 @cindex @code{.2byte} directive, ARM
570 @cindex @code{.4byte} directive, ARM
571 @cindex @code{.8byte} directive, ARM
572 @item .2byte @var{expression} [, @var{expression}]*
573 @itemx .4byte @var{expression} [, @var{expression}]*
574 @itemx .8byte @var{expression} [, @var{expression}]*
575 These directives write 2, 4 or 8 byte values to the output section.
577 @cindex @code{.align} directive, ARM
578 @item .align @var{expression} [, @var{expression}]
579 This is the generic @var{.align} directive. For the ARM however if the
580 first argument is zero (ie no alignment is needed) the assembler will
581 behave as if the argument had been 2 (ie pad to the next four byte
582 boundary). This is for compatibility with ARM's own assembler.
584 @cindex @code{.arch} directive, ARM
585 @item .arch @var{name}
586 Select the target architecture. Valid values for @var{name} are the same as
587 for the @option{-march} commandline option.
589 Specifying @code{.arch} clears any previously selected architecture
592 @cindex @code{.arch_extension} directive, ARM
593 @item .arch_extension @var{name}
594 Add or remove an architecture extension to the target architecture. Valid
595 values for @var{name} are the same as those accepted as architectural
596 extensions by the @option{-mcpu} commandline option.
598 @code{.arch_extension} may be used multiple times to add or remove extensions
599 incrementally to the architecture being compiled for.
601 @cindex @code{.arm} directive, ARM
603 This performs the same action as @var{.code 32}.
605 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
607 @cindex @code{.bss} directive, ARM
609 This directive switches to the @code{.bss} section.
611 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
613 @cindex @code{.cantunwind} directive, ARM
615 Prevents unwinding through the current function. No personality routine
616 or exception table data is required or permitted.
618 @cindex @code{.code} directive, ARM
619 @item .code @code{[16|32]}
620 This directive selects the instruction set being generated. The value 16
621 selects Thumb, with the value 32 selecting ARM.
623 @cindex @code{.cpu} directive, ARM
624 @item .cpu @var{name}
625 Select the target processor. Valid values for @var{name} are the same as
626 for the @option{-mcpu} commandline option.
628 Specifying @code{.cpu} clears any previously selected architecture
631 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
633 @cindex @code{.dn} and @code{.qn} directives, ARM
634 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
635 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
637 The @code{dn} and @code{qn} directives are used to create typed
638 and/or indexed register aliases for use in Advanced SIMD Extension
639 (Neon) instructions. The former should be used to create aliases
640 of double-precision registers, and the latter to create aliases of
641 quad-precision registers.
643 If these directives are used to create typed aliases, those aliases can
644 be used in Neon instructions instead of writing types after the mnemonic
645 or after each operand. For example:
654 This is equivalent to writing the following:
660 Aliases created using @code{dn} or @code{qn} can be destroyed using
663 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
665 @cindex @code{.eabi_attribute} directive, ARM
666 @item .eabi_attribute @var{tag}, @var{value}
667 Set the EABI object attribute @var{tag} to @var{value}.
669 The @var{tag} is either an attribute number, or one of the following:
670 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
671 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
672 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
673 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
674 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
675 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
676 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
677 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
678 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
679 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
680 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
681 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
682 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
683 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
684 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
685 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
686 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
687 @code{Tag_conformance}, @code{Tag_T2EE_use},
688 @code{Tag_Virtualization_use}
690 The @var{value} is either a @code{number}, @code{"string"}, or
691 @code{number, "string"} depending on the tag.
693 Note - the following legacy values are also accepted by @var{tag}:
694 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
695 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
697 @cindex @code{.even} directive, ARM
699 This directive aligns to an even-numbered address.
701 @cindex @code{.extend} directive, ARM
702 @cindex @code{.ldouble} directive, ARM
703 @item .extend @var{expression} [, @var{expression}]*
704 @itemx .ldouble @var{expression} [, @var{expression}]*
705 These directives write 12byte long double floating-point values to the
706 output section. These are not compatible with current ARM processors
709 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
712 @cindex @code{.fnend} directive, ARM
714 Marks the end of a function with an unwind table entry. The unwind index
715 table entry is created when this directive is processed.
717 If no personality routine has been specified then standard personality
718 routine 0 or 1 will be used, depending on the number of unwind opcodes
722 @cindex @code{.fnstart} directive, ARM
724 Marks the start of a function with an unwind table entry.
726 @cindex @code{.force_thumb} directive, ARM
728 This directive forces the selection of Thumb instructions, even if the
729 target processor does not support those instructions
731 @cindex @code{.fpu} directive, ARM
732 @item .fpu @var{name}
733 Select the floating-point unit to assemble for. Valid values for @var{name}
734 are the same as for the @option{-mfpu} commandline option.
736 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
737 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
739 @cindex @code{.handlerdata} directive, ARM
741 Marks the end of the current function, and the start of the exception table
742 entry for that function. Anything between this directive and the
743 @code{.fnend} directive will be added to the exception table entry.
745 Must be preceded by a @code{.personality} or @code{.personalityindex}
748 @c IIIIIIIIIIIIIIIIIIIIIIIIII
750 @cindex @code{.inst} directive, ARM
751 @item .inst @var{opcode} [ , @dots{} ]
752 @itemx .inst.n @var{opcode} [ , @dots{} ]
753 @itemx .inst.w @var{opcode} [ , @dots{} ]
754 Generates the instruction corresponding to the numerical value @var{opcode}.
755 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
756 specified explicitly, overriding the normal encoding rules.
758 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
759 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
760 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
762 @item .ldouble @var{expression} [, @var{expression}]*
765 @cindex @code{.ltorg} directive, ARM
767 This directive causes the current contents of the literal pool to be
768 dumped into the current section (which is assumed to be the .text
769 section) at the current location (aligned to a word boundary).
770 @code{GAS} maintains a separate literal pool for each section and each
771 sub-section. The @code{.ltorg} directive will only affect the literal
772 pool of the current section and sub-section. At the end of assembly
773 all remaining, un-empty literal pools will automatically be dumped.
775 Note - older versions of @code{GAS} would dump the current literal
776 pool any time a section change occurred. This is no longer done, since
777 it prevents accurate control of the placement of literal pools.
779 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
781 @cindex @code{.movsp} directive, ARM
782 @item .movsp @var{reg} [, #@var{offset}]
783 Tell the unwinder that @var{reg} contains an offset from the current
784 stack pointer. If @var{offset} is not specified then it is assumed to be
787 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
788 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
790 @cindex @code{.object_arch} directive, ARM
791 @item .object_arch @var{name}
792 Override the architecture recorded in the EABI object attribute section.
793 Valid values for @var{name} are the same as for the @code{.arch} directive.
794 Typically this is useful when code uses runtime detection of CPU features.
796 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
798 @cindex @code{.packed} directive, ARM
799 @item .packed @var{expression} [, @var{expression}]*
800 This directive writes 12-byte packed floating-point values to the
801 output section. These are not compatible with current ARM processors
805 @cindex @code{.pad} directive, ARM
806 @item .pad #@var{count}
807 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
808 A positive value indicates the function prologue allocated stack space by
809 decrementing the stack pointer.
811 @cindex @code{.personality} directive, ARM
812 @item .personality @var{name}
813 Sets the personality routine for the current function to @var{name}.
815 @cindex @code{.personalityindex} directive, ARM
816 @item .personalityindex @var{index}
817 Sets the personality routine for the current function to the EABI standard
818 routine number @var{index}
820 @cindex @code{.pool} directive, ARM
822 This is a synonym for .ltorg.
824 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
825 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
827 @cindex @code{.req} directive, ARM
828 @item @var{name} .req @var{register name}
829 This creates an alias for @var{register name} called @var{name}. For
836 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
839 @cindex @code{.save} directive, ARM
840 @item .save @var{reglist}
841 Generate unwinder annotations to restore the registers in @var{reglist}.
842 The format of @var{reglist} is the same as the corresponding store-multiple
846 @exdent @emph{core registers}
847 .save @{r4, r5, r6, lr@}
848 stmfd sp!, @{r4, r5, r6, lr@}
849 @exdent @emph{FPA registers}
852 @exdent @emph{VFP registers}
853 .save @{d8, d9, d10@}
854 fstmdx sp!, @{d8, d9, d10@}
855 @exdent @emph{iWMMXt registers}
857 wstrd wr11, [sp, #-8]!
858 wstrd wr10, [sp, #-8]!
861 wstrd wr11, [sp, #-8]!
863 wstrd wr10, [sp, #-8]!
867 @cindex @code{.setfp} directive, ARM
868 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
869 Make all unwinder annotations relative to a frame pointer. Without this
870 the unwinder will use offsets from the stack pointer.
872 The syntax of this directive is the same as the @code{add} or @code{mov}
873 instruction used to set the frame pointer. @var{spreg} must be either
874 @code{sp} or mentioned in a previous @code{.movsp} directive.
884 @cindex @code{.secrel32} directive, ARM
885 @item .secrel32 @var{expression} [, @var{expression}]*
886 This directive emits relocations that evaluate to the section-relative
887 offset of each expression's symbol. This directive is only supported
890 @cindex @code{.syntax} directive, ARM
891 @item .syntax [@code{unified} | @code{divided}]
892 This directive sets the Instruction Set Syntax as described in the
893 @ref{ARM-Instruction-Set} section.
895 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
897 @cindex @code{.thumb} directive, ARM
899 This performs the same action as @var{.code 16}.
901 @cindex @code{.thumb_func} directive, ARM
903 This directive specifies that the following symbol is the name of a
904 Thumb encoded function. This information is necessary in order to allow
905 the assembler and linker to generate correct code for interworking
906 between Arm and Thumb instructions and should be used even if
907 interworking is not going to be performed. The presence of this
908 directive also implies @code{.thumb}
910 This directive is not neccessary when generating EABI objects. On these
911 targets the encoding is implicit when generating Thumb code.
913 @cindex @code{.thumb_set} directive, ARM
915 This performs the equivalent of a @code{.set} directive in that it
916 creates a symbol which is an alias for another symbol (possibly not yet
917 defined). This directive also has the added property in that it marks
918 the aliased symbol as being a thumb function entry point, in the same
919 way that the @code{.thumb_func} directive does.
921 @cindex @code{.tlsdescseq} directive, ARM
922 @item .tlsdescseq @var{tls-variable}
923 This directive is used to annotate parts of an inlined TLS descriptor
924 trampoline. Normally the trampoline is provided by the linker, and
925 this directive is not needed.
927 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
929 @cindex @code{.unreq} directive, ARM
930 @item .unreq @var{alias-name}
931 This undefines a register alias which was previously defined using the
932 @code{req}, @code{dn} or @code{qn} directives. For example:
939 An error occurs if the name is undefined. Note - this pseudo op can
940 be used to delete builtin in register name aliases (eg 'r0'). This
941 should only be done if it is really necessary.
943 @cindex @code{.unwind_raw} directive, ARM
944 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
945 Insert one of more arbitary unwind opcode bytes, which are known to adjust
946 the stack pointer by @var{offset} bytes.
948 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
951 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
953 @cindex @code{.vsave} directive, ARM
954 @item .vsave @var{vfp-reglist}
955 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
956 using FLDMD. Also works for VFPv3 registers
957 that are to be restored using VLDM.
958 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
962 @exdent @emph{VFP registers}
963 .vsave @{d8, d9, d10@}
964 fstmdd sp!, @{d8, d9, d10@}
965 @exdent @emph{VFPv3 registers}
966 .vsave @{d15, d16, d17@}
967 vstm sp!, @{d15, d16, d17@}
970 Since FLDMX and FSTMX are now deprecated, this directive should be
971 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
973 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
974 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
975 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
976 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
984 @cindex opcodes for ARM
985 @code{@value{AS}} implements all the standard ARM opcodes. It also
986 implements several pseudo opcodes, including several synthetic load
991 @cindex @code{NOP} pseudo op, ARM
997 This pseudo op will always evaluate to a legal ARM instruction that does
998 nothing. Currently it will evaluate to MOV r0, r0.
1000 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1003 ldr <register> , = <expression>
1006 If expression evaluates to a numeric constant then a MOV or MVN
1007 instruction will be used in place of the LDR instruction, if the
1008 constant can be generated by either of these instructions. Otherwise
1009 the constant will be placed into the nearest literal pool (if it not
1010 already there) and a PC relative LDR instruction will be generated.
1012 @cindex @code{ADR reg,<label>} pseudo op, ARM
1015 adr <register> <label>
1018 This instruction will load the address of @var{label} into the indicated
1019 register. The instruction will evaluate to a PC relative ADD or SUB
1020 instruction depending upon where the label is located. If the label is
1021 out of range, or if it is not defined in the same file (and section) as
1022 the ADR instruction, then an error will be generated. This instruction
1023 will not make use of the literal pool.
1025 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1028 adrl <register> <label>
1031 This instruction will load the address of @var{label} into the indicated
1032 register. The instruction will evaluate to one or two PC relative ADD
1033 or SUB instructions depending upon where the label is located. If a
1034 second instruction is not needed a NOP instruction will be generated in
1035 its place, so that this instruction is always 8 bytes long.
1037 If the label is out of range, or if it is not defined in the same file
1038 (and section) as the ADRL instruction, then an error will be generated.
1039 This instruction will not make use of the literal pool.
1043 For information on the ARM or Thumb instruction sets, see @cite{ARM
1044 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1047 @node ARM Mapping Symbols
1048 @section Mapping Symbols
1050 The ARM ELF specification requires that special symbols be inserted
1051 into object files to mark certain features:
1057 At the start of a region of code containing ARM instructions.
1061 At the start of a region of code containing THUMB instructions.
1065 At the start of a region of data.
1069 The assembler will automatically insert these symbols for you - there
1070 is no need to code them yourself. Support for tagging symbols ($b,
1071 $f, $p and $m) which is also mentioned in the current ARM ELF
1072 specification is not implemented. This is because they have been
1073 dropped from the new EABI and so tools cannot rely upon their
1076 @node ARM Unwinding Tutorial
1079 The ABI for the ARM Architecture specifies a standard format for
1080 exception unwind information. This information is used when an
1081 exception is thrown to determine where control should be transferred.
1082 In particular, the unwind information is used to determine which
1083 function called the function that threw the exception, and which
1084 function called that one, and so forth. This information is also used
1085 to restore the values of callee-saved registers in the function
1086 catching the exception.
1088 If you are writing functions in assembly code, and those functions
1089 call other functions that throw exceptions, you must use assembly
1090 pseudo ops to ensure that appropriate exception unwind information is
1091 generated. Otherwise, if one of the functions called by your assembly
1092 code throws an exception, the run-time library will be unable to
1093 unwind the stack through your assembly code and your program will not
1096 To illustrate the use of these pseudo ops, we will examine the code
1097 that G++ generates for the following C++ input:
1100 void callee (int *);
1111 This example does not show how to throw or catch an exception from
1112 assembly code. That is a much more complex operation and should
1113 always be done in a high-level language, such as C++, that directly
1114 supports exceptions.
1116 The code generated by one particular version of G++ when compiling the
1123 @ Function supports interworking.
1124 @ args = 0, pretend = 0, frame = 8
1125 @ frame_needed = 1, uses_anonymous_args = 0
1147 Of course, the sequence of instructions varies based on the options
1148 you pass to GCC and on the version of GCC in use. The exact
1149 instructions are not important since we are focusing on the pseudo ops
1150 that are used to generate unwind information.
1152 An important assumption made by the unwinder is that the stack frame
1153 does not change during the body of the function. In particular, since
1154 we assume that the assembly code does not itself throw an exception,
1155 the only point where an exception can be thrown is from a call, such
1156 as the @code{bl} instruction above. At each call site, the same saved
1157 registers (including @code{lr}, which indicates the return address)
1158 must be located in the same locations relative to the frame pointer.
1160 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1161 op appears immediately before the first instruction of the function
1162 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1163 op appears immediately after the last instruction of the function.
1164 These pseudo ops specify the range of the function.
1166 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1167 @code{.pad}) matters; their exact locations are irrelevant. In the
1168 example above, the compiler emits the pseudo ops with particular
1169 instructions. That makes it easier to understand the code, but it is
1170 not required for correctness. It would work just as well to emit all
1171 of the pseudo ops other than @code{.fnend} in the same order, but
1172 immediately after @code{.fnstart}.
1174 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1175 indicates registers that have been saved to the stack so that they can
1176 be restored before the function returns. The argument to the
1177 @code{.save} pseudo op is a list of registers to save. If a register
1178 is ``callee-saved'' (as specified by the ABI) and is modified by the
1179 function you are writing, then your code must save the value before it
1180 is modified and restore the original value before the function
1181 returns. If an exception is thrown, the run-time library restores the
1182 values of these registers from their locations on the stack before
1183 returning control to the exception handler. (Of course, if an
1184 exception is not thrown, the function that contains the @code{.save}
1185 pseudo op restores these registers in the function epilogue, as is
1186 done with the @code{ldmfd} instruction above.)
1188 You do not have to save callee-saved registers at the very beginning
1189 of the function and you do not need to use the @code{.save} pseudo op
1190 immediately following the point at which the registers are saved.
1191 However, if you modify a callee-saved register, you must save it on
1192 the stack before modifying it and before calling any functions which
1193 might throw an exception. And, you must use the @code{.save} pseudo
1194 op to indicate that you have done so.
1196 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1197 modification of the stack pointer that does not save any registers.
1198 The argument is the number of bytes (in decimal) that are subtracted
1199 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1200 subtracting from the stack pointer increases the size of the stack.)
1202 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1203 indicates the register that contains the frame pointer. The first
1204 argument is the register that is set, which is typically @code{fp}.
1205 The second argument indicates the register from which the frame
1206 pointer takes its value. The third argument, if present, is the value
1207 (in decimal) added to the register specified by the second argument to
1208 compute the value of the frame pointer. You should not modify the
1209 frame pointer in the body of the function.
1211 If you do not use a frame pointer, then you should not use the
1212 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1213 should avoid modifying the stack pointer outside of the function
1214 prologue. Otherwise, the run-time library will be unable to find
1215 saved registers when it is unwinding the stack.
1217 The pseudo ops described above are sufficient for writing assembly
1218 code that calls functions which may throw exceptions. If you need to
1219 know more about the object-file format used to represent unwind
1220 information, you may consult the @cite{Exception Handling ABI for the
1221 ARM Architecture} available from @uref{http://infocenter.arm.com}.