1 @c Copyright (C) 1996-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
135 @code{cortex-m0plus},
138 @code{marvell-whitney},
142 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
143 @code{i80200} (Intel XScale processor)
144 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
147 The special name @code{all} may be used to allow the
148 assembler to accept instructions valid for any ARM processor.
150 In addition to the basic instruction set, the assembler can be told to
151 accept various extension mnemonics that extend the processor using the
152 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
153 is equivalent to specifying @code{-mcpu=ep9312}.
155 Multiple extensions may be specified, separated by a @code{+}. The
156 extensions should be specified in ascending alphabetical order.
158 Some extensions may be restricted to particular architectures; this is
159 documented in the list of extensions below.
161 Extension mnemonics may also be removed from those the assembler accepts.
162 This is done be prepending @code{no} to the option that adds the extension.
163 Extensions that are removed should be listed after all extensions which have
164 been added, again in ascending alphabetical order. For example,
165 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
168 The following extensions are currently supported:
170 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
171 @code{fp} (Floating Point Extensions for v8-A architecture),
172 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
177 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
179 @code{os} (Operating System for v6M architecture),
180 @code{sec} (Security Extensions for v6K and v7-A architectures),
181 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
182 @code{virt} (Virtualization Extensions for v7-A architecture, implies
184 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
185 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
190 @cindex @code{-march=} command line option, ARM
191 @item -march=@var{architecture}[+@var{extension}@dots{}]
192 This option specifies the target architecture. The assembler will issue
193 an error message if an attempt is made to assemble an instruction which
194 will not execute on the target architecture. The following architecture
195 names are recognized:
231 If both @code{-mcpu} and
232 @code{-march} are specified, the assembler will use
233 the setting for @code{-mcpu}.
235 The architecture option can be extended with the same instruction set
236 extension options as the @code{-mcpu} option.
238 @cindex @code{-mfpu=} command line option, ARM
239 @item -mfpu=@var{floating-point-format}
241 This option specifies the floating point format to assemble for. The
242 assembler will issue an error message if an attempt is made to assemble
243 an instruction which will not execute on the target floating point unit.
244 The following format options are recognized:
264 @code{vfpv3-d16-fp16},
279 @code{neon-fp-armv8},
280 @code{crypto-neon-fp-armv8},
281 @code{neon-fp-armv8.1}
283 @code{crypto-neon-fp-armv8.1}.
285 In addition to determining which instructions are assembled, this option
286 also affects the way in which the @code{.double} assembler directive behaves
287 when assembling little-endian code.
289 The default is dependent on the processor selected. For Architecture 5 or
290 later, the default is to assembler for VFP instructions; for earlier
291 architectures the default is to assemble for FPA instructions.
293 @cindex @code{-mthumb} command line option, ARM
295 This option specifies that the assembler should start assembling Thumb
296 instructions; that is, it should behave as though the file starts with a
297 @code{.code 16} directive.
299 @cindex @code{-mthumb-interwork} command line option, ARM
300 @item -mthumb-interwork
301 This option specifies that the output generated by the assembler should
302 be marked as supporting interworking.
304 @cindex @code{-mimplicit-it} command line option, ARM
305 @item -mimplicit-it=never
306 @itemx -mimplicit-it=always
307 @itemx -mimplicit-it=arm
308 @itemx -mimplicit-it=thumb
309 The @code{-mimplicit-it} option controls the behavior of the assembler when
310 conditional instructions are not enclosed in IT blocks.
311 There are four possible behaviors.
312 If @code{never} is specified, such constructs cause a warning in ARM
313 code and an error in Thumb-2 code.
314 If @code{always} is specified, such constructs are accepted in both
315 ARM and Thumb-2 code, where the IT instruction is added implicitly.
316 If @code{arm} is specified, such constructs are accepted in ARM code
317 and cause an error in Thumb-2 code.
318 If @code{thumb} is specified, such constructs cause a warning in ARM
319 code and are accepted in Thumb-2 code. If you omit this option, the
320 behavior is equivalent to @code{-mimplicit-it=arm}.
322 @cindex @code{-mapcs-26} command line option, ARM
323 @cindex @code{-mapcs-32} command line option, ARM
326 These options specify that the output generated by the assembler should
327 be marked as supporting the indicated version of the Arm Procedure.
330 @cindex @code{-matpcs} command line option, ARM
332 This option specifies that the output generated by the assembler should
333 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
334 enabled this option will cause the assembler to create an empty
335 debugging section in the object file called .arm.atpcs. Debuggers can
336 use this to determine the ABI being used by.
338 @cindex @code{-mapcs-float} command line option, ARM
340 This indicates the floating point variant of the APCS should be
341 used. In this variant floating point arguments are passed in FP
342 registers rather than integer registers.
344 @cindex @code{-mapcs-reentrant} command line option, ARM
345 @item -mapcs-reentrant
346 This indicates that the reentrant variant of the APCS should be used.
347 This variant supports position independent code.
349 @cindex @code{-mfloat-abi=} command line option, ARM
350 @item -mfloat-abi=@var{abi}
351 This option specifies that the output generated by the assembler should be
352 marked as using specified floating point ABI.
353 The following values are recognized:
359 @cindex @code{-eabi=} command line option, ARM
360 @item -meabi=@var{ver}
361 This option specifies which EABI version the produced object files should
363 The following values are recognized:
369 @cindex @code{-EB} command line option, ARM
371 This option specifies that the output generated by the assembler should
372 be marked as being encoded for a big-endian processor.
374 Note: If a program is being built for a system with big-endian data
375 and little-endian instructions then it should be assembled with the
376 @option{-EB} option, (all of it, code and data) and then linked with
377 the @option{--be8} option. This will reverse the endianness of the
378 instructions back to little-endian, but leave the data as big-endian.
380 @cindex @code{-EL} command line option, ARM
382 This option specifies that the output generated by the assembler should
383 be marked as being encoded for a little-endian processor.
385 @cindex @code{-k} command line option, ARM
386 @cindex PIC code generation for ARM
388 This option specifies that the output of the assembler should be marked
389 as position-independent code (PIC).
391 @cindex @code{--fix-v4bx} command line option, ARM
393 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
394 the linker option of the same name.
396 @cindex @code{-mwarn-deprecated} command line option, ARM
397 @item -mwarn-deprecated
398 @itemx -mno-warn-deprecated
399 Enable or disable warnings about using deprecated options or
400 features. The default is to warn.
402 @cindex @code{-mccs} command line option, ARM
404 Turns on CodeComposer Studio assembly syntax compatibility mode.
406 @cindex @code{-mwarn-syms} command line option, ARM
408 @itemx -mno-warn-syms
409 Enable or disable warnings about symbols that match the names of ARM
410 instructions. The default is to warn.
418 * ARM-Instruction-Set:: Instruction Set
419 * ARM-Chars:: Special Characters
420 * ARM-Regs:: Register Names
421 * ARM-Relocations:: Relocations
422 * ARM-Neon-Alignment:: NEON Alignment Specifiers
425 @node ARM-Instruction-Set
426 @subsection Instruction Set Syntax
427 Two slightly different syntaxes are support for ARM and THUMB
428 instructions. The default, @code{divided}, uses the old style where
429 ARM and THUMB instructions had their own, separate syntaxes. The new,
430 @code{unified} syntax, which can be selected via the @code{.syntax}
431 directive, and has the following main features:
435 Immediate operands do not require a @code{#} prefix.
438 The @code{IT} instruction may appear, and if it does it is validated
439 against subsequent conditional affixes. In ARM mode it does not
440 generate machine code, in THUMB mode it does.
443 For ARM instructions the conditional affixes always appear at the end
444 of the instruction. For THUMB instructions conditional affixes can be
445 used, but only inside the scope of an @code{IT} instruction.
448 All of the instructions new to the V6T2 architecture (and later) are
449 available. (Only a few such instructions can be written in the
450 @code{divided} syntax).
453 The @code{.N} and @code{.W} suffixes are recognized and honored.
456 All instructions set the flags if and only if they have an @code{s}
461 @subsection Special Characters
463 @cindex line comment character, ARM
464 @cindex ARM line comment character
465 The presence of a @samp{@@} anywhere on a line indicates the start of
466 a comment that extends to the end of that line.
468 If a @samp{#} appears as the first character of a line then the whole
469 line is treated as a comment, but in this case the line could also be
470 a logical line number directive (@pxref{Comments}) or a preprocessor
471 control command (@pxref{Preprocessing}).
473 @cindex line separator, ARM
474 @cindex statement separator, ARM
475 @cindex ARM line separator
476 The @samp{;} character can be used instead of a newline to separate
479 @cindex immediate character, ARM
480 @cindex ARM immediate character
481 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
483 @cindex identifiers, ARM
484 @cindex ARM identifiers
485 *TODO* Explain about /data modifier on symbols.
488 @subsection Register Names
490 @cindex ARM register names
491 @cindex register names, ARM
492 *TODO* Explain about ARM register naming, and the predefined names.
494 @node ARM-Relocations
495 @subsection ARM relocation generation
497 @cindex data relocations, ARM
498 @cindex ARM data relocations
499 Specific data relocations can be generated by putting the relocation name
500 in parentheses after the symbol name. For example:
506 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
508 The following relocations are supported:
524 For compatibility with older toolchains the assembler also accepts
525 @code{(PLT)} after branch targets. On legacy targets this will
526 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
527 targets it will encode either the @samp{R_ARM_CALL} or
528 @samp{R_ARM_JUMP24} relocation, as appropriate.
530 @cindex MOVW and MOVT relocations, ARM
531 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
532 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
533 respectively. For example to load the 32-bit address of foo into r0:
536 MOVW r0, #:lower16:foo
537 MOVT r0, #:upper16:foo
540 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
541 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
542 generated by prefixing the value with @samp{#:lower0_7:#},
543 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
544 respectively. For example to load the 32-bit address of foo into r0:
547 MOVS r0, #:upper8_15:#foo
549 ADDS r0, #:upper0_7:#foo
551 ADDS r0, #:lower8_15:#foo
553 ADDS r0, #:lower0_7:#foo
556 @node ARM-Neon-Alignment
557 @subsection NEON Alignment Specifiers
559 @cindex alignment for NEON instructions
560 Some NEON load/store instructions allow an optional address
562 The ARM documentation specifies that this is indicated by
563 @samp{@@ @var{align}}. However GAS already interprets
564 the @samp{@@} character as a "line comment" start,
565 so @samp{: @var{align}} is used instead. For example:
568 vld1.8 @{q0@}, [r0, :128]
571 @node ARM Floating Point
572 @section Floating Point
574 @cindex floating point, ARM (@sc{ieee})
575 @cindex ARM floating point (@sc{ieee})
576 The ARM family uses @sc{ieee} floating-point numbers.
579 @section ARM Machine Directives
581 @cindex machine directives, ARM
582 @cindex ARM machine directives
585 @c AAAAAAAAAAAAAAAAAAAAAAAAA
587 @cindex @code{.2byte} directive, ARM
588 @cindex @code{.4byte} directive, ARM
589 @cindex @code{.8byte} directive, ARM
590 @item .2byte @var{expression} [, @var{expression}]*
591 @itemx .4byte @var{expression} [, @var{expression}]*
592 @itemx .8byte @var{expression} [, @var{expression}]*
593 These directives write 2, 4 or 8 byte values to the output section.
595 @cindex @code{.align} directive, ARM
596 @item .align @var{expression} [, @var{expression}]
597 This is the generic @var{.align} directive. For the ARM however if the
598 first argument is zero (ie no alignment is needed) the assembler will
599 behave as if the argument had been 2 (ie pad to the next four byte
600 boundary). This is for compatibility with ARM's own assembler.
602 @cindex @code{.arch} directive, ARM
603 @item .arch @var{name}
604 Select the target architecture. Valid values for @var{name} are the same as
605 for the @option{-march} commandline option.
607 Specifying @code{.arch} clears any previously selected architecture
610 @cindex @code{.arch_extension} directive, ARM
611 @item .arch_extension @var{name}
612 Add or remove an architecture extension to the target architecture. Valid
613 values for @var{name} are the same as those accepted as architectural
614 extensions by the @option{-mcpu} commandline option.
616 @code{.arch_extension} may be used multiple times to add or remove extensions
617 incrementally to the architecture being compiled for.
619 @cindex @code{.arm} directive, ARM
621 This performs the same action as @var{.code 32}.
623 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
625 @cindex @code{.bss} directive, ARM
627 This directive switches to the @code{.bss} section.
629 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
631 @cindex @code{.cantunwind} directive, ARM
633 Prevents unwinding through the current function. No personality routine
634 or exception table data is required or permitted.
636 @cindex @code{.code} directive, ARM
637 @item .code @code{[16|32]}
638 This directive selects the instruction set being generated. The value 16
639 selects Thumb, with the value 32 selecting ARM.
641 @cindex @code{.cpu} directive, ARM
642 @item .cpu @var{name}
643 Select the target processor. Valid values for @var{name} are the same as
644 for the @option{-mcpu} commandline option.
646 Specifying @code{.cpu} clears any previously selected architecture
649 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
651 @cindex @code{.dn} and @code{.qn} directives, ARM
652 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
653 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
655 The @code{dn} and @code{qn} directives are used to create typed
656 and/or indexed register aliases for use in Advanced SIMD Extension
657 (Neon) instructions. The former should be used to create aliases
658 of double-precision registers, and the latter to create aliases of
659 quad-precision registers.
661 If these directives are used to create typed aliases, those aliases can
662 be used in Neon instructions instead of writing types after the mnemonic
663 or after each operand. For example:
672 This is equivalent to writing the following:
678 Aliases created using @code{dn} or @code{qn} can be destroyed using
681 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
683 @cindex @code{.eabi_attribute} directive, ARM
684 @item .eabi_attribute @var{tag}, @var{value}
685 Set the EABI object attribute @var{tag} to @var{value}.
687 The @var{tag} is either an attribute number, or one of the following:
688 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
689 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
690 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
691 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
692 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
693 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
694 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
695 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
696 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
697 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
698 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
699 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
700 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
701 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
702 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
703 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
704 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
705 @code{Tag_conformance}, @code{Tag_T2EE_use},
706 @code{Tag_Virtualization_use}
708 The @var{value} is either a @code{number}, @code{"string"}, or
709 @code{number, "string"} depending on the tag.
711 Note - the following legacy values are also accepted by @var{tag}:
712 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
713 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
715 @cindex @code{.even} directive, ARM
717 This directive aligns to an even-numbered address.
719 @cindex @code{.extend} directive, ARM
720 @cindex @code{.ldouble} directive, ARM
721 @item .extend @var{expression} [, @var{expression}]*
722 @itemx .ldouble @var{expression} [, @var{expression}]*
723 These directives write 12byte long double floating-point values to the
724 output section. These are not compatible with current ARM processors
727 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
730 @cindex @code{.fnend} directive, ARM
732 Marks the end of a function with an unwind table entry. The unwind index
733 table entry is created when this directive is processed.
735 If no personality routine has been specified then standard personality
736 routine 0 or 1 will be used, depending on the number of unwind opcodes
740 @cindex @code{.fnstart} directive, ARM
742 Marks the start of a function with an unwind table entry.
744 @cindex @code{.force_thumb} directive, ARM
746 This directive forces the selection of Thumb instructions, even if the
747 target processor does not support those instructions
749 @cindex @code{.fpu} directive, ARM
750 @item .fpu @var{name}
751 Select the floating-point unit to assemble for. Valid values for @var{name}
752 are the same as for the @option{-mfpu} commandline option.
754 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
755 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
757 @cindex @code{.handlerdata} directive, ARM
759 Marks the end of the current function, and the start of the exception table
760 entry for that function. Anything between this directive and the
761 @code{.fnend} directive will be added to the exception table entry.
763 Must be preceded by a @code{.personality} or @code{.personalityindex}
766 @c IIIIIIIIIIIIIIIIIIIIIIIIII
768 @cindex @code{.inst} directive, ARM
769 @item .inst @var{opcode} [ , @dots{} ]
770 @itemx .inst.n @var{opcode} [ , @dots{} ]
771 @itemx .inst.w @var{opcode} [ , @dots{} ]
772 Generates the instruction corresponding to the numerical value @var{opcode}.
773 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
774 specified explicitly, overriding the normal encoding rules.
776 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
777 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
778 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
780 @item .ldouble @var{expression} [, @var{expression}]*
783 @cindex @code{.ltorg} directive, ARM
785 This directive causes the current contents of the literal pool to be
786 dumped into the current section (which is assumed to be the .text
787 section) at the current location (aligned to a word boundary).
788 @code{GAS} maintains a separate literal pool for each section and each
789 sub-section. The @code{.ltorg} directive will only affect the literal
790 pool of the current section and sub-section. At the end of assembly
791 all remaining, un-empty literal pools will automatically be dumped.
793 Note - older versions of @code{GAS} would dump the current literal
794 pool any time a section change occurred. This is no longer done, since
795 it prevents accurate control of the placement of literal pools.
797 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
799 @cindex @code{.movsp} directive, ARM
800 @item .movsp @var{reg} [, #@var{offset}]
801 Tell the unwinder that @var{reg} contains an offset from the current
802 stack pointer. If @var{offset} is not specified then it is assumed to be
805 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
806 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
808 @cindex @code{.object_arch} directive, ARM
809 @item .object_arch @var{name}
810 Override the architecture recorded in the EABI object attribute section.
811 Valid values for @var{name} are the same as for the @code{.arch} directive.
812 Typically this is useful when code uses runtime detection of CPU features.
814 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
816 @cindex @code{.packed} directive, ARM
817 @item .packed @var{expression} [, @var{expression}]*
818 This directive writes 12-byte packed floating-point values to the
819 output section. These are not compatible with current ARM processors
823 @cindex @code{.pad} directive, ARM
824 @item .pad #@var{count}
825 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
826 A positive value indicates the function prologue allocated stack space by
827 decrementing the stack pointer.
829 @cindex @code{.personality} directive, ARM
830 @item .personality @var{name}
831 Sets the personality routine for the current function to @var{name}.
833 @cindex @code{.personalityindex} directive, ARM
834 @item .personalityindex @var{index}
835 Sets the personality routine for the current function to the EABI standard
836 routine number @var{index}
838 @cindex @code{.pool} directive, ARM
840 This is a synonym for .ltorg.
842 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
843 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
845 @cindex @code{.req} directive, ARM
846 @item @var{name} .req @var{register name}
847 This creates an alias for @var{register name} called @var{name}. For
854 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
857 @cindex @code{.save} directive, ARM
858 @item .save @var{reglist}
859 Generate unwinder annotations to restore the registers in @var{reglist}.
860 The format of @var{reglist} is the same as the corresponding store-multiple
864 @exdent @emph{core registers}
865 .save @{r4, r5, r6, lr@}
866 stmfd sp!, @{r4, r5, r6, lr@}
867 @exdent @emph{FPA registers}
870 @exdent @emph{VFP registers}
871 .save @{d8, d9, d10@}
872 fstmdx sp!, @{d8, d9, d10@}
873 @exdent @emph{iWMMXt registers}
875 wstrd wr11, [sp, #-8]!
876 wstrd wr10, [sp, #-8]!
879 wstrd wr11, [sp, #-8]!
881 wstrd wr10, [sp, #-8]!
885 @cindex @code{.setfp} directive, ARM
886 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
887 Make all unwinder annotations relative to a frame pointer. Without this
888 the unwinder will use offsets from the stack pointer.
890 The syntax of this directive is the same as the @code{add} or @code{mov}
891 instruction used to set the frame pointer. @var{spreg} must be either
892 @code{sp} or mentioned in a previous @code{.movsp} directive.
902 @cindex @code{.secrel32} directive, ARM
903 @item .secrel32 @var{expression} [, @var{expression}]*
904 This directive emits relocations that evaluate to the section-relative
905 offset of each expression's symbol. This directive is only supported
908 @cindex @code{.syntax} directive, ARM
909 @item .syntax [@code{unified} | @code{divided}]
910 This directive sets the Instruction Set Syntax as described in the
911 @ref{ARM-Instruction-Set} section.
913 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
915 @cindex @code{.thumb} directive, ARM
917 This performs the same action as @var{.code 16}.
919 @cindex @code{.thumb_func} directive, ARM
921 This directive specifies that the following symbol is the name of a
922 Thumb encoded function. This information is necessary in order to allow
923 the assembler and linker to generate correct code for interworking
924 between Arm and Thumb instructions and should be used even if
925 interworking is not going to be performed. The presence of this
926 directive also implies @code{.thumb}
928 This directive is not neccessary when generating EABI objects. On these
929 targets the encoding is implicit when generating Thumb code.
931 @cindex @code{.thumb_set} directive, ARM
933 This performs the equivalent of a @code{.set} directive in that it
934 creates a symbol which is an alias for another symbol (possibly not yet
935 defined). This directive also has the added property in that it marks
936 the aliased symbol as being a thumb function entry point, in the same
937 way that the @code{.thumb_func} directive does.
939 @cindex @code{.tlsdescseq} directive, ARM
940 @item .tlsdescseq @var{tls-variable}
941 This directive is used to annotate parts of an inlined TLS descriptor
942 trampoline. Normally the trampoline is provided by the linker, and
943 this directive is not needed.
945 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
947 @cindex @code{.unreq} directive, ARM
948 @item .unreq @var{alias-name}
949 This undefines a register alias which was previously defined using the
950 @code{req}, @code{dn} or @code{qn} directives. For example:
957 An error occurs if the name is undefined. Note - this pseudo op can
958 be used to delete builtin in register name aliases (eg 'r0'). This
959 should only be done if it is really necessary.
961 @cindex @code{.unwind_raw} directive, ARM
962 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
963 Insert one of more arbitary unwind opcode bytes, which are known to adjust
964 the stack pointer by @var{offset} bytes.
966 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
969 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
971 @cindex @code{.vsave} directive, ARM
972 @item .vsave @var{vfp-reglist}
973 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
974 using FLDMD. Also works for VFPv3 registers
975 that are to be restored using VLDM.
976 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
980 @exdent @emph{VFP registers}
981 .vsave @{d8, d9, d10@}
982 fstmdd sp!, @{d8, d9, d10@}
983 @exdent @emph{VFPv3 registers}
984 .vsave @{d15, d16, d17@}
985 vstm sp!, @{d15, d16, d17@}
988 Since FLDMX and FSTMX are now deprecated, this directive should be
989 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
991 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
992 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
993 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
994 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1002 @cindex opcodes for ARM
1003 @code{@value{AS}} implements all the standard ARM opcodes. It also
1004 implements several pseudo opcodes, including several synthetic load
1009 @cindex @code{NOP} pseudo op, ARM
1015 This pseudo op will always evaluate to a legal ARM instruction that does
1016 nothing. Currently it will evaluate to MOV r0, r0.
1018 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1021 ldr <register> , = <expression>
1024 If expression evaluates to a numeric constant then a MOV or MVN
1025 instruction will be used in place of the LDR instruction, if the
1026 constant can be generated by either of these instructions. Otherwise
1027 the constant will be placed into the nearest literal pool (if it not
1028 already there) and a PC relative LDR instruction will be generated.
1030 @cindex @code{ADR reg,<label>} pseudo op, ARM
1033 adr <register> <label>
1036 This instruction will load the address of @var{label} into the indicated
1037 register. The instruction will evaluate to a PC relative ADD or SUB
1038 instruction depending upon where the label is located. If the label is
1039 out of range, or if it is not defined in the same file (and section) as
1040 the ADR instruction, then an error will be generated. This instruction
1041 will not make use of the literal pool.
1043 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1046 adrl <register> <label>
1049 This instruction will load the address of @var{label} into the indicated
1050 register. The instruction will evaluate to one or two PC relative ADD
1051 or SUB instructions depending upon where the label is located. If a
1052 second instruction is not needed a NOP instruction will be generated in
1053 its place, so that this instruction is always 8 bytes long.
1055 If the label is out of range, or if it is not defined in the same file
1056 (and section) as the ADRL instruction, then an error will be generated.
1057 This instruction will not make use of the literal pool.
1061 For information on the ARM or Thumb instruction sets, see @cite{ARM
1062 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1065 @node ARM Mapping Symbols
1066 @section Mapping Symbols
1068 The ARM ELF specification requires that special symbols be inserted
1069 into object files to mark certain features:
1075 At the start of a region of code containing ARM instructions.
1079 At the start of a region of code containing THUMB instructions.
1083 At the start of a region of data.
1087 The assembler will automatically insert these symbols for you - there
1088 is no need to code them yourself. Support for tagging symbols ($b,
1089 $f, $p and $m) which is also mentioned in the current ARM ELF
1090 specification is not implemented. This is because they have been
1091 dropped from the new EABI and so tools cannot rely upon their
1094 @node ARM Unwinding Tutorial
1097 The ABI for the ARM Architecture specifies a standard format for
1098 exception unwind information. This information is used when an
1099 exception is thrown to determine where control should be transferred.
1100 In particular, the unwind information is used to determine which
1101 function called the function that threw the exception, and which
1102 function called that one, and so forth. This information is also used
1103 to restore the values of callee-saved registers in the function
1104 catching the exception.
1106 If you are writing functions in assembly code, and those functions
1107 call other functions that throw exceptions, you must use assembly
1108 pseudo ops to ensure that appropriate exception unwind information is
1109 generated. Otherwise, if one of the functions called by your assembly
1110 code throws an exception, the run-time library will be unable to
1111 unwind the stack through your assembly code and your program will not
1114 To illustrate the use of these pseudo ops, we will examine the code
1115 that G++ generates for the following C++ input:
1118 void callee (int *);
1129 This example does not show how to throw or catch an exception from
1130 assembly code. That is a much more complex operation and should
1131 always be done in a high-level language, such as C++, that directly
1132 supports exceptions.
1134 The code generated by one particular version of G++ when compiling the
1141 @ Function supports interworking.
1142 @ args = 0, pretend = 0, frame = 8
1143 @ frame_needed = 1, uses_anonymous_args = 0
1165 Of course, the sequence of instructions varies based on the options
1166 you pass to GCC and on the version of GCC in use. The exact
1167 instructions are not important since we are focusing on the pseudo ops
1168 that are used to generate unwind information.
1170 An important assumption made by the unwinder is that the stack frame
1171 does not change during the body of the function. In particular, since
1172 we assume that the assembly code does not itself throw an exception,
1173 the only point where an exception can be thrown is from a call, such
1174 as the @code{bl} instruction above. At each call site, the same saved
1175 registers (including @code{lr}, which indicates the return address)
1176 must be located in the same locations relative to the frame pointer.
1178 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1179 op appears immediately before the first instruction of the function
1180 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1181 op appears immediately after the last instruction of the function.
1182 These pseudo ops specify the range of the function.
1184 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1185 @code{.pad}) matters; their exact locations are irrelevant. In the
1186 example above, the compiler emits the pseudo ops with particular
1187 instructions. That makes it easier to understand the code, but it is
1188 not required for correctness. It would work just as well to emit all
1189 of the pseudo ops other than @code{.fnend} in the same order, but
1190 immediately after @code{.fnstart}.
1192 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1193 indicates registers that have been saved to the stack so that they can
1194 be restored before the function returns. The argument to the
1195 @code{.save} pseudo op is a list of registers to save. If a register
1196 is ``callee-saved'' (as specified by the ABI) and is modified by the
1197 function you are writing, then your code must save the value before it
1198 is modified and restore the original value before the function
1199 returns. If an exception is thrown, the run-time library restores the
1200 values of these registers from their locations on the stack before
1201 returning control to the exception handler. (Of course, if an
1202 exception is not thrown, the function that contains the @code{.save}
1203 pseudo op restores these registers in the function epilogue, as is
1204 done with the @code{ldmfd} instruction above.)
1206 You do not have to save callee-saved registers at the very beginning
1207 of the function and you do not need to use the @code{.save} pseudo op
1208 immediately following the point at which the registers are saved.
1209 However, if you modify a callee-saved register, you must save it on
1210 the stack before modifying it and before calling any functions which
1211 might throw an exception. And, you must use the @code{.save} pseudo
1212 op to indicate that you have done so.
1214 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1215 modification of the stack pointer that does not save any registers.
1216 The argument is the number of bytes (in decimal) that are subtracted
1217 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1218 subtracting from the stack pointer increases the size of the stack.)
1220 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1221 indicates the register that contains the frame pointer. The first
1222 argument is the register that is set, which is typically @code{fp}.
1223 The second argument indicates the register from which the frame
1224 pointer takes its value. The third argument, if present, is the value
1225 (in decimal) added to the register specified by the second argument to
1226 compute the value of the frame pointer. You should not modify the
1227 frame pointer in the body of the function.
1229 If you do not use a frame pointer, then you should not use the
1230 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1231 should avoid modifying the stack pointer outside of the function
1232 prologue. Otherwise, the run-time library will be unable to find
1233 saved registers when it is unwinding the stack.
1235 The pseudo ops described above are sufficient for writing assembly
1236 code that calls functions which may throw exceptions. If you need to
1237 know more about the object-file format used to represent unwind
1238 information, you may consult the @cite{Exception Handling ABI for the
1239 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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