1 @c Copyright (C) 1996-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
145 @code{cortex-m0plus},
148 @code{marvell-whitney},
151 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
152 @code{i80200} (Intel XScale processor)
153 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
156 The special name @code{all} may be used to allow the
157 assembler to accept instructions valid for any ARM processor.
159 In addition to the basic instruction set, the assembler can be told to
160 accept various extension mnemonics that extend the processor using the
161 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
162 is equivalent to specifying @code{-mcpu=ep9312}.
164 Multiple extensions may be specified, separated by a @code{+}. The
165 extensions should be specified in ascending alphabetical order.
167 Some extensions may be restricted to particular architectures; this is
168 documented in the list of extensions below.
170 Extension mnemonics may also be removed from those the assembler accepts.
171 This is done be prepending @code{no} to the option that adds the extension.
172 Extensions that are removed should be listed after all extensions which have
173 been added, again in ascending alphabetical order. For example,
174 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
177 The following extensions are currently supported:
179 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
180 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
181 @code{fp} (Floating Point Extensions for v8-A architecture),
182 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
183 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
184 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
189 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
191 @code{os} (Operating System for v6M architecture),
192 @code{predres} (Execution and Data Prediction Restriction Instruction for
193 v8-A architectures, added by default from v8.5-A),
194 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
195 default from v8.5-A),
196 @code{sec} (Security Extensions for v6K and v7-A architectures),
197 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
198 @code{virt} (Virtualization Extensions for v7-A architecture, implies
200 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
201 @code{ras} (Reliability, Availability and Serviceability extensions
202 for v8-A architecture),
203 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
208 @cindex @code{-march=} command-line option, ARM
209 @item -march=@var{architecture}[+@var{extension}@dots{}]
210 This option specifies the target architecture. The assembler will issue
211 an error message if an attempt is made to assemble an instruction which
212 will not execute on the target architecture. The following architecture
213 names are recognized:
253 If both @code{-mcpu} and
254 @code{-march} are specified, the assembler will use
255 the setting for @code{-mcpu}.
257 The architecture option can be extended with the same instruction set
258 extension options as the @code{-mcpu} option.
260 @cindex @code{-mfpu=} command-line option, ARM
261 @item -mfpu=@var{floating-point-format}
263 This option specifies the floating point format to assemble for. The
264 assembler will issue an error message if an attempt is made to assemble
265 an instruction which will not execute on the target floating point unit.
266 The following format options are recognized:
286 @code{vfpv3-d16-fp16},
303 @code{neon-fp-armv8},
304 @code{crypto-neon-fp-armv8},
305 @code{neon-fp-armv8.1}
307 @code{crypto-neon-fp-armv8.1}.
309 In addition to determining which instructions are assembled, this option
310 also affects the way in which the @code{.double} assembler directive behaves
311 when assembling little-endian code.
313 The default is dependent on the processor selected. For Architecture 5 or
314 later, the default is to assemble for VFP instructions; for earlier
315 architectures the default is to assemble for FPA instructions.
317 @cindex @code{-mthumb} command-line option, ARM
319 This option specifies that the assembler should start assembling Thumb
320 instructions; that is, it should behave as though the file starts with a
321 @code{.code 16} directive.
323 @cindex @code{-mthumb-interwork} command-line option, ARM
324 @item -mthumb-interwork
325 This option specifies that the output generated by the assembler should
326 be marked as supporting interworking. It also affects the behaviour
327 of the @code{ADR} and @code{ADRL} pseudo opcodes.
329 @cindex @code{-mimplicit-it} command-line option, ARM
330 @item -mimplicit-it=never
331 @itemx -mimplicit-it=always
332 @itemx -mimplicit-it=arm
333 @itemx -mimplicit-it=thumb
334 The @code{-mimplicit-it} option controls the behavior of the assembler when
335 conditional instructions are not enclosed in IT blocks.
336 There are four possible behaviors.
337 If @code{never} is specified, such constructs cause a warning in ARM
338 code and an error in Thumb-2 code.
339 If @code{always} is specified, such constructs are accepted in both
340 ARM and Thumb-2 code, where the IT instruction is added implicitly.
341 If @code{arm} is specified, such constructs are accepted in ARM code
342 and cause an error in Thumb-2 code.
343 If @code{thumb} is specified, such constructs cause a warning in ARM
344 code and are accepted in Thumb-2 code. If you omit this option, the
345 behavior is equivalent to @code{-mimplicit-it=arm}.
347 @cindex @code{-mapcs-26} command-line option, ARM
348 @cindex @code{-mapcs-32} command-line option, ARM
351 These options specify that the output generated by the assembler should
352 be marked as supporting the indicated version of the Arm Procedure.
355 @cindex @code{-matpcs} command-line option, ARM
357 This option specifies that the output generated by the assembler should
358 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
359 enabled this option will cause the assembler to create an empty
360 debugging section in the object file called .arm.atpcs. Debuggers can
361 use this to determine the ABI being used by.
363 @cindex @code{-mapcs-float} command-line option, ARM
365 This indicates the floating point variant of the APCS should be
366 used. In this variant floating point arguments are passed in FP
367 registers rather than integer registers.
369 @cindex @code{-mapcs-reentrant} command-line option, ARM
370 @item -mapcs-reentrant
371 This indicates that the reentrant variant of the APCS should be used.
372 This variant supports position independent code.
374 @cindex @code{-mfloat-abi=} command-line option, ARM
375 @item -mfloat-abi=@var{abi}
376 This option specifies that the output generated by the assembler should be
377 marked as using specified floating point ABI.
378 The following values are recognized:
384 @cindex @code{-eabi=} command-line option, ARM
385 @item -meabi=@var{ver}
386 This option specifies which EABI version the produced object files should
388 The following values are recognized:
394 @cindex @code{-EB} command-line option, ARM
396 This option specifies that the output generated by the assembler should
397 be marked as being encoded for a big-endian processor.
399 Note: If a program is being built for a system with big-endian data
400 and little-endian instructions then it should be assembled with the
401 @option{-EB} option, (all of it, code and data) and then linked with
402 the @option{--be8} option. This will reverse the endianness of the
403 instructions back to little-endian, but leave the data as big-endian.
405 @cindex @code{-EL} command-line option, ARM
407 This option specifies that the output generated by the assembler should
408 be marked as being encoded for a little-endian processor.
410 @cindex @code{-k} command-line option, ARM
411 @cindex PIC code generation for ARM
413 This option specifies that the output of the assembler should be marked
414 as position-independent code (PIC).
416 @cindex @code{--fix-v4bx} command-line option, ARM
418 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
419 the linker option of the same name.
421 @cindex @code{-mwarn-deprecated} command-line option, ARM
422 @item -mwarn-deprecated
423 @itemx -mno-warn-deprecated
424 Enable or disable warnings about using deprecated options or
425 features. The default is to warn.
427 @cindex @code{-mccs} command-line option, ARM
429 Turns on CodeComposer Studio assembly syntax compatibility mode.
431 @cindex @code{-mwarn-syms} command-line option, ARM
433 @itemx -mno-warn-syms
434 Enable or disable warnings about symbols that match the names of ARM
435 instructions. The default is to warn.
443 * ARM-Instruction-Set:: Instruction Set
444 * ARM-Chars:: Special Characters
445 * ARM-Regs:: Register Names
446 * ARM-Relocations:: Relocations
447 * ARM-Neon-Alignment:: NEON Alignment Specifiers
450 @node ARM-Instruction-Set
451 @subsection Instruction Set Syntax
452 Two slightly different syntaxes are support for ARM and THUMB
453 instructions. The default, @code{divided}, uses the old style where
454 ARM and THUMB instructions had their own, separate syntaxes. The new,
455 @code{unified} syntax, which can be selected via the @code{.syntax}
456 directive, and has the following main features:
460 Immediate operands do not require a @code{#} prefix.
463 The @code{IT} instruction may appear, and if it does it is validated
464 against subsequent conditional affixes. In ARM mode it does not
465 generate machine code, in THUMB mode it does.
468 For ARM instructions the conditional affixes always appear at the end
469 of the instruction. For THUMB instructions conditional affixes can be
470 used, but only inside the scope of an @code{IT} instruction.
473 All of the instructions new to the V6T2 architecture (and later) are
474 available. (Only a few such instructions can be written in the
475 @code{divided} syntax).
478 The @code{.N} and @code{.W} suffixes are recognized and honored.
481 All instructions set the flags if and only if they have an @code{s}
486 @subsection Special Characters
488 @cindex line comment character, ARM
489 @cindex ARM line comment character
490 The presence of a @samp{@@} anywhere on a line indicates the start of
491 a comment that extends to the end of that line.
493 If a @samp{#} appears as the first character of a line then the whole
494 line is treated as a comment, but in this case the line could also be
495 a logical line number directive (@pxref{Comments}) or a preprocessor
496 control command (@pxref{Preprocessing}).
498 @cindex line separator, ARM
499 @cindex statement separator, ARM
500 @cindex ARM line separator
501 The @samp{;} character can be used instead of a newline to separate
504 @cindex immediate character, ARM
505 @cindex ARM immediate character
506 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
508 @cindex identifiers, ARM
509 @cindex ARM identifiers
510 *TODO* Explain about /data modifier on symbols.
513 @subsection Register Names
515 @cindex ARM register names
516 @cindex register names, ARM
517 *TODO* Explain about ARM register naming, and the predefined names.
519 @node ARM-Relocations
520 @subsection ARM relocation generation
522 @cindex data relocations, ARM
523 @cindex ARM data relocations
524 Specific data relocations can be generated by putting the relocation name
525 in parentheses after the symbol name. For example:
531 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
533 The following relocations are supported:
549 For compatibility with older toolchains the assembler also accepts
550 @code{(PLT)} after branch targets. On legacy targets this will
551 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
552 targets it will encode either the @samp{R_ARM_CALL} or
553 @samp{R_ARM_JUMP24} relocation, as appropriate.
555 @cindex MOVW and MOVT relocations, ARM
556 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
557 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
558 respectively. For example to load the 32-bit address of foo into r0:
561 MOVW r0, #:lower16:foo
562 MOVT r0, #:upper16:foo
565 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
566 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
567 generated by prefixing the value with @samp{#:lower0_7:#},
568 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
569 respectively. For example to load the 32-bit address of foo into r0:
572 MOVS r0, #:upper8_15:#foo
574 ADDS r0, #:upper0_7:#foo
576 ADDS r0, #:lower8_15:#foo
578 ADDS r0, #:lower0_7:#foo
581 @node ARM-Neon-Alignment
582 @subsection NEON Alignment Specifiers
584 @cindex alignment for NEON instructions
585 Some NEON load/store instructions allow an optional address
587 The ARM documentation specifies that this is indicated by
588 @samp{@@ @var{align}}. However GAS already interprets
589 the @samp{@@} character as a "line comment" start,
590 so @samp{: @var{align}} is used instead. For example:
593 vld1.8 @{q0@}, [r0, :128]
596 @node ARM Floating Point
597 @section Floating Point
599 @cindex floating point, ARM (@sc{ieee})
600 @cindex ARM floating point (@sc{ieee})
601 The ARM family uses @sc{ieee} floating-point numbers.
604 @section ARM Machine Directives
606 @cindex machine directives, ARM
607 @cindex ARM machine directives
610 @c AAAAAAAAAAAAAAAAAAAAAAAAA
613 @cindex @code{.2byte} directive, ARM
614 @cindex @code{.4byte} directive, ARM
615 @cindex @code{.8byte} directive, ARM
616 @item .2byte @var{expression} [, @var{expression}]*
617 @itemx .4byte @var{expression} [, @var{expression}]*
618 @itemx .8byte @var{expression} [, @var{expression}]*
619 These directives write 2, 4 or 8 byte values to the output section.
622 @cindex @code{.align} directive, ARM
623 @item .align @var{expression} [, @var{expression}]
624 This is the generic @var{.align} directive. For the ARM however if the
625 first argument is zero (ie no alignment is needed) the assembler will
626 behave as if the argument had been 2 (ie pad to the next four byte
627 boundary). This is for compatibility with ARM's own assembler.
629 @cindex @code{.arch} directive, ARM
630 @item .arch @var{name}
631 Select the target architecture. Valid values for @var{name} are the same as
632 for the @option{-march} command-line option without the instruction set
635 Specifying @code{.arch} clears any previously selected architecture
638 @cindex @code{.arch_extension} directive, ARM
639 @item .arch_extension @var{name}
640 Add or remove an architecture extension to the target architecture. Valid
641 values for @var{name} are the same as those accepted as architectural
642 extensions by the @option{-mcpu} and @option{-march} command-line options.
644 @code{.arch_extension} may be used multiple times to add or remove extensions
645 incrementally to the architecture being compiled for.
647 @cindex @code{.arm} directive, ARM
649 This performs the same action as @var{.code 32}.
651 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
653 @cindex @code{.bss} directive, ARM
655 This directive switches to the @code{.bss} section.
657 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
659 @cindex @code{.cantunwind} directive, ARM
661 Prevents unwinding through the current function. No personality routine
662 or exception table data is required or permitted.
664 @cindex @code{.code} directive, ARM
665 @item .code @code{[16|32]}
666 This directive selects the instruction set being generated. The value 16
667 selects Thumb, with the value 32 selecting ARM.
669 @cindex @code{.cpu} directive, ARM
670 @item .cpu @var{name}
671 Select the target processor. Valid values for @var{name} are the same as
672 for the @option{-mcpu} command-line option without the instruction set
675 Specifying @code{.cpu} clears any previously selected architecture
678 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
680 @cindex @code{.dn} and @code{.qn} directives, ARM
681 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
682 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
684 The @code{dn} and @code{qn} directives are used to create typed
685 and/or indexed register aliases for use in Advanced SIMD Extension
686 (Neon) instructions. The former should be used to create aliases
687 of double-precision registers, and the latter to create aliases of
688 quad-precision registers.
690 If these directives are used to create typed aliases, those aliases can
691 be used in Neon instructions instead of writing types after the mnemonic
692 or after each operand. For example:
701 This is equivalent to writing the following:
707 Aliases created using @code{dn} or @code{qn} can be destroyed using
710 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
712 @cindex @code{.eabi_attribute} directive, ARM
713 @item .eabi_attribute @var{tag}, @var{value}
714 Set the EABI object attribute @var{tag} to @var{value}.
716 The @var{tag} is either an attribute number, or one of the following:
717 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
718 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
719 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
720 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
721 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
722 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
723 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
724 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
725 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
726 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
727 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
728 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
729 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
730 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
731 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
732 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
733 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
734 @code{Tag_conformance}, @code{Tag_T2EE_use},
735 @code{Tag_Virtualization_use}
737 The @var{value} is either a @code{number}, @code{"string"}, or
738 @code{number, "string"} depending on the tag.
740 Note - the following legacy values are also accepted by @var{tag}:
741 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
742 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
744 @cindex @code{.even} directive, ARM
746 This directive aligns to an even-numbered address.
748 @cindex @code{.extend} directive, ARM
749 @cindex @code{.ldouble} directive, ARM
750 @item .extend @var{expression} [, @var{expression}]*
751 @itemx .ldouble @var{expression} [, @var{expression}]*
752 These directives write 12byte long double floating-point values to the
753 output section. These are not compatible with current ARM processors
756 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
759 @cindex @code{.fnend} directive, ARM
761 Marks the end of a function with an unwind table entry. The unwind index
762 table entry is created when this directive is processed.
764 If no personality routine has been specified then standard personality
765 routine 0 or 1 will be used, depending on the number of unwind opcodes
769 @cindex @code{.fnstart} directive, ARM
771 Marks the start of a function with an unwind table entry.
773 @cindex @code{.force_thumb} directive, ARM
775 This directive forces the selection of Thumb instructions, even if the
776 target processor does not support those instructions
778 @cindex @code{.fpu} directive, ARM
779 @item .fpu @var{name}
780 Select the floating-point unit to assemble for. Valid values for @var{name}
781 are the same as for the @option{-mfpu} command-line option.
783 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
784 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
786 @cindex @code{.handlerdata} directive, ARM
788 Marks the end of the current function, and the start of the exception table
789 entry for that function. Anything between this directive and the
790 @code{.fnend} directive will be added to the exception table entry.
792 Must be preceded by a @code{.personality} or @code{.personalityindex}
795 @c IIIIIIIIIIIIIIIIIIIIIIIIII
797 @cindex @code{.inst} directive, ARM
798 @item .inst @var{opcode} [ , @dots{} ]
799 @itemx .inst.n @var{opcode} [ , @dots{} ]
800 @itemx .inst.w @var{opcode} [ , @dots{} ]
801 Generates the instruction corresponding to the numerical value @var{opcode}.
802 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
803 specified explicitly, overriding the normal encoding rules.
805 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
806 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
807 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
809 @item .ldouble @var{expression} [, @var{expression}]*
812 @cindex @code{.ltorg} directive, ARM
814 This directive causes the current contents of the literal pool to be
815 dumped into the current section (which is assumed to be the .text
816 section) at the current location (aligned to a word boundary).
817 @code{GAS} maintains a separate literal pool for each section and each
818 sub-section. The @code{.ltorg} directive will only affect the literal
819 pool of the current section and sub-section. At the end of assembly
820 all remaining, un-empty literal pools will automatically be dumped.
822 Note - older versions of @code{GAS} would dump the current literal
823 pool any time a section change occurred. This is no longer done, since
824 it prevents accurate control of the placement of literal pools.
826 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
828 @cindex @code{.movsp} directive, ARM
829 @item .movsp @var{reg} [, #@var{offset}]
830 Tell the unwinder that @var{reg} contains an offset from the current
831 stack pointer. If @var{offset} is not specified then it is assumed to be
834 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
835 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
837 @cindex @code{.object_arch} directive, ARM
838 @item .object_arch @var{name}
839 Override the architecture recorded in the EABI object attribute section.
840 Valid values for @var{name} are the same as for the @code{.arch} directive.
841 Typically this is useful when code uses runtime detection of CPU features.
843 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
845 @cindex @code{.packed} directive, ARM
846 @item .packed @var{expression} [, @var{expression}]*
847 This directive writes 12-byte packed floating-point values to the
848 output section. These are not compatible with current ARM processors
852 @cindex @code{.pad} directive, ARM
853 @item .pad #@var{count}
854 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
855 A positive value indicates the function prologue allocated stack space by
856 decrementing the stack pointer.
858 @cindex @code{.personality} directive, ARM
859 @item .personality @var{name}
860 Sets the personality routine for the current function to @var{name}.
862 @cindex @code{.personalityindex} directive, ARM
863 @item .personalityindex @var{index}
864 Sets the personality routine for the current function to the EABI standard
865 routine number @var{index}
867 @cindex @code{.pool} directive, ARM
869 This is a synonym for .ltorg.
871 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
872 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
874 @cindex @code{.req} directive, ARM
875 @item @var{name} .req @var{register name}
876 This creates an alias for @var{register name} called @var{name}. For
883 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
886 @cindex @code{.save} directive, ARM
887 @item .save @var{reglist}
888 Generate unwinder annotations to restore the registers in @var{reglist}.
889 The format of @var{reglist} is the same as the corresponding store-multiple
893 @exdent @emph{core registers}
894 .save @{r4, r5, r6, lr@}
895 stmfd sp!, @{r4, r5, r6, lr@}
896 @exdent @emph{FPA registers}
899 @exdent @emph{VFP registers}
900 .save @{d8, d9, d10@}
901 fstmdx sp!, @{d8, d9, d10@}
902 @exdent @emph{iWMMXt registers}
904 wstrd wr11, [sp, #-8]!
905 wstrd wr10, [sp, #-8]!
908 wstrd wr11, [sp, #-8]!
910 wstrd wr10, [sp, #-8]!
914 @cindex @code{.setfp} directive, ARM
915 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
916 Make all unwinder annotations relative to a frame pointer. Without this
917 the unwinder will use offsets from the stack pointer.
919 The syntax of this directive is the same as the @code{add} or @code{mov}
920 instruction used to set the frame pointer. @var{spreg} must be either
921 @code{sp} or mentioned in a previous @code{.movsp} directive.
931 @cindex @code{.secrel32} directive, ARM
932 @item .secrel32 @var{expression} [, @var{expression}]*
933 This directive emits relocations that evaluate to the section-relative
934 offset of each expression's symbol. This directive is only supported
937 @cindex @code{.syntax} directive, ARM
938 @item .syntax [@code{unified} | @code{divided}]
939 This directive sets the Instruction Set Syntax as described in the
940 @ref{ARM-Instruction-Set} section.
942 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
944 @cindex @code{.thumb} directive, ARM
946 This performs the same action as @var{.code 16}.
948 @cindex @code{.thumb_func} directive, ARM
950 This directive specifies that the following symbol is the name of a
951 Thumb encoded function. This information is necessary in order to allow
952 the assembler and linker to generate correct code for interworking
953 between Arm and Thumb instructions and should be used even if
954 interworking is not going to be performed. The presence of this
955 directive also implies @code{.thumb}
957 This directive is not necessary when generating EABI objects. On these
958 targets the encoding is implicit when generating Thumb code.
960 @cindex @code{.thumb_set} directive, ARM
962 This performs the equivalent of a @code{.set} directive in that it
963 creates a symbol which is an alias for another symbol (possibly not yet
964 defined). This directive also has the added property in that it marks
965 the aliased symbol as being a thumb function entry point, in the same
966 way that the @code{.thumb_func} directive does.
968 @cindex @code{.tlsdescseq} directive, ARM
969 @item .tlsdescseq @var{tls-variable}
970 This directive is used to annotate parts of an inlined TLS descriptor
971 trampoline. Normally the trampoline is provided by the linker, and
972 this directive is not needed.
974 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
976 @cindex @code{.unreq} directive, ARM
977 @item .unreq @var{alias-name}
978 This undefines a register alias which was previously defined using the
979 @code{req}, @code{dn} or @code{qn} directives. For example:
986 An error occurs if the name is undefined. Note - this pseudo op can
987 be used to delete builtin in register name aliases (eg 'r0'). This
988 should only be done if it is really necessary.
990 @cindex @code{.unwind_raw} directive, ARM
991 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
992 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
993 the stack pointer by @var{offset} bytes.
995 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
998 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1000 @cindex @code{.vsave} directive, ARM
1001 @item .vsave @var{vfp-reglist}
1002 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1003 using FLDMD. Also works for VFPv3 registers
1004 that are to be restored using VLDM.
1005 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1009 @exdent @emph{VFP registers}
1010 .vsave @{d8, d9, d10@}
1011 fstmdd sp!, @{d8, d9, d10@}
1012 @exdent @emph{VFPv3 registers}
1013 .vsave @{d15, d16, d17@}
1014 vstm sp!, @{d15, d16, d17@}
1017 Since FLDMX and FSTMX are now deprecated, this directive should be
1018 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1020 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1021 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1022 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1023 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1031 @cindex opcodes for ARM
1032 @code{@value{AS}} implements all the standard ARM opcodes. It also
1033 implements several pseudo opcodes, including several synthetic load
1038 @cindex @code{NOP} pseudo op, ARM
1044 This pseudo op will always evaluate to a legal ARM instruction that does
1045 nothing. Currently it will evaluate to MOV r0, r0.
1047 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1050 ldr <register> , = <expression>
1053 If expression evaluates to a numeric constant then a MOV or MVN
1054 instruction will be used in place of the LDR instruction, if the
1055 constant can be generated by either of these instructions. Otherwise
1056 the constant will be placed into the nearest literal pool (if it not
1057 already there) and a PC relative LDR instruction will be generated.
1059 @cindex @code{ADR reg,<label>} pseudo op, ARM
1062 adr <register> <label>
1065 This instruction will load the address of @var{label} into the indicated
1066 register. The instruction will evaluate to a PC relative ADD or SUB
1067 instruction depending upon where the label is located. If the label is
1068 out of range, or if it is not defined in the same file (and section) as
1069 the ADR instruction, then an error will be generated. This instruction
1070 will not make use of the literal pool.
1072 If @var{label} is a thumb function symbol, and thumb interworking has
1073 been enabled via the @option{-mthumb-interwork} option then the bottom
1074 bit of the value stored into @var{register} will be set. This allows
1075 the following sequence to work as expected:
1078 adr r0, thumb_function
1082 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1085 adrl <register> <label>
1088 This instruction will load the address of @var{label} into the indicated
1089 register. The instruction will evaluate to one or two PC relative ADD
1090 or SUB instructions depending upon where the label is located. If a
1091 second instruction is not needed a NOP instruction will be generated in
1092 its place, so that this instruction is always 8 bytes long.
1094 If the label is out of range, or if it is not defined in the same file
1095 (and section) as the ADRL instruction, then an error will be generated.
1096 This instruction will not make use of the literal pool.
1098 If @var{label} is a thumb function symbol, and thumb interworking has
1099 been enabled via the @option{-mthumb-interwork} option then the bottom
1100 bit of the value stored into @var{register} will be set.
1104 For information on the ARM or Thumb instruction sets, see @cite{ARM
1105 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1108 @node ARM Mapping Symbols
1109 @section Mapping Symbols
1111 The ARM ELF specification requires that special symbols be inserted
1112 into object files to mark certain features:
1118 At the start of a region of code containing ARM instructions.
1122 At the start of a region of code containing THUMB instructions.
1126 At the start of a region of data.
1130 The assembler will automatically insert these symbols for you - there
1131 is no need to code them yourself. Support for tagging symbols ($b,
1132 $f, $p and $m) which is also mentioned in the current ARM ELF
1133 specification is not implemented. This is because they have been
1134 dropped from the new EABI and so tools cannot rely upon their
1137 @node ARM Unwinding Tutorial
1140 The ABI for the ARM Architecture specifies a standard format for
1141 exception unwind information. This information is used when an
1142 exception is thrown to determine where control should be transferred.
1143 In particular, the unwind information is used to determine which
1144 function called the function that threw the exception, and which
1145 function called that one, and so forth. This information is also used
1146 to restore the values of callee-saved registers in the function
1147 catching the exception.
1149 If you are writing functions in assembly code, and those functions
1150 call other functions that throw exceptions, you must use assembly
1151 pseudo ops to ensure that appropriate exception unwind information is
1152 generated. Otherwise, if one of the functions called by your assembly
1153 code throws an exception, the run-time library will be unable to
1154 unwind the stack through your assembly code and your program will not
1157 To illustrate the use of these pseudo ops, we will examine the code
1158 that G++ generates for the following C++ input:
1161 void callee (int *);
1172 This example does not show how to throw or catch an exception from
1173 assembly code. That is a much more complex operation and should
1174 always be done in a high-level language, such as C++, that directly
1175 supports exceptions.
1177 The code generated by one particular version of G++ when compiling the
1184 @ Function supports interworking.
1185 @ args = 0, pretend = 0, frame = 8
1186 @ frame_needed = 1, uses_anonymous_args = 0
1208 Of course, the sequence of instructions varies based on the options
1209 you pass to GCC and on the version of GCC in use. The exact
1210 instructions are not important since we are focusing on the pseudo ops
1211 that are used to generate unwind information.
1213 An important assumption made by the unwinder is that the stack frame
1214 does not change during the body of the function. In particular, since
1215 we assume that the assembly code does not itself throw an exception,
1216 the only point where an exception can be thrown is from a call, such
1217 as the @code{bl} instruction above. At each call site, the same saved
1218 registers (including @code{lr}, which indicates the return address)
1219 must be located in the same locations relative to the frame pointer.
1221 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1222 op appears immediately before the first instruction of the function
1223 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1224 op appears immediately after the last instruction of the function.
1225 These pseudo ops specify the range of the function.
1227 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1228 @code{.pad}) matters; their exact locations are irrelevant. In the
1229 example above, the compiler emits the pseudo ops with particular
1230 instructions. That makes it easier to understand the code, but it is
1231 not required for correctness. It would work just as well to emit all
1232 of the pseudo ops other than @code{.fnend} in the same order, but
1233 immediately after @code{.fnstart}.
1235 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1236 indicates registers that have been saved to the stack so that they can
1237 be restored before the function returns. The argument to the
1238 @code{.save} pseudo op is a list of registers to save. If a register
1239 is ``callee-saved'' (as specified by the ABI) and is modified by the
1240 function you are writing, then your code must save the value before it
1241 is modified and restore the original value before the function
1242 returns. If an exception is thrown, the run-time library restores the
1243 values of these registers from their locations on the stack before
1244 returning control to the exception handler. (Of course, if an
1245 exception is not thrown, the function that contains the @code{.save}
1246 pseudo op restores these registers in the function epilogue, as is
1247 done with the @code{ldmfd} instruction above.)
1249 You do not have to save callee-saved registers at the very beginning
1250 of the function and you do not need to use the @code{.save} pseudo op
1251 immediately following the point at which the registers are saved.
1252 However, if you modify a callee-saved register, you must save it on
1253 the stack before modifying it and before calling any functions which
1254 might throw an exception. And, you must use the @code{.save} pseudo
1255 op to indicate that you have done so.
1257 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1258 modification of the stack pointer that does not save any registers.
1259 The argument is the number of bytes (in decimal) that are subtracted
1260 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1261 subtracting from the stack pointer increases the size of the stack.)
1263 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1264 indicates the register that contains the frame pointer. The first
1265 argument is the register that is set, which is typically @code{fp}.
1266 The second argument indicates the register from which the frame
1267 pointer takes its value. The third argument, if present, is the value
1268 (in decimal) added to the register specified by the second argument to
1269 compute the value of the frame pointer. You should not modify the
1270 frame pointer in the body of the function.
1272 If you do not use a frame pointer, then you should not use the
1273 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1274 should avoid modifying the stack pointer outside of the function
1275 prologue. Otherwise, the run-time library will be unable to find
1276 saved registers when it is unwinding the stack.
1278 The pseudo ops described above are sufficient for writing assembly
1279 code that calls functions which may throw exceptions. If you need to
1280 know more about the object-file format used to represent unwind
1281 information, you may consult the @cite{Exception Handling ABI for the
1282 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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