1 @c Copyright (C) 1996-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
134 @code{cortex-m0plus},
137 @code{marvell-whitney},
140 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
141 @code{i80200} (Intel XScale processor)
142 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
145 The special name @code{all} may be used to allow the
146 assembler to accept instructions valid for any ARM processor.
148 In addition to the basic instruction set, the assembler can be told to
149 accept various extension mnemonics that extend the processor using the
150 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
151 is equivalent to specifying @code{-mcpu=ep9312}.
153 Multiple extensions may be specified, separated by a @code{+}. The
154 extensions should be specified in ascending alphabetical order.
156 Some extensions may be restricted to particular architectures; this is
157 documented in the list of extensions below.
159 Extension mnemonics may also be removed from those the assembler accepts.
160 This is done be prepending @code{no} to the option that adds the extension.
161 Extensions that are removed should be listed after all extensions which have
162 been added, again in ascending alphabetical order. For example,
163 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
166 The following extensions are currently supported:
168 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
169 @code{fp} (Floating Point Extensions for v8-A architecture),
170 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
175 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
177 @code{os} (Operating System for v6M architecture),
178 @code{sec} (Security Extensions for v6K and v7-A architectures),
179 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
180 @code{virt} (Virtualization Extensions for v7-A architecture, implies
185 @cindex @code{-march=} command line option, ARM
186 @item -march=@var{architecture}[+@var{extension}@dots{}]
187 This option specifies the target architecture. The assembler will issue
188 an error message if an attempt is made to assemble an instruction which
189 will not execute on the target architecture. The following architecture
190 names are recognized:
224 If both @code{-mcpu} and
225 @code{-march} are specified, the assembler will use
226 the setting for @code{-mcpu}.
228 The architecture option can be extended with the same instruction set
229 extension options as the @code{-mcpu} option.
231 @cindex @code{-mfpu=} command line option, ARM
232 @item -mfpu=@var{floating-point-format}
234 This option specifies the floating point format to assemble for. The
235 assembler will issue an error message if an attempt is made to assemble
236 an instruction which will not execute on the target floating point unit.
237 The following format options are recognized:
257 @code{vfpv3-d16-fp16},
272 @code{neon-fp-armv8},
274 @code{crypto-neon-fp-armv8}.
276 In addition to determining which instructions are assembled, this option
277 also affects the way in which the @code{.double} assembler directive behaves
278 when assembling little-endian code.
280 The default is dependent on the processor selected. For Architecture 5 or
281 later, the default is to assembler for VFP instructions; for earlier
282 architectures the default is to assemble for FPA instructions.
284 @cindex @code{-mthumb} command line option, ARM
286 This option specifies that the assembler should start assembling Thumb
287 instructions; that is, it should behave as though the file starts with a
288 @code{.code 16} directive.
290 @cindex @code{-mthumb-interwork} command line option, ARM
291 @item -mthumb-interwork
292 This option specifies that the output generated by the assembler should
293 be marked as supporting interworking.
295 @cindex @code{-mimplicit-it} command line option, ARM
296 @item -mimplicit-it=never
297 @itemx -mimplicit-it=always
298 @itemx -mimplicit-it=arm
299 @itemx -mimplicit-it=thumb
300 The @code{-mimplicit-it} option controls the behavior of the assembler when
301 conditional instructions are not enclosed in IT blocks.
302 There are four possible behaviors.
303 If @code{never} is specified, such constructs cause a warning in ARM
304 code and an error in Thumb-2 code.
305 If @code{always} is specified, such constructs are accepted in both
306 ARM and Thumb-2 code, where the IT instruction is added implicitly.
307 If @code{arm} is specified, such constructs are accepted in ARM code
308 and cause an error in Thumb-2 code.
309 If @code{thumb} is specified, such constructs cause a warning in ARM
310 code and are accepted in Thumb-2 code. If you omit this option, the
311 behavior is equivalent to @code{-mimplicit-it=arm}.
313 @cindex @code{-mapcs-26} command line option, ARM
314 @cindex @code{-mapcs-32} command line option, ARM
317 These options specify that the output generated by the assembler should
318 be marked as supporting the indicated version of the Arm Procedure.
321 @cindex @code{-matpcs} command line option, ARM
323 This option specifies that the output generated by the assembler should
324 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
325 enabled this option will cause the assembler to create an empty
326 debugging section in the object file called .arm.atpcs. Debuggers can
327 use this to determine the ABI being used by.
329 @cindex @code{-mapcs-float} command line option, ARM
331 This indicates the floating point variant of the APCS should be
332 used. In this variant floating point arguments are passed in FP
333 registers rather than integer registers.
335 @cindex @code{-mapcs-reentrant} command line option, ARM
336 @item -mapcs-reentrant
337 This indicates that the reentrant variant of the APCS should be used.
338 This variant supports position independent code.
340 @cindex @code{-mfloat-abi=} command line option, ARM
341 @item -mfloat-abi=@var{abi}
342 This option specifies that the output generated by the assembler should be
343 marked as using specified floating point ABI.
344 The following values are recognized:
350 @cindex @code{-eabi=} command line option, ARM
351 @item -meabi=@var{ver}
352 This option specifies which EABI version the produced object files should
354 The following values are recognized:
360 @cindex @code{-EB} command line option, ARM
362 This option specifies that the output generated by the assembler should
363 be marked as being encoded for a big-endian processor.
365 Note: If a program is being built for a system with big-endian data
366 and little-endian instructions then it should be assembled with the
367 @option{-EB} option, (all of it, code and data) and then linked with
368 the @option{--be8} option. This will reverse the endianness of the
369 instructions back to little-endian, but leave the data as big-endian.
371 @cindex @code{-EL} command line option, ARM
373 This option specifies that the output generated by the assembler should
374 be marked as being encoded for a little-endian processor.
376 @cindex @code{-k} command line option, ARM
377 @cindex PIC code generation for ARM
379 This option specifies that the output of the assembler should be marked
380 as position-independent code (PIC).
382 @cindex @code{--fix-v4bx} command line option, ARM
384 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
385 the linker option of the same name.
387 @cindex @code{-mwarn-deprecated} command line option, ARM
388 @item -mwarn-deprecated
389 @itemx -mno-warn-deprecated
390 Enable or disable warnings about using deprecated options or
391 features. The default is to warn.
393 @cindex @code{-mccs} command line option, ARM
395 Turns on CodeComposer Studio assembly syntax compatibility mode.
397 @cindex @code{-mwarn-syms} command line option, ARM
399 @itemx -mno-warn-syms
400 Enable or disable warnings about symbols that match the names of ARM
401 instructions. The default is to warn.
409 * ARM-Instruction-Set:: Instruction Set
410 * ARM-Chars:: Special Characters
411 * ARM-Regs:: Register Names
412 * ARM-Relocations:: Relocations
413 * ARM-Neon-Alignment:: NEON Alignment Specifiers
416 @node ARM-Instruction-Set
417 @subsection Instruction Set Syntax
418 Two slightly different syntaxes are support for ARM and THUMB
419 instructions. The default, @code{divided}, uses the old style where
420 ARM and THUMB instructions had their own, separate syntaxes. The new,
421 @code{unified} syntax, which can be selected via the @code{.syntax}
422 directive, and has the following main features:
426 Immediate operands do not require a @code{#} prefix.
429 The @code{IT} instruction may appear, and if it does it is validated
430 against subsequent conditional affixes. In ARM mode it does not
431 generate machine code, in THUMB mode it does.
434 For ARM instructions the conditional affixes always appear at the end
435 of the instruction. For THUMB instructions conditional affixes can be
436 used, but only inside the scope of an @code{IT} instruction.
439 All of the instructions new to the V6T2 architecture (and later) are
440 available. (Only a few such instructions can be written in the
441 @code{divided} syntax).
444 The @code{.N} and @code{.W} suffixes are recognized and honored.
447 All instructions set the flags if and only if they have an @code{s}
452 @subsection Special Characters
454 @cindex line comment character, ARM
455 @cindex ARM line comment character
456 The presence of a @samp{@@} anywhere on a line indicates the start of
457 a comment that extends to the end of that line.
459 If a @samp{#} appears as the first character of a line then the whole
460 line is treated as a comment, but in this case the line could also be
461 a logical line number directive (@pxref{Comments}) or a preprocessor
462 control command (@pxref{Preprocessing}).
464 @cindex line separator, ARM
465 @cindex statement separator, ARM
466 @cindex ARM line separator
467 The @samp{;} character can be used instead of a newline to separate
470 @cindex immediate character, ARM
471 @cindex ARM immediate character
472 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
474 @cindex identifiers, ARM
475 @cindex ARM identifiers
476 *TODO* Explain about /data modifier on symbols.
479 @subsection Register Names
481 @cindex ARM register names
482 @cindex register names, ARM
483 *TODO* Explain about ARM register naming, and the predefined names.
485 @node ARM-Relocations
486 @subsection ARM relocation generation
488 @cindex data relocations, ARM
489 @cindex ARM data relocations
490 Specific data relocations can be generated by putting the relocation name
491 in parentheses after the symbol name. For example:
497 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
499 The following relocations are supported:
515 For compatibility with older toolchains the assembler also accepts
516 @code{(PLT)} after branch targets. On legacy targets this will
517 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
518 targets it will encode either the @samp{R_ARM_CALL} or
519 @samp{R_ARM_JUMP24} relocation, as appropriate.
521 @cindex MOVW and MOVT relocations, ARM
522 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
523 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
524 respectively. For example to load the 32-bit address of foo into r0:
527 MOVW r0, #:lower16:foo
528 MOVT r0, #:upper16:foo
531 @node ARM-Neon-Alignment
532 @subsection NEON Alignment Specifiers
534 @cindex alignment for NEON instructions
535 Some NEON load/store instructions allow an optional address
537 The ARM documentation specifies that this is indicated by
538 @samp{@@ @var{align}}. However GAS already interprets
539 the @samp{@@} character as a "line comment" start,
540 so @samp{: @var{align}} is used instead. For example:
543 vld1.8 @{q0@}, [r0, :128]
546 @node ARM Floating Point
547 @section Floating Point
549 @cindex floating point, ARM (@sc{ieee})
550 @cindex ARM floating point (@sc{ieee})
551 The ARM family uses @sc{ieee} floating-point numbers.
554 @section ARM Machine Directives
556 @cindex machine directives, ARM
557 @cindex ARM machine directives
560 @c AAAAAAAAAAAAAAAAAAAAAAAAA
562 @cindex @code{.2byte} directive, ARM
563 @cindex @code{.4byte} directive, ARM
564 @cindex @code{.8byte} directive, ARM
565 @item .2byte @var{expression} [, @var{expression}]*
566 @itemx .4byte @var{expression} [, @var{expression}]*
567 @itemx .8byte @var{expression} [, @var{expression}]*
568 These directives write 2, 4 or 8 byte values to the output section.
570 @cindex @code{.align} directive, ARM
571 @item .align @var{expression} [, @var{expression}]
572 This is the generic @var{.align} directive. For the ARM however if the
573 first argument is zero (ie no alignment is needed) the assembler will
574 behave as if the argument had been 2 (ie pad to the next four byte
575 boundary). This is for compatibility with ARM's own assembler.
577 @cindex @code{.arch} directive, ARM
578 @item .arch @var{name}
579 Select the target architecture. Valid values for @var{name} are the same as
580 for the @option{-march} commandline option.
582 Specifying @code{.arch} clears any previously selected architecture
585 @cindex @code{.arch_extension} directive, ARM
586 @item .arch_extension @var{name}
587 Add or remove an architecture extension to the target architecture. Valid
588 values for @var{name} are the same as those accepted as architectural
589 extensions by the @option{-mcpu} commandline option.
591 @code{.arch_extension} may be used multiple times to add or remove extensions
592 incrementally to the architecture being compiled for.
594 @cindex @code{.arm} directive, ARM
596 This performs the same action as @var{.code 32}.
598 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
600 @cindex @code{.bss} directive, ARM
602 This directive switches to the @code{.bss} section.
604 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
606 @cindex @code{.cantunwind} directive, ARM
608 Prevents unwinding through the current function. No personality routine
609 or exception table data is required or permitted.
611 @cindex @code{.code} directive, ARM
612 @item .code @code{[16|32]}
613 This directive selects the instruction set being generated. The value 16
614 selects Thumb, with the value 32 selecting ARM.
616 @cindex @code{.cpu} directive, ARM
617 @item .cpu @var{name}
618 Select the target processor. Valid values for @var{name} are the same as
619 for the @option{-mcpu} commandline option.
621 Specifying @code{.cpu} clears any previously selected architecture
624 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
626 @cindex @code{.dn} and @code{.qn} directives, ARM
627 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
628 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
630 The @code{dn} and @code{qn} directives are used to create typed
631 and/or indexed register aliases for use in Advanced SIMD Extension
632 (Neon) instructions. The former should be used to create aliases
633 of double-precision registers, and the latter to create aliases of
634 quad-precision registers.
636 If these directives are used to create typed aliases, those aliases can
637 be used in Neon instructions instead of writing types after the mnemonic
638 or after each operand. For example:
647 This is equivalent to writing the following:
653 Aliases created using @code{dn} or @code{qn} can be destroyed using
656 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
658 @cindex @code{.eabi_attribute} directive, ARM
659 @item .eabi_attribute @var{tag}, @var{value}
660 Set the EABI object attribute @var{tag} to @var{value}.
662 The @var{tag} is either an attribute number, or one of the following:
663 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
664 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
665 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
666 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
667 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
668 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
669 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
670 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
671 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
672 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
673 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
674 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
675 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
676 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
677 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
678 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
679 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
680 @code{Tag_conformance}, @code{Tag_T2EE_use},
681 @code{Tag_Virtualization_use}
683 The @var{value} is either a @code{number}, @code{"string"}, or
684 @code{number, "string"} depending on the tag.
686 Note - the following legacy values are also accepted by @var{tag}:
687 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
688 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
690 @cindex @code{.even} directive, ARM
692 This directive aligns to an even-numbered address.
694 @cindex @code{.extend} directive, ARM
695 @cindex @code{.ldouble} directive, ARM
696 @item .extend @var{expression} [, @var{expression}]*
697 @itemx .ldouble @var{expression} [, @var{expression}]*
698 These directives write 12byte long double floating-point values to the
699 output section. These are not compatible with current ARM processors
702 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
705 @cindex @code{.fnend} directive, ARM
707 Marks the end of a function with an unwind table entry. The unwind index
708 table entry is created when this directive is processed.
710 If no personality routine has been specified then standard personality
711 routine 0 or 1 will be used, depending on the number of unwind opcodes
715 @cindex @code{.fnstart} directive, ARM
717 Marks the start of a function with an unwind table entry.
719 @cindex @code{.force_thumb} directive, ARM
721 This directive forces the selection of Thumb instructions, even if the
722 target processor does not support those instructions
724 @cindex @code{.fpu} directive, ARM
725 @item .fpu @var{name}
726 Select the floating-point unit to assemble for. Valid values for @var{name}
727 are the same as for the @option{-mfpu} commandline option.
729 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
730 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
732 @cindex @code{.handlerdata} directive, ARM
734 Marks the end of the current function, and the start of the exception table
735 entry for that function. Anything between this directive and the
736 @code{.fnend} directive will be added to the exception table entry.
738 Must be preceded by a @code{.personality} or @code{.personalityindex}
741 @c IIIIIIIIIIIIIIIIIIIIIIIIII
743 @cindex @code{.inst} directive, ARM
744 @item .inst @var{opcode} [ , @dots{} ]
745 @itemx .inst.n @var{opcode} [ , @dots{} ]
746 @itemx .inst.w @var{opcode} [ , @dots{} ]
747 Generates the instruction corresponding to the numerical value @var{opcode}.
748 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
749 specified explicitly, overriding the normal encoding rules.
751 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
752 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
753 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
755 @item .ldouble @var{expression} [, @var{expression}]*
758 @cindex @code{.ltorg} directive, ARM
760 This directive causes the current contents of the literal pool to be
761 dumped into the current section (which is assumed to be the .text
762 section) at the current location (aligned to a word boundary).
763 @code{GAS} maintains a separate literal pool for each section and each
764 sub-section. The @code{.ltorg} directive will only affect the literal
765 pool of the current section and sub-section. At the end of assembly
766 all remaining, un-empty literal pools will automatically be dumped.
768 Note - older versions of @code{GAS} would dump the current literal
769 pool any time a section change occurred. This is no longer done, since
770 it prevents accurate control of the placement of literal pools.
772 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
774 @cindex @code{.movsp} directive, ARM
775 @item .movsp @var{reg} [, #@var{offset}]
776 Tell the unwinder that @var{reg} contains an offset from the current
777 stack pointer. If @var{offset} is not specified then it is assumed to be
780 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
781 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
783 @cindex @code{.object_arch} directive, ARM
784 @item .object_arch @var{name}
785 Override the architecture recorded in the EABI object attribute section.
786 Valid values for @var{name} are the same as for the @code{.arch} directive.
787 Typically this is useful when code uses runtime detection of CPU features.
789 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
791 @cindex @code{.packed} directive, ARM
792 @item .packed @var{expression} [, @var{expression}]*
793 This directive writes 12-byte packed floating-point values to the
794 output section. These are not compatible with current ARM processors
798 @cindex @code{.pad} directive, ARM
799 @item .pad #@var{count}
800 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
801 A positive value indicates the function prologue allocated stack space by
802 decrementing the stack pointer.
804 @cindex @code{.personality} directive, ARM
805 @item .personality @var{name}
806 Sets the personality routine for the current function to @var{name}.
808 @cindex @code{.personalityindex} directive, ARM
809 @item .personalityindex @var{index}
810 Sets the personality routine for the current function to the EABI standard
811 routine number @var{index}
813 @cindex @code{.pool} directive, ARM
815 This is a synonym for .ltorg.
817 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
818 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
820 @cindex @code{.req} directive, ARM
821 @item @var{name} .req @var{register name}
822 This creates an alias for @var{register name} called @var{name}. For
829 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
832 @cindex @code{.save} directive, ARM
833 @item .save @var{reglist}
834 Generate unwinder annotations to restore the registers in @var{reglist}.
835 The format of @var{reglist} is the same as the corresponding store-multiple
839 @exdent @emph{core registers}
840 .save @{r4, r5, r6, lr@}
841 stmfd sp!, @{r4, r5, r6, lr@}
842 @exdent @emph{FPA registers}
845 @exdent @emph{VFP registers}
846 .save @{d8, d9, d10@}
847 fstmdx sp!, @{d8, d9, d10@}
848 @exdent @emph{iWMMXt registers}
850 wstrd wr11, [sp, #-8]!
851 wstrd wr10, [sp, #-8]!
854 wstrd wr11, [sp, #-8]!
856 wstrd wr10, [sp, #-8]!
860 @cindex @code{.setfp} directive, ARM
861 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
862 Make all unwinder annotations relative to a frame pointer. Without this
863 the unwinder will use offsets from the stack pointer.
865 The syntax of this directive is the same as the @code{add} or @code{mov}
866 instruction used to set the frame pointer. @var{spreg} must be either
867 @code{sp} or mentioned in a previous @code{.movsp} directive.
877 @cindex @code{.secrel32} directive, ARM
878 @item .secrel32 @var{expression} [, @var{expression}]*
879 This directive emits relocations that evaluate to the section-relative
880 offset of each expression's symbol. This directive is only supported
883 @cindex @code{.syntax} directive, ARM
884 @item .syntax [@code{unified} | @code{divided}]
885 This directive sets the Instruction Set Syntax as described in the
886 @ref{ARM-Instruction-Set} section.
888 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
890 @cindex @code{.thumb} directive, ARM
892 This performs the same action as @var{.code 16}.
894 @cindex @code{.thumb_func} directive, ARM
896 This directive specifies that the following symbol is the name of a
897 Thumb encoded function. This information is necessary in order to allow
898 the assembler and linker to generate correct code for interworking
899 between Arm and Thumb instructions and should be used even if
900 interworking is not going to be performed. The presence of this
901 directive also implies @code{.thumb}
903 This directive is not neccessary when generating EABI objects. On these
904 targets the encoding is implicit when generating Thumb code.
906 @cindex @code{.thumb_set} directive, ARM
908 This performs the equivalent of a @code{.set} directive in that it
909 creates a symbol which is an alias for another symbol (possibly not yet
910 defined). This directive also has the added property in that it marks
911 the aliased symbol as being a thumb function entry point, in the same
912 way that the @code{.thumb_func} directive does.
914 @cindex @code{.tlsdescseq} directive, ARM
915 @item .tlsdescseq @var{tls-variable}
916 This directive is used to annotate parts of an inlined TLS descriptor
917 trampoline. Normally the trampoline is provided by the linker, and
918 this directive is not needed.
920 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
922 @cindex @code{.unreq} directive, ARM
923 @item .unreq @var{alias-name}
924 This undefines a register alias which was previously defined using the
925 @code{req}, @code{dn} or @code{qn} directives. For example:
932 An error occurs if the name is undefined. Note - this pseudo op can
933 be used to delete builtin in register name aliases (eg 'r0'). This
934 should only be done if it is really necessary.
936 @cindex @code{.unwind_raw} directive, ARM
937 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
938 Insert one of more arbitary unwind opcode bytes, which are known to adjust
939 the stack pointer by @var{offset} bytes.
941 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
944 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
946 @cindex @code{.vsave} directive, ARM
947 @item .vsave @var{vfp-reglist}
948 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
949 using FLDMD. Also works for VFPv3 registers
950 that are to be restored using VLDM.
951 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
955 @exdent @emph{VFP registers}
956 .vsave @{d8, d9, d10@}
957 fstmdd sp!, @{d8, d9, d10@}
958 @exdent @emph{VFPv3 registers}
959 .vsave @{d15, d16, d17@}
960 vstm sp!, @{d15, d16, d17@}
963 Since FLDMX and FSTMX are now deprecated, this directive should be
964 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
966 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
967 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
968 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
969 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
977 @cindex opcodes for ARM
978 @code{@value{AS}} implements all the standard ARM opcodes. It also
979 implements several pseudo opcodes, including several synthetic load
984 @cindex @code{NOP} pseudo op, ARM
990 This pseudo op will always evaluate to a legal ARM instruction that does
991 nothing. Currently it will evaluate to MOV r0, r0.
993 @cindex @code{LDR reg,=<label>} pseudo op, ARM
996 ldr <register> , = <expression>
999 If expression evaluates to a numeric constant then a MOV or MVN
1000 instruction will be used in place of the LDR instruction, if the
1001 constant can be generated by either of these instructions. Otherwise
1002 the constant will be placed into the nearest literal pool (if it not
1003 already there) and a PC relative LDR instruction will be generated.
1005 @cindex @code{ADR reg,<label>} pseudo op, ARM
1008 adr <register> <label>
1011 This instruction will load the address of @var{label} into the indicated
1012 register. The instruction will evaluate to a PC relative ADD or SUB
1013 instruction depending upon where the label is located. If the label is
1014 out of range, or if it is not defined in the same file (and section) as
1015 the ADR instruction, then an error will be generated. This instruction
1016 will not make use of the literal pool.
1018 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1021 adrl <register> <label>
1024 This instruction will load the address of @var{label} into the indicated
1025 register. The instruction will evaluate to one or two PC relative ADD
1026 or SUB instructions depending upon where the label is located. If a
1027 second instruction is not needed a NOP instruction will be generated in
1028 its place, so that this instruction is always 8 bytes long.
1030 If the label is out of range, or if it is not defined in the same file
1031 (and section) as the ADRL instruction, then an error will be generated.
1032 This instruction will not make use of the literal pool.
1036 For information on the ARM or Thumb instruction sets, see @cite{ARM
1037 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1040 @node ARM Mapping Symbols
1041 @section Mapping Symbols
1043 The ARM ELF specification requires that special symbols be inserted
1044 into object files to mark certain features:
1050 At the start of a region of code containing ARM instructions.
1054 At the start of a region of code containing THUMB instructions.
1058 At the start of a region of data.
1062 The assembler will automatically insert these symbols for you - there
1063 is no need to code them yourself. Support for tagging symbols ($b,
1064 $f, $p and $m) which is also mentioned in the current ARM ELF
1065 specification is not implemented. This is because they have been
1066 dropped from the new EABI and so tools cannot rely upon their
1069 @node ARM Unwinding Tutorial
1072 The ABI for the ARM Architecture specifies a standard format for
1073 exception unwind information. This information is used when an
1074 exception is thrown to determine where control should be transferred.
1075 In particular, the unwind information is used to determine which
1076 function called the function that threw the exception, and which
1077 function called that one, and so forth. This information is also used
1078 to restore the values of callee-saved registers in the function
1079 catching the exception.
1081 If you are writing functions in assembly code, and those functions
1082 call other functions that throw exceptions, you must use assembly
1083 pseudo ops to ensure that appropriate exception unwind information is
1084 generated. Otherwise, if one of the functions called by your assembly
1085 code throws an exception, the run-time library will be unable to
1086 unwind the stack through your assembly code and your program will not
1089 To illustrate the use of these pseudo ops, we will examine the code
1090 that G++ generates for the following C++ input:
1093 void callee (int *);
1104 This example does not show how to throw or catch an exception from
1105 assembly code. That is a much more complex operation and should
1106 always be done in a high-level language, such as C++, that directly
1107 supports exceptions.
1109 The code generated by one particular version of G++ when compiling the
1116 @ Function supports interworking.
1117 @ args = 0, pretend = 0, frame = 8
1118 @ frame_needed = 1, uses_anonymous_args = 0
1140 Of course, the sequence of instructions varies based on the options
1141 you pass to GCC and on the version of GCC in use. The exact
1142 instructions are not important since we are focusing on the pseudo ops
1143 that are used to generate unwind information.
1145 An important assumption made by the unwinder is that the stack frame
1146 does not change during the body of the function. In particular, since
1147 we assume that the assembly code does not itself throw an exception,
1148 the only point where an exception can be thrown is from a call, such
1149 as the @code{bl} instruction above. At each call site, the same saved
1150 registers (including @code{lr}, which indicates the return address)
1151 must be located in the same locations relative to the frame pointer.
1153 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1154 op appears immediately before the first instruction of the function
1155 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1156 op appears immediately after the last instruction of the function.
1157 These pseudo ops specify the range of the function.
1159 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1160 @code{.pad}) matters; their exact locations are irrelevant. In the
1161 example above, the compiler emits the pseudo ops with particular
1162 instructions. That makes it easier to understand the code, but it is
1163 not required for correctness. It would work just as well to emit all
1164 of the pseudo ops other than @code{.fnend} in the same order, but
1165 immediately after @code{.fnstart}.
1167 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1168 indicates registers that have been saved to the stack so that they can
1169 be restored before the function returns. The argument to the
1170 @code{.save} pseudo op is a list of registers to save. If a register
1171 is ``callee-saved'' (as specified by the ABI) and is modified by the
1172 function you are writing, then your code must save the value before it
1173 is modified and restore the original value before the function
1174 returns. If an exception is thrown, the run-time library restores the
1175 values of these registers from their locations on the stack before
1176 returning control to the exception handler. (Of course, if an
1177 exception is not thrown, the function that contains the @code{.save}
1178 pseudo op restores these registers in the function epilogue, as is
1179 done with the @code{ldmfd} instruction above.)
1181 You do not have to save callee-saved registers at the very beginning
1182 of the function and you do not need to use the @code{.save} pseudo op
1183 immediately following the point at which the registers are saved.
1184 However, if you modify a callee-saved register, you must save it on
1185 the stack before modifying it and before calling any functions which
1186 might throw an exception. And, you must use the @code{.save} pseudo
1187 op to indicate that you have done so.
1189 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1190 modification of the stack pointer that does not save any registers.
1191 The argument is the number of bytes (in decimal) that are subtracted
1192 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1193 subtracting from the stack pointer increases the size of the stack.)
1195 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1196 indicates the register that contains the frame pointer. The first
1197 argument is the register that is set, which is typically @code{fp}.
1198 The second argument indicates the register from which the frame
1199 pointer takes its value. The third argument, if present, is the value
1200 (in decimal) added to the register specified by the second argument to
1201 compute the value of the frame pointer. You should not modify the
1202 frame pointer in the body of the function.
1204 If you do not use a frame pointer, then you should not use the
1205 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1206 should avoid modifying the stack pointer outside of the function
1207 prologue. Otherwise, the run-time library will be unable to find
1208 saved registers when it is unwinding the stack.
1210 The pseudo ops described above are sufficient for writing assembly
1211 code that calls functions which may throw exceptions. If you need to
1212 know more about the object-file format used to represent unwind
1213 information, you may consult the @cite{Exception Handling ABI for the
1214 ARM Architecture} available from @uref{http://infocenter.arm.com}.