Arm: Add support for missing CPUs
[deliverable/binutils-gdb.git] / gas / doc / c-arm.texi
1 @c Copyright (C) 1996-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
4
5 @ifset GENERIC
6 @page
7 @node ARM-Dependent
8 @chapter ARM Dependent Features
9 @end ifset
10
11 @ifclear GENERIC
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
14 @end ifclear
15
16 @cindex ARM support
17 @cindex Thumb support
18 @menu
19 * ARM Options:: Options
20 * ARM Syntax:: Syntax
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
26 @end menu
27
28 @node ARM Options
29 @section Options
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
32
33 @table @code
34
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
40 recognized:
41 @code{arm1},
42 @code{arm2},
43 @code{arm250},
44 @code{arm3},
45 @code{arm6},
46 @code{arm60},
47 @code{arm600},
48 @code{arm610},
49 @code{arm620},
50 @code{arm7},
51 @code{arm7m},
52 @code{arm7d},
53 @code{arm7dm},
54 @code{arm7di},
55 @code{arm7dmi},
56 @code{arm70},
57 @code{arm700},
58 @code{arm700i},
59 @code{arm710},
60 @code{arm710t},
61 @code{arm720},
62 @code{arm720t},
63 @code{arm740t},
64 @code{arm710c},
65 @code{arm7100},
66 @code{arm7500},
67 @code{arm7500fe},
68 @code{arm7t},
69 @code{arm7tdmi},
70 @code{arm7tdmi-s},
71 @code{arm8},
72 @code{arm810},
73 @code{strongarm},
74 @code{strongarm1},
75 @code{strongarm110},
76 @code{strongarm1100},
77 @code{strongarm1110},
78 @code{arm9},
79 @code{arm920},
80 @code{arm920t},
81 @code{arm922t},
82 @code{arm940t},
83 @code{arm9tdmi},
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
86 @code{arm9e},
87 @code{arm926e},
88 @code{arm926ej-s},
89 @code{arm946e-r0},
90 @code{arm946e},
91 @code{arm946e-s},
92 @code{arm966e-r0},
93 @code{arm966e},
94 @code{arm966e-s},
95 @code{arm968e-s},
96 @code{arm10t},
97 @code{arm10tdmi},
98 @code{arm10e},
99 @code{arm1020},
100 @code{arm1020t},
101 @code{arm1020e},
102 @code{arm1022e},
103 @code{arm1026ej-s},
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
109 @code{arm1136j-s},
110 @code{arm1136jf-s},
111 @code{arm1156t2-s},
112 @code{arm1156t2f-s},
113 @code{arm1176jz-s},
114 @code{arm1176jzf-s},
115 @code{mpcore},
116 @code{mpcorenovfp},
117 @code{cortex-a5},
118 @code{cortex-a7},
119 @code{cortex-a8},
120 @code{cortex-a9},
121 @code{cortex-a15},
122 @code{cortex-a17},
123 @code{cortex-a32},
124 @code{cortex-a35},
125 @code{cortex-a53},
126 @code{cortex-a55},
127 @code{cortex-a57},
128 @code{cortex-a72},
129 @code{cortex-a73},
130 @code{cortex-a75},
131 @code{cortex-a76},
132 @code{cortex-a76ae},
133 @code{cortex-a77},
134 @code{ares},
135 @code{cortex-r4},
136 @code{cortex-r4f},
137 @code{cortex-r5},
138 @code{cortex-r7},
139 @code{cortex-r8},
140 @code{cortex-r52},
141 @code{cortex-m35p},
142 @code{cortex-m33},
143 @code{cortex-m23},
144 @code{cortex-m7},
145 @code{cortex-m4},
146 @code{cortex-m3},
147 @code{cortex-m1},
148 @code{cortex-m0},
149 @code{cortex-m0plus},
150 @code{exynos-m1},
151 @code{marvell-pj4},
152 @code{marvell-whitney},
153 @code{neoverse-n1},
154 @code{xgene1},
155 @code{xgene2},
156 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
157 @code{i80200} (Intel XScale processor)
158 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
159 and
160 @code{xscale}.
161 The special name @code{all} may be used to allow the
162 assembler to accept instructions valid for any ARM processor.
163
164 In addition to the basic instruction set, the assembler can be told to
165 accept various extension mnemonics that extend the processor using the
166 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
167 is equivalent to specifying @code{-mcpu=ep9312}.
168
169 Multiple extensions may be specified, separated by a @code{+}. The
170 extensions should be specified in ascending alphabetical order.
171
172 Some extensions may be restricted to particular architectures; this is
173 documented in the list of extensions below.
174
175 Extension mnemonics may also be removed from those the assembler accepts.
176 This is done be prepending @code{no} to the option that adds the extension.
177 Extensions that are removed should be listed after all extensions which have
178 been added, again in ascending alphabetical order. For example,
179 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
180
181
182 The following extensions are currently supported:
183 @code{crc}
184 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
185 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
186 @code{fp} (Floating Point Extensions for v8-A architecture),
187 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
188 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
189 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
190 @code{iwmmxt},
191 @code{iwmmxt2},
192 @code{xscale},
193 @code{maverick},
194 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
195 architectures),
196 @code{os} (Operating System for v6M architecture),
197 @code{predres} (Execution and Data Prediction Restriction Instruction for
198 v8-A architectures, added by default from v8.5-A),
199 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
200 default from v8.5-A),
201 @code{sec} (Security Extensions for v6K and v7-A architectures),
202 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
203 @code{virt} (Virtualization Extensions for v7-A architecture, implies
204 @code{idiv}),
205 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
206 @code{ras} (Reliability, Availability and Serviceability extensions
207 for v8-A architecture),
208 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
209 @code{simd})
210 and
211 @code{xscale}.
212
213 @cindex @code{-march=} command-line option, ARM
214 @item -march=@var{architecture}[+@var{extension}@dots{}]
215 This option specifies the target architecture. The assembler will issue
216 an error message if an attempt is made to assemble an instruction which
217 will not execute on the target architecture. The following architecture
218 names are recognized:
219 @code{armv1},
220 @code{armv2},
221 @code{armv2a},
222 @code{armv2s},
223 @code{armv3},
224 @code{armv3m},
225 @code{armv4},
226 @code{armv4xm},
227 @code{armv4t},
228 @code{armv4txm},
229 @code{armv5},
230 @code{armv5t},
231 @code{armv5txm},
232 @code{armv5te},
233 @code{armv5texp},
234 @code{armv6},
235 @code{armv6j},
236 @code{armv6k},
237 @code{armv6z},
238 @code{armv6kz},
239 @code{armv6-m},
240 @code{armv6s-m},
241 @code{armv7},
242 @code{armv7-a},
243 @code{armv7ve},
244 @code{armv7-r},
245 @code{armv7-m},
246 @code{armv7e-m},
247 @code{armv8-a},
248 @code{armv8.1-a},
249 @code{armv8.2-a},
250 @code{armv8.3-a},
251 @code{armv8-r},
252 @code{armv8.4-a},
253 @code{armv8.5-a},
254 @code{armv8-m.base},
255 @code{armv8-m.main},
256 @code{armv8.1-m.main},
257 @code{iwmmxt},
258 @code{iwmmxt2}
259 and
260 @code{xscale}.
261 If both @code{-mcpu} and
262 @code{-march} are specified, the assembler will use
263 the setting for @code{-mcpu}.
264
265 The architecture option can be extended with a set extension options. These
266 extensions are context sensitive, i.e. the same extension may mean different
267 things when used with different architectures. When used together with a
268 @code{-mfpu} option, the union of both feature enablement is taken.
269 See their availability and meaning below:
270
271 For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
272
273 @code{+fp}: Enables VFPv2 instructions.
274 @code{+nofp}: Disables all FPU instrunctions.
275
276 For @code{armv7}:
277
278 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
279 @code{+nofp}: Disables all FPU instructions.
280
281 For @code{armv7-a}:
282
283 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
284 @code{+vfpv3-d16}: Alias for @code{+fp}.
285 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
286 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
287 conversion instructions and 16 double-word registers.
288 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
289 instructions and 32 double-word registers.
290 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
291 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
292 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
293 registers.
294 @code{+neon}: Alias for @code{+simd}.
295 @code{+neon-vfpv3}: Alias for @code{+simd}.
296 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
297 NEONv1 instructions with 32 double-word registers.
298 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
299 double-word registers.
300 @code{+mp}: Enables Multiprocessing Extensions.
301 @code{+sec}: Enables Security Extensions.
302 @code{+nofp}: Disables all FPU and NEON instructions.
303 @code{+nosimd}: Disables all NEON instructions.
304
305 For @code{armv7ve}:
306
307 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
308 @code{+vfpv4-d16}: Alias for @code{+fp}.
309 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
310 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
311 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
312 conversion instructions and 16 double-word registers.
313 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
314 instructions and 32 double-word registers.
315 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
316 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
317 double-word registers.
318 @code{+neon-vfpv4}: Alias for @code{+simd}.
319 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
320 registers.
321 @code{+neon-vfpv3}: Alias for @code{+neon}.
322 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
323 NEONv1 instructions with 32 double-word registers.
324 double-word registers.
325 @code{+nofp}: Disables all FPU and NEON instructions.
326 @code{+nosimd}: Disables all NEON instructions.
327
328 For @code{armv7-r}:
329
330 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
331 double-word registers.
332 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
333 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
334 @code{+vfpv3-d16}: Alias for @code{+fp}.
335 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
336 floating-point conversion instructions with 16 double-word registers.
337 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
338 conversion instructions with 16 double-word registers.
339 @code{+idiv}: Enables integer division instructions in ARM mode.
340 @code{+nofp}: Disables all FPU instructions.
341
342 For @code{armv7e-m}:
343
344 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
345 double-word registers.
346 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
347 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
348 double-word registers.
349 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
350 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
351 @code{+nofp}: Disables all FPU instructions.
352
353 For @code{armv8-m.main}:
354
355 @code{+dsp}: Enables DSP Extension.
356 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
357 double-word registers.
358 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
359 @code{+nofp}: Disables all FPU instructions.
360 @code{+nodsp}: Disables DSP Extension.
361
362 For @code{armv8.1-m.main}:
363
364 @code{+dsp}: Enables DSP Extension.
365 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
366 for Armv8.1-M Mainline with 16 double-word registers.
367 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
368 Armv8.1-M Mainline, implies @code{+fp}.
369 @code{+mve}: Enables integer only M-profile Vector Extension for
370 Armv8.1-M Mainline, implies @code{+dsp}.
371 @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
372 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
373 @code{+nofp}: Disables all FPU instructions.
374 @code{+nodsp}: Disables DSP Extension.
375 @code{+nomve}: Disables all M-profile Vector Extensions.
376
377 For @code{armv8-a}:
378
379 @code{+crc}: Enables CRC32 Extension.
380 @code{+simd}: Enables VFP and NEON for Armv8-A.
381 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
382 @code{+simd}.
383 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
384 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
385 for Armv8-A.
386 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
387 @code{+nocrypto}: Disables Cryptography Extensions.
388
389 For @code{armv8.1-a}:
390
391 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
392 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
393 @code{+simd}.
394 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
395 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
396 for Armv8-A.
397 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
398 @code{+nocrypto}: Disables Cryptography Extensions.
399
400 For @code{armv8.2-a} and @code{armv8.3-a}:
401
402 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
403 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
404 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
405 for Armv8.2-A, implies @code{+fp16}.
406 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
407 @code{+simd}.
408 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
409 @code{+simd}.
410 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
411 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
412 for Armv8-A.
413 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
414 @code{+nocrypto}: Disables Cryptography Extensions.
415
416 For @code{armv8.4-a}:
417
418 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
419 Armv8.2-A.
420 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
421 Variant Extensions for Armv8.2-A, implies @code{+simd}.
422 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
423 @code{+simd}.
424 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
425 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
426 for Armv8-A.
427 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
428 @code{+nocryptp}: Disables Cryptography Extensions.
429
430 For @code{armv8.5-a}:
431
432 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
433 Armv8.2-A.
434 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
435 Variant Extensions for Armv8.2-A, implies @code{+simd}.
436 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
437 @code{+simd}.
438 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
439 @code{+nocryptp}: Disables Cryptography Extensions.
440
441
442 @cindex @code{-mfpu=} command-line option, ARM
443 @item -mfpu=@var{floating-point-format}
444
445 This option specifies the floating point format to assemble for. The
446 assembler will issue an error message if an attempt is made to assemble
447 an instruction which will not execute on the target floating point unit.
448 The following format options are recognized:
449 @code{softfpa},
450 @code{fpe},
451 @code{fpe2},
452 @code{fpe3},
453 @code{fpa},
454 @code{fpa10},
455 @code{fpa11},
456 @code{arm7500fe},
457 @code{softvfp},
458 @code{softvfp+vfp},
459 @code{vfp},
460 @code{vfp10},
461 @code{vfp10-r0},
462 @code{vfp9},
463 @code{vfpxd},
464 @code{vfpv2},
465 @code{vfpv3},
466 @code{vfpv3-fp16},
467 @code{vfpv3-d16},
468 @code{vfpv3-d16-fp16},
469 @code{vfpv3xd},
470 @code{vfpv3xd-d16},
471 @code{vfpv4},
472 @code{vfpv4-d16},
473 @code{fpv4-sp-d16},
474 @code{fpv5-sp-d16},
475 @code{fpv5-d16},
476 @code{fp-armv8},
477 @code{arm1020t},
478 @code{arm1020e},
479 @code{arm1136jf-s},
480 @code{maverick},
481 @code{neon},
482 @code{neon-vfpv3},
483 @code{neon-fp16},
484 @code{neon-vfpv4},
485 @code{neon-fp-armv8},
486 @code{crypto-neon-fp-armv8},
487 @code{neon-fp-armv8.1}
488 and
489 @code{crypto-neon-fp-armv8.1}.
490
491 In addition to determining which instructions are assembled, this option
492 also affects the way in which the @code{.double} assembler directive behaves
493 when assembling little-endian code.
494
495 The default is dependent on the processor selected. For Architecture 5 or
496 later, the default is to assemble for VFP instructions; for earlier
497 architectures the default is to assemble for FPA instructions.
498
499 @cindex @code{-mfp16-format=} command-line option
500 @item -mfp16-format=@var{format}
501 This option specifies the half-precision floating point format to use
502 when assembling floating point numbers emitted by the @code{.float16}
503 directive.
504 The following format options are recognized:
505 @code{ieee},
506 @code{alternative}.
507 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
508 point format is used, if @code{alternative} is specified then the Arm
509 alternative half-precision format is used. If this option is set on the
510 command line then the format is fixed and cannot be changed with
511 the @code{float16_format} directive. If this value is not set then
512 the IEEE 754-2008 format is used until the format is explicitly set with
513 the @code{float16_format} directive.
514
515 @cindex @code{-mthumb} command-line option, ARM
516 @item -mthumb
517 This option specifies that the assembler should start assembling Thumb
518 instructions; that is, it should behave as though the file starts with a
519 @code{.code 16} directive.
520
521 @cindex @code{-mthumb-interwork} command-line option, ARM
522 @item -mthumb-interwork
523 This option specifies that the output generated by the assembler should
524 be marked as supporting interworking. It also affects the behaviour
525 of the @code{ADR} and @code{ADRL} pseudo opcodes.
526
527 @cindex @code{-mimplicit-it} command-line option, ARM
528 @item -mimplicit-it=never
529 @itemx -mimplicit-it=always
530 @itemx -mimplicit-it=arm
531 @itemx -mimplicit-it=thumb
532 The @code{-mimplicit-it} option controls the behavior of the assembler when
533 conditional instructions are not enclosed in IT blocks.
534 There are four possible behaviors.
535 If @code{never} is specified, such constructs cause a warning in ARM
536 code and an error in Thumb-2 code.
537 If @code{always} is specified, such constructs are accepted in both
538 ARM and Thumb-2 code, where the IT instruction is added implicitly.
539 If @code{arm} is specified, such constructs are accepted in ARM code
540 and cause an error in Thumb-2 code.
541 If @code{thumb} is specified, such constructs cause a warning in ARM
542 code and are accepted in Thumb-2 code. If you omit this option, the
543 behavior is equivalent to @code{-mimplicit-it=arm}.
544
545 @cindex @code{-mapcs-26} command-line option, ARM
546 @cindex @code{-mapcs-32} command-line option, ARM
547 @item -mapcs-26
548 @itemx -mapcs-32
549 These options specify that the output generated by the assembler should
550 be marked as supporting the indicated version of the Arm Procedure.
551 Calling Standard.
552
553 @cindex @code{-matpcs} command-line option, ARM
554 @item -matpcs
555 This option specifies that the output generated by the assembler should
556 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
557 enabled this option will cause the assembler to create an empty
558 debugging section in the object file called .arm.atpcs. Debuggers can
559 use this to determine the ABI being used by.
560
561 @cindex @code{-mapcs-float} command-line option, ARM
562 @item -mapcs-float
563 This indicates the floating point variant of the APCS should be
564 used. In this variant floating point arguments are passed in FP
565 registers rather than integer registers.
566
567 @cindex @code{-mapcs-reentrant} command-line option, ARM
568 @item -mapcs-reentrant
569 This indicates that the reentrant variant of the APCS should be used.
570 This variant supports position independent code.
571
572 @cindex @code{-mfloat-abi=} command-line option, ARM
573 @item -mfloat-abi=@var{abi}
574 This option specifies that the output generated by the assembler should be
575 marked as using specified floating point ABI.
576 The following values are recognized:
577 @code{soft},
578 @code{softfp}
579 and
580 @code{hard}.
581
582 @cindex @code{-eabi=} command-line option, ARM
583 @item -meabi=@var{ver}
584 This option specifies which EABI version the produced object files should
585 conform to.
586 The following values are recognized:
587 @code{gnu},
588 @code{4}
589 and
590 @code{5}.
591
592 @cindex @code{-EB} command-line option, ARM
593 @item -EB
594 This option specifies that the output generated by the assembler should
595 be marked as being encoded for a big-endian processor.
596
597 Note: If a program is being built for a system with big-endian data
598 and little-endian instructions then it should be assembled with the
599 @option{-EB} option, (all of it, code and data) and then linked with
600 the @option{--be8} option. This will reverse the endianness of the
601 instructions back to little-endian, but leave the data as big-endian.
602
603 @cindex @code{-EL} command-line option, ARM
604 @item -EL
605 This option specifies that the output generated by the assembler should
606 be marked as being encoded for a little-endian processor.
607
608 @cindex @code{-k} command-line option, ARM
609 @cindex PIC code generation for ARM
610 @item -k
611 This option specifies that the output of the assembler should be marked
612 as position-independent code (PIC).
613
614 @cindex @code{--fix-v4bx} command-line option, ARM
615 @item --fix-v4bx
616 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
617 the linker option of the same name.
618
619 @cindex @code{-mwarn-deprecated} command-line option, ARM
620 @item -mwarn-deprecated
621 @itemx -mno-warn-deprecated
622 Enable or disable warnings about using deprecated options or
623 features. The default is to warn.
624
625 @cindex @code{-mccs} command-line option, ARM
626 @item -mccs
627 Turns on CodeComposer Studio assembly syntax compatibility mode.
628
629 @cindex @code{-mwarn-syms} command-line option, ARM
630 @item -mwarn-syms
631 @itemx -mno-warn-syms
632 Enable or disable warnings about symbols that match the names of ARM
633 instructions. The default is to warn.
634
635 @end table
636
637
638 @node ARM Syntax
639 @section Syntax
640 @menu
641 * ARM-Instruction-Set:: Instruction Set
642 * ARM-Chars:: Special Characters
643 * ARM-Regs:: Register Names
644 * ARM-Relocations:: Relocations
645 * ARM-Neon-Alignment:: NEON Alignment Specifiers
646 @end menu
647
648 @node ARM-Instruction-Set
649 @subsection Instruction Set Syntax
650 Two slightly different syntaxes are support for ARM and THUMB
651 instructions. The default, @code{divided}, uses the old style where
652 ARM and THUMB instructions had their own, separate syntaxes. The new,
653 @code{unified} syntax, which can be selected via the @code{.syntax}
654 directive, and has the following main features:
655
656 @itemize @bullet
657 @item
658 Immediate operands do not require a @code{#} prefix.
659
660 @item
661 The @code{IT} instruction may appear, and if it does it is validated
662 against subsequent conditional affixes. In ARM mode it does not
663 generate machine code, in THUMB mode it does.
664
665 @item
666 For ARM instructions the conditional affixes always appear at the end
667 of the instruction. For THUMB instructions conditional affixes can be
668 used, but only inside the scope of an @code{IT} instruction.
669
670 @item
671 All of the instructions new to the V6T2 architecture (and later) are
672 available. (Only a few such instructions can be written in the
673 @code{divided} syntax).
674
675 @item
676 The @code{.N} and @code{.W} suffixes are recognized and honored.
677
678 @item
679 All instructions set the flags if and only if they have an @code{s}
680 affix.
681 @end itemize
682
683 @node ARM-Chars
684 @subsection Special Characters
685
686 @cindex line comment character, ARM
687 @cindex ARM line comment character
688 The presence of a @samp{@@} anywhere on a line indicates the start of
689 a comment that extends to the end of that line.
690
691 If a @samp{#} appears as the first character of a line then the whole
692 line is treated as a comment, but in this case the line could also be
693 a logical line number directive (@pxref{Comments}) or a preprocessor
694 control command (@pxref{Preprocessing}).
695
696 @cindex line separator, ARM
697 @cindex statement separator, ARM
698 @cindex ARM line separator
699 The @samp{;} character can be used instead of a newline to separate
700 statements.
701
702 @cindex immediate character, ARM
703 @cindex ARM immediate character
704 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
705
706 @cindex identifiers, ARM
707 @cindex ARM identifiers
708 *TODO* Explain about /data modifier on symbols.
709
710 @node ARM-Regs
711 @subsection Register Names
712
713 @cindex ARM register names
714 @cindex register names, ARM
715 *TODO* Explain about ARM register naming, and the predefined names.
716
717 @node ARM-Relocations
718 @subsection ARM relocation generation
719
720 @cindex data relocations, ARM
721 @cindex ARM data relocations
722 Specific data relocations can be generated by putting the relocation name
723 in parentheses after the symbol name. For example:
724
725 @smallexample
726 .word foo(TARGET1)
727 @end smallexample
728
729 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
730 @var{foo}.
731 The following relocations are supported:
732 @code{GOT},
733 @code{GOTOFF},
734 @code{TARGET1},
735 @code{TARGET2},
736 @code{SBREL},
737 @code{TLSGD},
738 @code{TLSLDM},
739 @code{TLSLDO},
740 @code{TLSDESC},
741 @code{TLSCALL},
742 @code{GOTTPOFF},
743 @code{GOT_PREL}
744 and
745 @code{TPOFF}.
746
747 For compatibility with older toolchains the assembler also accepts
748 @code{(PLT)} after branch targets. On legacy targets this will
749 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
750 targets it will encode either the @samp{R_ARM_CALL} or
751 @samp{R_ARM_JUMP24} relocation, as appropriate.
752
753 @cindex MOVW and MOVT relocations, ARM
754 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
755 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
756 respectively. For example to load the 32-bit address of foo into r0:
757
758 @smallexample
759 MOVW r0, #:lower16:foo
760 MOVT r0, #:upper16:foo
761 @end smallexample
762
763 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
764 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
765 generated by prefixing the value with @samp{#:lower0_7:#},
766 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
767 respectively. For example to load the 32-bit address of foo into r0:
768
769 @smallexample
770 MOVS r0, #:upper8_15:#foo
771 LSLS r0, r0, #8
772 ADDS r0, #:upper0_7:#foo
773 LSLS r0, r0, #8
774 ADDS r0, #:lower8_15:#foo
775 LSLS r0, r0, #8
776 ADDS r0, #:lower0_7:#foo
777 @end smallexample
778
779 @node ARM-Neon-Alignment
780 @subsection NEON Alignment Specifiers
781
782 @cindex alignment for NEON instructions
783 Some NEON load/store instructions allow an optional address
784 alignment qualifier.
785 The ARM documentation specifies that this is indicated by
786 @samp{@@ @var{align}}. However GAS already interprets
787 the @samp{@@} character as a "line comment" start,
788 so @samp{: @var{align}} is used instead. For example:
789
790 @smallexample
791 vld1.8 @{q0@}, [r0, :128]
792 @end smallexample
793
794 @node ARM Floating Point
795 @section Floating Point
796
797 @cindex floating point, ARM (@sc{ieee})
798 @cindex ARM floating point (@sc{ieee})
799 The ARM family uses @sc{ieee} floating-point numbers.
800
801 @node ARM Directives
802 @section ARM Machine Directives
803
804 @cindex machine directives, ARM
805 @cindex ARM machine directives
806 @table @code
807
808 @c AAAAAAAAAAAAAAAAAAAAAAAAA
809
810 @ifclear ELF
811 @cindex @code{.2byte} directive, ARM
812 @cindex @code{.4byte} directive, ARM
813 @cindex @code{.8byte} directive, ARM
814 @item .2byte @var{expression} [, @var{expression}]*
815 @itemx .4byte @var{expression} [, @var{expression}]*
816 @itemx .8byte @var{expression} [, @var{expression}]*
817 These directives write 2, 4 or 8 byte values to the output section.
818 @end ifclear
819
820 @cindex @code{.align} directive, ARM
821 @item .align @var{expression} [, @var{expression}]
822 This is the generic @var{.align} directive. For the ARM however if the
823 first argument is zero (ie no alignment is needed) the assembler will
824 behave as if the argument had been 2 (ie pad to the next four byte
825 boundary). This is for compatibility with ARM's own assembler.
826
827 @cindex @code{.arch} directive, ARM
828 @item .arch @var{name}
829 Select the target architecture. Valid values for @var{name} are the same as
830 for the @option{-march} command-line option without the instruction set
831 extension.
832
833 Specifying @code{.arch} clears any previously selected architecture
834 extensions.
835
836 @cindex @code{.arch_extension} directive, ARM
837 @item .arch_extension @var{name}
838 Add or remove an architecture extension to the target architecture. Valid
839 values for @var{name} are the same as those accepted as architectural
840 extensions by the @option{-mcpu} and @option{-march} command-line options.
841
842 @code{.arch_extension} may be used multiple times to add or remove extensions
843 incrementally to the architecture being compiled for.
844
845 @cindex @code{.arm} directive, ARM
846 @item .arm
847 This performs the same action as @var{.code 32}.
848
849 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
850
851 @cindex @code{.bss} directive, ARM
852 @item .bss
853 This directive switches to the @code{.bss} section.
854
855 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
856
857 @cindex @code{.cantunwind} directive, ARM
858 @item .cantunwind
859 Prevents unwinding through the current function. No personality routine
860 or exception table data is required or permitted.
861
862 @cindex @code{.code} directive, ARM
863 @item .code @code{[16|32]}
864 This directive selects the instruction set being generated. The value 16
865 selects Thumb, with the value 32 selecting ARM.
866
867 @cindex @code{.cpu} directive, ARM
868 @item .cpu @var{name}
869 Select the target processor. Valid values for @var{name} are the same as
870 for the @option{-mcpu} command-line option without the instruction set
871 extension.
872
873 Specifying @code{.cpu} clears any previously selected architecture
874 extensions.
875
876 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
877
878 @cindex @code{.dn} and @code{.qn} directives, ARM
879 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
880 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
881
882 The @code{dn} and @code{qn} directives are used to create typed
883 and/or indexed register aliases for use in Advanced SIMD Extension
884 (Neon) instructions. The former should be used to create aliases
885 of double-precision registers, and the latter to create aliases of
886 quad-precision registers.
887
888 If these directives are used to create typed aliases, those aliases can
889 be used in Neon instructions instead of writing types after the mnemonic
890 or after each operand. For example:
891
892 @smallexample
893 x .dn d2.f32
894 y .dn d3.f32
895 z .dn d4.f32[1]
896 vmul x,y,z
897 @end smallexample
898
899 This is equivalent to writing the following:
900
901 @smallexample
902 vmul.f32 d2,d3,d4[1]
903 @end smallexample
904
905 Aliases created using @code{dn} or @code{qn} can be destroyed using
906 @code{unreq}.
907
908 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
909
910 @cindex @code{.eabi_attribute} directive, ARM
911 @item .eabi_attribute @var{tag}, @var{value}
912 Set the EABI object attribute @var{tag} to @var{value}.
913
914 The @var{tag} is either an attribute number, or one of the following:
915 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
916 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
917 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
918 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
919 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
920 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
921 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
922 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
923 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
924 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
925 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
926 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
927 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
928 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
929 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
930 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
931 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
932 @code{Tag_conformance}, @code{Tag_T2EE_use},
933 @code{Tag_Virtualization_use}
934
935 The @var{value} is either a @code{number}, @code{"string"}, or
936 @code{number, "string"} depending on the tag.
937
938 Note - the following legacy values are also accepted by @var{tag}:
939 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
940 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
941
942 @cindex @code{.even} directive, ARM
943 @item .even
944 This directive aligns to an even-numbered address.
945
946 @cindex @code{.extend} directive, ARM
947 @cindex @code{.ldouble} directive, ARM
948 @item .extend @var{expression} [, @var{expression}]*
949 @itemx .ldouble @var{expression} [, @var{expression}]*
950 These directives write 12byte long double floating-point values to the
951 output section. These are not compatible with current ARM processors
952 or ABIs.
953
954 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
955
956 @cindex @code{.float16} directive, ARM
957 @item .float16 @var{value [,...,value_n]}
958 Place the half precision floating point representation of one or more
959 floating-point values into the current section. The exact format of the
960 encoding is specified by @code{.float16_format}. If the format has not
961 been explicitly set yet (either via the @code{.float16_format} directive or
962 the command line option) then the IEEE 754-2008 format is used.
963
964 @cindex @code{.float16_format} directive, ARM
965 @item .float16_format @var{format}
966 Set the format to use when encoding float16 values emitted by
967 the @code{.float16} directive.
968 Once the format has been set it cannot be changed.
969 @code{format} should be one of the following: @code{ieee} (encode in
970 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
971 the Arm alternative half precision format).
972
973 @anchor{arm_fnend}
974 @cindex @code{.fnend} directive, ARM
975 @item .fnend
976 Marks the end of a function with an unwind table entry. The unwind index
977 table entry is created when this directive is processed.
978
979 If no personality routine has been specified then standard personality
980 routine 0 or 1 will be used, depending on the number of unwind opcodes
981 required.
982
983 @anchor{arm_fnstart}
984 @cindex @code{.fnstart} directive, ARM
985 @item .fnstart
986 Marks the start of a function with an unwind table entry.
987
988 @cindex @code{.force_thumb} directive, ARM
989 @item .force_thumb
990 This directive forces the selection of Thumb instructions, even if the
991 target processor does not support those instructions
992
993 @cindex @code{.fpu} directive, ARM
994 @item .fpu @var{name}
995 Select the floating-point unit to assemble for. Valid values for @var{name}
996 are the same as for the @option{-mfpu} command-line option.
997
998 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
999 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
1000
1001 @cindex @code{.handlerdata} directive, ARM
1002 @item .handlerdata
1003 Marks the end of the current function, and the start of the exception table
1004 entry for that function. Anything between this directive and the
1005 @code{.fnend} directive will be added to the exception table entry.
1006
1007 Must be preceded by a @code{.personality} or @code{.personalityindex}
1008 directive.
1009
1010 @c IIIIIIIIIIIIIIIIIIIIIIIIII
1011
1012 @cindex @code{.inst} directive, ARM
1013 @item .inst @var{opcode} [ , @dots{} ]
1014 @itemx .inst.n @var{opcode} [ , @dots{} ]
1015 @itemx .inst.w @var{opcode} [ , @dots{} ]
1016 Generates the instruction corresponding to the numerical value @var{opcode}.
1017 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1018 specified explicitly, overriding the normal encoding rules.
1019
1020 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
1021 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
1022 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
1023
1024 @item .ldouble @var{expression} [, @var{expression}]*
1025 See @code{.extend}.
1026
1027 @cindex @code{.ltorg} directive, ARM
1028 @item .ltorg
1029 This directive causes the current contents of the literal pool to be
1030 dumped into the current section (which is assumed to be the .text
1031 section) at the current location (aligned to a word boundary).
1032 @code{GAS} maintains a separate literal pool for each section and each
1033 sub-section. The @code{.ltorg} directive will only affect the literal
1034 pool of the current section and sub-section. At the end of assembly
1035 all remaining, un-empty literal pools will automatically be dumped.
1036
1037 Note - older versions of @code{GAS} would dump the current literal
1038 pool any time a section change occurred. This is no longer done, since
1039 it prevents accurate control of the placement of literal pools.
1040
1041 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
1042
1043 @cindex @code{.movsp} directive, ARM
1044 @item .movsp @var{reg} [, #@var{offset}]
1045 Tell the unwinder that @var{reg} contains an offset from the current
1046 stack pointer. If @var{offset} is not specified then it is assumed to be
1047 zero.
1048
1049 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
1050 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
1051
1052 @cindex @code{.object_arch} directive, ARM
1053 @item .object_arch @var{name}
1054 Override the architecture recorded in the EABI object attribute section.
1055 Valid values for @var{name} are the same as for the @code{.arch} directive.
1056 Typically this is useful when code uses runtime detection of CPU features.
1057
1058 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
1059
1060 @cindex @code{.packed} directive, ARM
1061 @item .packed @var{expression} [, @var{expression}]*
1062 This directive writes 12-byte packed floating-point values to the
1063 output section. These are not compatible with current ARM processors
1064 or ABIs.
1065
1066 @anchor{arm_pad}
1067 @cindex @code{.pad} directive, ARM
1068 @item .pad #@var{count}
1069 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
1070 A positive value indicates the function prologue allocated stack space by
1071 decrementing the stack pointer.
1072
1073 @cindex @code{.personality} directive, ARM
1074 @item .personality @var{name}
1075 Sets the personality routine for the current function to @var{name}.
1076
1077 @cindex @code{.personalityindex} directive, ARM
1078 @item .personalityindex @var{index}
1079 Sets the personality routine for the current function to the EABI standard
1080 routine number @var{index}
1081
1082 @cindex @code{.pool} directive, ARM
1083 @item .pool
1084 This is a synonym for .ltorg.
1085
1086 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
1087 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
1088
1089 @cindex @code{.req} directive, ARM
1090 @item @var{name} .req @var{register name}
1091 This creates an alias for @var{register name} called @var{name}. For
1092 example:
1093
1094 @smallexample
1095 foo .req r0
1096 @end smallexample
1097
1098 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
1099
1100 @anchor{arm_save}
1101 @cindex @code{.save} directive, ARM
1102 @item .save @var{reglist}
1103 Generate unwinder annotations to restore the registers in @var{reglist}.
1104 The format of @var{reglist} is the same as the corresponding store-multiple
1105 instruction.
1106
1107 @smallexample
1108 @exdent @emph{core registers}
1109 .save @{r4, r5, r6, lr@}
1110 stmfd sp!, @{r4, r5, r6, lr@}
1111 @exdent @emph{FPA registers}
1112 .save f4, 2
1113 sfmfd f4, 2, [sp]!
1114 @exdent @emph{VFP registers}
1115 .save @{d8, d9, d10@}
1116 fstmdx sp!, @{d8, d9, d10@}
1117 @exdent @emph{iWMMXt registers}
1118 .save @{wr10, wr11@}
1119 wstrd wr11, [sp, #-8]!
1120 wstrd wr10, [sp, #-8]!
1121 or
1122 .save wr11
1123 wstrd wr11, [sp, #-8]!
1124 .save wr10
1125 wstrd wr10, [sp, #-8]!
1126 @end smallexample
1127
1128 @anchor{arm_setfp}
1129 @cindex @code{.setfp} directive, ARM
1130 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
1131 Make all unwinder annotations relative to a frame pointer. Without this
1132 the unwinder will use offsets from the stack pointer.
1133
1134 The syntax of this directive is the same as the @code{add} or @code{mov}
1135 instruction used to set the frame pointer. @var{spreg} must be either
1136 @code{sp} or mentioned in a previous @code{.movsp} directive.
1137
1138 @smallexample
1139 .movsp ip
1140 mov ip, sp
1141 @dots{}
1142 .setfp fp, ip, #4
1143 add fp, ip, #4
1144 @end smallexample
1145
1146 @cindex @code{.secrel32} directive, ARM
1147 @item .secrel32 @var{expression} [, @var{expression}]*
1148 This directive emits relocations that evaluate to the section-relative
1149 offset of each expression's symbol. This directive is only supported
1150 for PE targets.
1151
1152 @cindex @code{.syntax} directive, ARM
1153 @item .syntax [@code{unified} | @code{divided}]
1154 This directive sets the Instruction Set Syntax as described in the
1155 @ref{ARM-Instruction-Set} section.
1156
1157 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
1158
1159 @cindex @code{.thumb} directive, ARM
1160 @item .thumb
1161 This performs the same action as @var{.code 16}.
1162
1163 @cindex @code{.thumb_func} directive, ARM
1164 @item .thumb_func
1165 This directive specifies that the following symbol is the name of a
1166 Thumb encoded function. This information is necessary in order to allow
1167 the assembler and linker to generate correct code for interworking
1168 between Arm and Thumb instructions and should be used even if
1169 interworking is not going to be performed. The presence of this
1170 directive also implies @code{.thumb}
1171
1172 This directive is not necessary when generating EABI objects. On these
1173 targets the encoding is implicit when generating Thumb code.
1174
1175 @cindex @code{.thumb_set} directive, ARM
1176 @item .thumb_set
1177 This performs the equivalent of a @code{.set} directive in that it
1178 creates a symbol which is an alias for another symbol (possibly not yet
1179 defined). This directive also has the added property in that it marks
1180 the aliased symbol as being a thumb function entry point, in the same
1181 way that the @code{.thumb_func} directive does.
1182
1183 @cindex @code{.tlsdescseq} directive, ARM
1184 @item .tlsdescseq @var{tls-variable}
1185 This directive is used to annotate parts of an inlined TLS descriptor
1186 trampoline. Normally the trampoline is provided by the linker, and
1187 this directive is not needed.
1188
1189 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
1190
1191 @cindex @code{.unreq} directive, ARM
1192 @item .unreq @var{alias-name}
1193 This undefines a register alias which was previously defined using the
1194 @code{req}, @code{dn} or @code{qn} directives. For example:
1195
1196 @smallexample
1197 foo .req r0
1198 .unreq foo
1199 @end smallexample
1200
1201 An error occurs if the name is undefined. Note - this pseudo op can
1202 be used to delete builtin in register name aliases (eg 'r0'). This
1203 should only be done if it is really necessary.
1204
1205 @cindex @code{.unwind_raw} directive, ARM
1206 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
1207 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
1208 the stack pointer by @var{offset} bytes.
1209
1210 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1211 @code{.save @{r0@}}
1212
1213 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1214
1215 @cindex @code{.vsave} directive, ARM
1216 @item .vsave @var{vfp-reglist}
1217 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1218 using FLDMD. Also works for VFPv3 registers
1219 that are to be restored using VLDM.
1220 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1221 instruction.
1222
1223 @smallexample
1224 @exdent @emph{VFP registers}
1225 .vsave @{d8, d9, d10@}
1226 fstmdd sp!, @{d8, d9, d10@}
1227 @exdent @emph{VFPv3 registers}
1228 .vsave @{d15, d16, d17@}
1229 vstm sp!, @{d15, d16, d17@}
1230 @end smallexample
1231
1232 Since FLDMX and FSTMX are now deprecated, this directive should be
1233 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1234
1235 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1236 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1237 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1238 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1239
1240 @end table
1241
1242 @node ARM Opcodes
1243 @section Opcodes
1244
1245 @cindex ARM opcodes
1246 @cindex opcodes for ARM
1247 @code{@value{AS}} implements all the standard ARM opcodes. It also
1248 implements several pseudo opcodes, including several synthetic load
1249 instructions.
1250
1251 @table @code
1252
1253 @cindex @code{NOP} pseudo op, ARM
1254 @item NOP
1255 @smallexample
1256 nop
1257 @end smallexample
1258
1259 This pseudo op will always evaluate to a legal ARM instruction that does
1260 nothing. Currently it will evaluate to MOV r0, r0.
1261
1262 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1263 @item LDR
1264 @smallexample
1265 ldr <register> , = <expression>
1266 @end smallexample
1267
1268 If expression evaluates to a numeric constant then a MOV or MVN
1269 instruction will be used in place of the LDR instruction, if the
1270 constant can be generated by either of these instructions. Otherwise
1271 the constant will be placed into the nearest literal pool (if it not
1272 already there) and a PC relative LDR instruction will be generated.
1273
1274 @cindex @code{ADR reg,<label>} pseudo op, ARM
1275 @item ADR
1276 @smallexample
1277 adr <register> <label>
1278 @end smallexample
1279
1280 This instruction will load the address of @var{label} into the indicated
1281 register. The instruction will evaluate to a PC relative ADD or SUB
1282 instruction depending upon where the label is located. If the label is
1283 out of range, or if it is not defined in the same file (and section) as
1284 the ADR instruction, then an error will be generated. This instruction
1285 will not make use of the literal pool.
1286
1287 If @var{label} is a thumb function symbol, and thumb interworking has
1288 been enabled via the @option{-mthumb-interwork} option then the bottom
1289 bit of the value stored into @var{register} will be set. This allows
1290 the following sequence to work as expected:
1291
1292 @smallexample
1293 adr r0, thumb_function
1294 blx r0
1295 @end smallexample
1296
1297 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1298 @item ADRL
1299 @smallexample
1300 adrl <register> <label>
1301 @end smallexample
1302
1303 This instruction will load the address of @var{label} into the indicated
1304 register. The instruction will evaluate to one or two PC relative ADD
1305 or SUB instructions depending upon where the label is located. If a
1306 second instruction is not needed a NOP instruction will be generated in
1307 its place, so that this instruction is always 8 bytes long.
1308
1309 If the label is out of range, or if it is not defined in the same file
1310 (and section) as the ADRL instruction, then an error will be generated.
1311 This instruction will not make use of the literal pool.
1312
1313 If @var{label} is a thumb function symbol, and thumb interworking has
1314 been enabled via the @option{-mthumb-interwork} option then the bottom
1315 bit of the value stored into @var{register} will be set.
1316
1317 @end table
1318
1319 For information on the ARM or Thumb instruction sets, see @cite{ARM
1320 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1321 Ltd.
1322
1323 @node ARM Mapping Symbols
1324 @section Mapping Symbols
1325
1326 The ARM ELF specification requires that special symbols be inserted
1327 into object files to mark certain features:
1328
1329 @table @code
1330
1331 @cindex @code{$a}
1332 @item $a
1333 At the start of a region of code containing ARM instructions.
1334
1335 @cindex @code{$t}
1336 @item $t
1337 At the start of a region of code containing THUMB instructions.
1338
1339 @cindex @code{$d}
1340 @item $d
1341 At the start of a region of data.
1342
1343 @end table
1344
1345 The assembler will automatically insert these symbols for you - there
1346 is no need to code them yourself. Support for tagging symbols ($b,
1347 $f, $p and $m) which is also mentioned in the current ARM ELF
1348 specification is not implemented. This is because they have been
1349 dropped from the new EABI and so tools cannot rely upon their
1350 presence.
1351
1352 @node ARM Unwinding Tutorial
1353 @section Unwinding
1354
1355 The ABI for the ARM Architecture specifies a standard format for
1356 exception unwind information. This information is used when an
1357 exception is thrown to determine where control should be transferred.
1358 In particular, the unwind information is used to determine which
1359 function called the function that threw the exception, and which
1360 function called that one, and so forth. This information is also used
1361 to restore the values of callee-saved registers in the function
1362 catching the exception.
1363
1364 If you are writing functions in assembly code, and those functions
1365 call other functions that throw exceptions, you must use assembly
1366 pseudo ops to ensure that appropriate exception unwind information is
1367 generated. Otherwise, if one of the functions called by your assembly
1368 code throws an exception, the run-time library will be unable to
1369 unwind the stack through your assembly code and your program will not
1370 behave correctly.
1371
1372 To illustrate the use of these pseudo ops, we will examine the code
1373 that G++ generates for the following C++ input:
1374
1375 @verbatim
1376 void callee (int *);
1377
1378 int
1379 caller ()
1380 {
1381 int i;
1382 callee (&i);
1383 return i;
1384 }
1385 @end verbatim
1386
1387 This example does not show how to throw or catch an exception from
1388 assembly code. That is a much more complex operation and should
1389 always be done in a high-level language, such as C++, that directly
1390 supports exceptions.
1391
1392 The code generated by one particular version of G++ when compiling the
1393 example above is:
1394
1395 @verbatim
1396 _Z6callerv:
1397 .fnstart
1398 .LFB2:
1399 @ Function supports interworking.
1400 @ args = 0, pretend = 0, frame = 8
1401 @ frame_needed = 1, uses_anonymous_args = 0
1402 stmfd sp!, {fp, lr}
1403 .save {fp, lr}
1404 .LCFI0:
1405 .setfp fp, sp, #4
1406 add fp, sp, #4
1407 .LCFI1:
1408 .pad #8
1409 sub sp, sp, #8
1410 .LCFI2:
1411 sub r3, fp, #8
1412 mov r0, r3
1413 bl _Z6calleePi
1414 ldr r3, [fp, #-8]
1415 mov r0, r3
1416 sub sp, fp, #4
1417 ldmfd sp!, {fp, lr}
1418 bx lr
1419 .LFE2:
1420 .fnend
1421 @end verbatim
1422
1423 Of course, the sequence of instructions varies based on the options
1424 you pass to GCC and on the version of GCC in use. The exact
1425 instructions are not important since we are focusing on the pseudo ops
1426 that are used to generate unwind information.
1427
1428 An important assumption made by the unwinder is that the stack frame
1429 does not change during the body of the function. In particular, since
1430 we assume that the assembly code does not itself throw an exception,
1431 the only point where an exception can be thrown is from a call, such
1432 as the @code{bl} instruction above. At each call site, the same saved
1433 registers (including @code{lr}, which indicates the return address)
1434 must be located in the same locations relative to the frame pointer.
1435
1436 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1437 op appears immediately before the first instruction of the function
1438 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1439 op appears immediately after the last instruction of the function.
1440 These pseudo ops specify the range of the function.
1441
1442 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1443 @code{.pad}) matters; their exact locations are irrelevant. In the
1444 example above, the compiler emits the pseudo ops with particular
1445 instructions. That makes it easier to understand the code, but it is
1446 not required for correctness. It would work just as well to emit all
1447 of the pseudo ops other than @code{.fnend} in the same order, but
1448 immediately after @code{.fnstart}.
1449
1450 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1451 indicates registers that have been saved to the stack so that they can
1452 be restored before the function returns. The argument to the
1453 @code{.save} pseudo op is a list of registers to save. If a register
1454 is ``callee-saved'' (as specified by the ABI) and is modified by the
1455 function you are writing, then your code must save the value before it
1456 is modified and restore the original value before the function
1457 returns. If an exception is thrown, the run-time library restores the
1458 values of these registers from their locations on the stack before
1459 returning control to the exception handler. (Of course, if an
1460 exception is not thrown, the function that contains the @code{.save}
1461 pseudo op restores these registers in the function epilogue, as is
1462 done with the @code{ldmfd} instruction above.)
1463
1464 You do not have to save callee-saved registers at the very beginning
1465 of the function and you do not need to use the @code{.save} pseudo op
1466 immediately following the point at which the registers are saved.
1467 However, if you modify a callee-saved register, you must save it on
1468 the stack before modifying it and before calling any functions which
1469 might throw an exception. And, you must use the @code{.save} pseudo
1470 op to indicate that you have done so.
1471
1472 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1473 modification of the stack pointer that does not save any registers.
1474 The argument is the number of bytes (in decimal) that are subtracted
1475 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1476 subtracting from the stack pointer increases the size of the stack.)
1477
1478 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1479 indicates the register that contains the frame pointer. The first
1480 argument is the register that is set, which is typically @code{fp}.
1481 The second argument indicates the register from which the frame
1482 pointer takes its value. The third argument, if present, is the value
1483 (in decimal) added to the register specified by the second argument to
1484 compute the value of the frame pointer. You should not modify the
1485 frame pointer in the body of the function.
1486
1487 If you do not use a frame pointer, then you should not use the
1488 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1489 should avoid modifying the stack pointer outside of the function
1490 prologue. Otherwise, the run-time library will be unable to find
1491 saved registers when it is unwinding the stack.
1492
1493 The pseudo ops described above are sufficient for writing assembly
1494 code that calls functions which may throw exceptions. If you need to
1495 know more about the object-file format used to represent unwind
1496 information, you may consult the @cite{Exception Handling ABI for the
1497 ARM Architecture} available from @uref{http://infocenter.arm.com}.
1498
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