1 @c Copyright (C) 1996-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
134 @code{cortex-m0plus},
137 @code{marvell-whitney},
140 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
141 @code{i80200} (Intel XScale processor)
142 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
145 The special name @code{all} may be used to allow the
146 assembler to accept instructions valid for any ARM processor.
148 In addition to the basic instruction set, the assembler can be told to
149 accept various extension mnemonics that extend the processor using the
150 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
151 is equivalent to specifying @code{-mcpu=ep9312}.
153 Multiple extensions may be specified, separated by a @code{+}. The
154 extensions should be specified in ascending alphabetical order.
156 Some extensions may be restricted to particular architectures; this is
157 documented in the list of extensions below.
159 Extension mnemonics may also be removed from those the assembler accepts.
160 This is done be prepending @code{no} to the option that adds the extension.
161 Extensions that are removed should be listed after all extensions which have
162 been added, again in ascending alphabetical order. For example,
163 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
166 The following extensions are currently supported:
168 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
169 @code{fp} (Floating Point Extensions for v8-A architecture),
170 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
175 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
177 @code{os} (Operating System for v6M architecture),
178 @code{sec} (Security Extensions for v6K and v7-A architectures),
179 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
180 @code{virt} (Virtualization Extensions for v7-A architecture, implies
185 @cindex @code{-march=} command line option, ARM
186 @item -march=@var{architecture}[+@var{extension}@dots{}]
187 This option specifies the target architecture. The assembler will issue
188 an error message if an attempt is made to assemble an instruction which
189 will not execute on the target architecture. The following architecture
190 names are recognized:
224 If both @code{-mcpu} and
225 @code{-march} are specified, the assembler will use
226 the setting for @code{-mcpu}.
228 The architecture option can be extended with the same instruction set
229 extension options as the @code{-mcpu} option.
231 @cindex @code{-mfpu=} command line option, ARM
232 @item -mfpu=@var{floating-point-format}
234 This option specifies the floating point format to assemble for. The
235 assembler will issue an error message if an attempt is made to assemble
236 an instruction which will not execute on the target floating point unit.
237 The following format options are recognized:
257 @code{vfpv3-d16-fp16},
272 @code{neon-fp-armv8},
274 @code{crypto-neon-fp-armv8}.
276 In addition to determining which instructions are assembled, this option
277 also affects the way in which the @code{.double} assembler directive behaves
278 when assembling little-endian code.
280 The default is dependent on the processor selected. For Architecture 5 or
281 later, the default is to assembler for VFP instructions; for earlier
282 architectures the default is to assemble for FPA instructions.
284 @cindex @code{-mthumb} command line option, ARM
286 This option specifies that the assembler should start assembling Thumb
287 instructions; that is, it should behave as though the file starts with a
288 @code{.code 16} directive.
290 @cindex @code{-mthumb-interwork} command line option, ARM
291 @item -mthumb-interwork
292 This option specifies that the output generated by the assembler should
293 be marked as supporting interworking.
295 @cindex @code{-mimplicit-it} command line option, ARM
296 @item -mimplicit-it=never
297 @itemx -mimplicit-it=always
298 @itemx -mimplicit-it=arm
299 @itemx -mimplicit-it=thumb
300 The @code{-mimplicit-it} option controls the behavior of the assembler when
301 conditional instructions are not enclosed in IT blocks.
302 There are four possible behaviors.
303 If @code{never} is specified, such constructs cause a warning in ARM
304 code and an error in Thumb-2 code.
305 If @code{always} is specified, such constructs are accepted in both
306 ARM and Thumb-2 code, where the IT instruction is added implicitly.
307 If @code{arm} is specified, such constructs are accepted in ARM code
308 and cause an error in Thumb-2 code.
309 If @code{thumb} is specified, such constructs cause a warning in ARM
310 code and are accepted in Thumb-2 code. If you omit this option, the
311 behavior is equivalent to @code{-mimplicit-it=arm}.
313 @cindex @code{-mapcs-26} command line option, ARM
314 @cindex @code{-mapcs-32} command line option, ARM
317 These options specify that the output generated by the assembler should
318 be marked as supporting the indicated version of the Arm Procedure.
321 @cindex @code{-matpcs} command line option, ARM
323 This option specifies that the output generated by the assembler should
324 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
325 enabled this option will cause the assembler to create an empty
326 debugging section in the object file called .arm.atpcs. Debuggers can
327 use this to determine the ABI being used by.
329 @cindex @code{-mapcs-float} command line option, ARM
331 This indicates the floating point variant of the APCS should be
332 used. In this variant floating point arguments are passed in FP
333 registers rather than integer registers.
335 @cindex @code{-mapcs-reentrant} command line option, ARM
336 @item -mapcs-reentrant
337 This indicates that the reentrant variant of the APCS should be used.
338 This variant supports position independent code.
340 @cindex @code{-mfloat-abi=} command line option, ARM
341 @item -mfloat-abi=@var{abi}
342 This option specifies that the output generated by the assembler should be
343 marked as using specified floating point ABI.
344 The following values are recognized:
350 @cindex @code{-eabi=} command line option, ARM
351 @item -meabi=@var{ver}
352 This option specifies which EABI version the produced object files should
354 The following values are recognized:
360 @cindex @code{-EB} command line option, ARM
362 This option specifies that the output generated by the assembler should
363 be marked as being encoded for a big-endian processor.
365 Note: If a program is being built for a system with big-endian data
366 and little-endian instructions then it should be assembled with the
367 @option{-EB} option, (all of it, code and data) and then linked with
368 the @option{--be8} option. This will reverse the endianness of the
369 instructions back to little-endian, but leave the data as big-endian.
371 @cindex @code{-EL} command line option, ARM
373 This option specifies that the output generated by the assembler should
374 be marked as being encoded for a little-endian processor.
376 @cindex @code{-k} command line option, ARM
377 @cindex PIC code generation for ARM
379 This option specifies that the output of the assembler should be marked
380 as position-independent code (PIC).
382 @cindex @code{--fix-v4bx} command line option, ARM
384 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
385 the linker option of the same name.
387 @cindex @code{-mwarn-deprecated} command line option, ARM
388 @item -mwarn-deprecated
389 @itemx -mno-warn-deprecated
390 Enable or disable warnings about using deprecated options or
391 features. The default is to warn.
393 @cindex @code{-mccs} command line option, ARM
395 Turns on CodeComposer Studio assembly syntax compatibility mode.
403 * ARM-Instruction-Set:: Instruction Set
404 * ARM-Chars:: Special Characters
405 * ARM-Regs:: Register Names
406 * ARM-Relocations:: Relocations
407 * ARM-Neon-Alignment:: NEON Alignment Specifiers
410 @node ARM-Instruction-Set
411 @subsection Instruction Set Syntax
412 Two slightly different syntaxes are support for ARM and THUMB
413 instructions. The default, @code{divided}, uses the old style where
414 ARM and THUMB instructions had their own, separate syntaxes. The new,
415 @code{unified} syntax, which can be selected via the @code{.syntax}
416 directive, and has the following main features:
420 Immediate operands do not require a @code{#} prefix.
423 The @code{IT} instruction may appear, and if it does it is validated
424 against subsequent conditional affixes. In ARM mode it does not
425 generate machine code, in THUMB mode it does.
428 For ARM instructions the conditional affixes always appear at the end
429 of the instruction. For THUMB instructions conditional affixes can be
430 used, but only inside the scope of an @code{IT} instruction.
433 All of the instructions new to the V6T2 architecture (and later) are
434 available. (Only a few such instructions can be written in the
435 @code{divided} syntax).
438 The @code{.N} and @code{.W} suffixes are recognized and honored.
441 All instructions set the flags if and only if they have an @code{s}
446 @subsection Special Characters
448 @cindex line comment character, ARM
449 @cindex ARM line comment character
450 The presence of a @samp{@@} anywhere on a line indicates the start of
451 a comment that extends to the end of that line.
453 If a @samp{#} appears as the first character of a line then the whole
454 line is treated as a comment, but in this case the line could also be
455 a logical line number directive (@pxref{Comments}) or a preprocessor
456 control command (@pxref{Preprocessing}).
458 @cindex line separator, ARM
459 @cindex statement separator, ARM
460 @cindex ARM line separator
461 The @samp{;} character can be used instead of a newline to separate
464 @cindex immediate character, ARM
465 @cindex ARM immediate character
466 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
468 @cindex identifiers, ARM
469 @cindex ARM identifiers
470 *TODO* Explain about /data modifier on symbols.
473 @subsection Register Names
475 @cindex ARM register names
476 @cindex register names, ARM
477 *TODO* Explain about ARM register naming, and the predefined names.
479 @node ARM-Relocations
480 @subsection ARM relocation generation
482 @cindex data relocations, ARM
483 @cindex ARM data relocations
484 Specific data relocations can be generated by putting the relocation name
485 in parentheses after the symbol name. For example:
491 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
493 The following relocations are supported:
509 For compatibility with older toolchains the assembler also accepts
510 @code{(PLT)} after branch targets. On legacy targets this will
511 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
512 targets it will encode either the @samp{R_ARM_CALL} or
513 @samp{R_ARM_JUMP24} relocation, as appropriate.
515 @cindex MOVW and MOVT relocations, ARM
516 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
517 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
518 respectively. For example to load the 32-bit address of foo into r0:
521 MOVW r0, #:lower16:foo
522 MOVT r0, #:upper16:foo
525 @node ARM-Neon-Alignment
526 @subsection NEON Alignment Specifiers
528 @cindex alignment for NEON instructions
529 Some NEON load/store instructions allow an optional address
531 The ARM documentation specifies that this is indicated by
532 @samp{@@ @var{align}}. However GAS already interprets
533 the @samp{@@} character as a "line comment" start,
534 so @samp{: @var{align}} is used instead. For example:
537 vld1.8 @{q0@}, [r0, :128]
540 @node ARM Floating Point
541 @section Floating Point
543 @cindex floating point, ARM (@sc{ieee})
544 @cindex ARM floating point (@sc{ieee})
545 The ARM family uses @sc{ieee} floating-point numbers.
548 @section ARM Machine Directives
550 @cindex machine directives, ARM
551 @cindex ARM machine directives
554 @c AAAAAAAAAAAAAAAAAAAAAAAAA
556 @cindex @code{.2byte} directive, ARM
557 @cindex @code{.4byte} directive, ARM
558 @cindex @code{.8byte} directive, ARM
559 @item .2byte @var{expression} [, @var{expression}]*
560 @itemx .4byte @var{expression} [, @var{expression}]*
561 @itemx .8byte @var{expression} [, @var{expression}]*
562 These directives write 2, 4 or 8 byte values to the output section.
564 @cindex @code{.align} directive, ARM
565 @item .align @var{expression} [, @var{expression}]
566 This is the generic @var{.align} directive. For the ARM however if the
567 first argument is zero (ie no alignment is needed) the assembler will
568 behave as if the argument had been 2 (ie pad to the next four byte
569 boundary). This is for compatibility with ARM's own assembler.
571 @cindex @code{.arch} directive, ARM
572 @item .arch @var{name}
573 Select the target architecture. Valid values for @var{name} are the same as
574 for the @option{-march} commandline option.
576 Specifying @code{.arch} clears any previously selected architecture
579 @cindex @code{.arch_extension} directive, ARM
580 @item .arch_extension @var{name}
581 Add or remove an architecture extension to the target architecture. Valid
582 values for @var{name} are the same as those accepted as architectural
583 extensions by the @option{-mcpu} commandline option.
585 @code{.arch_extension} may be used multiple times to add or remove extensions
586 incrementally to the architecture being compiled for.
588 @cindex @code{.arm} directive, ARM
590 This performs the same action as @var{.code 32}.
592 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
594 @cindex @code{.bss} directive, ARM
596 This directive switches to the @code{.bss} section.
598 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
600 @cindex @code{.cantunwind} directive, ARM
602 Prevents unwinding through the current function. No personality routine
603 or exception table data is required or permitted.
605 @cindex @code{.code} directive, ARM
606 @item .code @code{[16|32]}
607 This directive selects the instruction set being generated. The value 16
608 selects Thumb, with the value 32 selecting ARM.
610 @cindex @code{.cpu} directive, ARM
611 @item .cpu @var{name}
612 Select the target processor. Valid values for @var{name} are the same as
613 for the @option{-mcpu} commandline option.
615 Specifying @code{.cpu} clears any previously selected architecture
618 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
620 @cindex @code{.dn} and @code{.qn} directives, ARM
621 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
622 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
624 The @code{dn} and @code{qn} directives are used to create typed
625 and/or indexed register aliases for use in Advanced SIMD Extension
626 (Neon) instructions. The former should be used to create aliases
627 of double-precision registers, and the latter to create aliases of
628 quad-precision registers.
630 If these directives are used to create typed aliases, those aliases can
631 be used in Neon instructions instead of writing types after the mnemonic
632 or after each operand. For example:
641 This is equivalent to writing the following:
647 Aliases created using @code{dn} or @code{qn} can be destroyed using
650 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
652 @cindex @code{.eabi_attribute} directive, ARM
653 @item .eabi_attribute @var{tag}, @var{value}
654 Set the EABI object attribute @var{tag} to @var{value}.
656 The @var{tag} is either an attribute number, or one of the following:
657 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
658 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
659 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
660 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
661 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
662 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
663 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
664 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
665 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
666 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
667 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
668 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
669 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
670 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
671 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
672 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
673 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
674 @code{Tag_conformance}, @code{Tag_T2EE_use},
675 @code{Tag_Virtualization_use}
677 The @var{value} is either a @code{number}, @code{"string"}, or
678 @code{number, "string"} depending on the tag.
680 Note - the following legacy values are also accepted by @var{tag}:
681 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
682 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
684 @cindex @code{.even} directive, ARM
686 This directive aligns to an even-numbered address.
688 @cindex @code{.extend} directive, ARM
689 @cindex @code{.ldouble} directive, ARM
690 @item .extend @var{expression} [, @var{expression}]*
691 @itemx .ldouble @var{expression} [, @var{expression}]*
692 These directives write 12byte long double floating-point values to the
693 output section. These are not compatible with current ARM processors
696 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
699 @cindex @code{.fnend} directive, ARM
701 Marks the end of a function with an unwind table entry. The unwind index
702 table entry is created when this directive is processed.
704 If no personality routine has been specified then standard personality
705 routine 0 or 1 will be used, depending on the number of unwind opcodes
709 @cindex @code{.fnstart} directive, ARM
711 Marks the start of a function with an unwind table entry.
713 @cindex @code{.force_thumb} directive, ARM
715 This directive forces the selection of Thumb instructions, even if the
716 target processor does not support those instructions
718 @cindex @code{.fpu} directive, ARM
719 @item .fpu @var{name}
720 Select the floating-point unit to assemble for. Valid values for @var{name}
721 are the same as for the @option{-mfpu} commandline option.
723 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
724 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
726 @cindex @code{.handlerdata} directive, ARM
728 Marks the end of the current function, and the start of the exception table
729 entry for that function. Anything between this directive and the
730 @code{.fnend} directive will be added to the exception table entry.
732 Must be preceded by a @code{.personality} or @code{.personalityindex}
735 @c IIIIIIIIIIIIIIIIIIIIIIIIII
737 @cindex @code{.inst} directive, ARM
738 @item .inst @var{opcode} [ , @dots{} ]
739 @itemx .inst.n @var{opcode} [ , @dots{} ]
740 @itemx .inst.w @var{opcode} [ , @dots{} ]
741 Generates the instruction corresponding to the numerical value @var{opcode}.
742 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
743 specified explicitly, overriding the normal encoding rules.
745 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
746 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
747 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
749 @item .ldouble @var{expression} [, @var{expression}]*
752 @cindex @code{.ltorg} directive, ARM
754 This directive causes the current contents of the literal pool to be
755 dumped into the current section (which is assumed to be the .text
756 section) at the current location (aligned to a word boundary).
757 @code{GAS} maintains a separate literal pool for each section and each
758 sub-section. The @code{.ltorg} directive will only affect the literal
759 pool of the current section and sub-section. At the end of assembly
760 all remaining, un-empty literal pools will automatically be dumped.
762 Note - older versions of @code{GAS} would dump the current literal
763 pool any time a section change occurred. This is no longer done, since
764 it prevents accurate control of the placement of literal pools.
766 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
768 @cindex @code{.movsp} directive, ARM
769 @item .movsp @var{reg} [, #@var{offset}]
770 Tell the unwinder that @var{reg} contains an offset from the current
771 stack pointer. If @var{offset} is not specified then it is assumed to be
774 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
775 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
777 @cindex @code{.object_arch} directive, ARM
778 @item .object_arch @var{name}
779 Override the architecture recorded in the EABI object attribute section.
780 Valid values for @var{name} are the same as for the @code{.arch} directive.
781 Typically this is useful when code uses runtime detection of CPU features.
783 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
785 @cindex @code{.packed} directive, ARM
786 @item .packed @var{expression} [, @var{expression}]*
787 This directive writes 12-byte packed floating-point values to the
788 output section. These are not compatible with current ARM processors
792 @cindex @code{.pad} directive, ARM
793 @item .pad #@var{count}
794 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
795 A positive value indicates the function prologue allocated stack space by
796 decrementing the stack pointer.
798 @cindex @code{.personality} directive, ARM
799 @item .personality @var{name}
800 Sets the personality routine for the current function to @var{name}.
802 @cindex @code{.personalityindex} directive, ARM
803 @item .personalityindex @var{index}
804 Sets the personality routine for the current function to the EABI standard
805 routine number @var{index}
807 @cindex @code{.pool} directive, ARM
809 This is a synonym for .ltorg.
811 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
812 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
814 @cindex @code{.req} directive, ARM
815 @item @var{name} .req @var{register name}
816 This creates an alias for @var{register name} called @var{name}. For
823 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
826 @cindex @code{.save} directive, ARM
827 @item .save @var{reglist}
828 Generate unwinder annotations to restore the registers in @var{reglist}.
829 The format of @var{reglist} is the same as the corresponding store-multiple
833 @exdent @emph{core registers}
834 .save @{r4, r5, r6, lr@}
835 stmfd sp!, @{r4, r5, r6, lr@}
836 @exdent @emph{FPA registers}
839 @exdent @emph{VFP registers}
840 .save @{d8, d9, d10@}
841 fstmdx sp!, @{d8, d9, d10@}
842 @exdent @emph{iWMMXt registers}
844 wstrd wr11, [sp, #-8]!
845 wstrd wr10, [sp, #-8]!
848 wstrd wr11, [sp, #-8]!
850 wstrd wr10, [sp, #-8]!
854 @cindex @code{.setfp} directive, ARM
855 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
856 Make all unwinder annotations relative to a frame pointer. Without this
857 the unwinder will use offsets from the stack pointer.
859 The syntax of this directive is the same as the @code{add} or @code{mov}
860 instruction used to set the frame pointer. @var{spreg} must be either
861 @code{sp} or mentioned in a previous @code{.movsp} directive.
871 @cindex @code{.secrel32} directive, ARM
872 @item .secrel32 @var{expression} [, @var{expression}]*
873 This directive emits relocations that evaluate to the section-relative
874 offset of each expression's symbol. This directive is only supported
877 @cindex @code{.syntax} directive, ARM
878 @item .syntax [@code{unified} | @code{divided}]
879 This directive sets the Instruction Set Syntax as described in the
880 @ref{ARM-Instruction-Set} section.
882 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
884 @cindex @code{.thumb} directive, ARM
886 This performs the same action as @var{.code 16}.
888 @cindex @code{.thumb_func} directive, ARM
890 This directive specifies that the following symbol is the name of a
891 Thumb encoded function. This information is necessary in order to allow
892 the assembler and linker to generate correct code for interworking
893 between Arm and Thumb instructions and should be used even if
894 interworking is not going to be performed. The presence of this
895 directive also implies @code{.thumb}
897 This directive is not neccessary when generating EABI objects. On these
898 targets the encoding is implicit when generating Thumb code.
900 @cindex @code{.thumb_set} directive, ARM
902 This performs the equivalent of a @code{.set} directive in that it
903 creates a symbol which is an alias for another symbol (possibly not yet
904 defined). This directive also has the added property in that it marks
905 the aliased symbol as being a thumb function entry point, in the same
906 way that the @code{.thumb_func} directive does.
908 @cindex @code{.tlsdescseq} directive, ARM
909 @item .tlsdescseq @var{tls-variable}
910 This directive is used to annotate parts of an inlined TLS descriptor
911 trampoline. Normally the trampoline is provided by the linker, and
912 this directive is not needed.
914 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
916 @cindex @code{.unreq} directive, ARM
917 @item .unreq @var{alias-name}
918 This undefines a register alias which was previously defined using the
919 @code{req}, @code{dn} or @code{qn} directives. For example:
926 An error occurs if the name is undefined. Note - this pseudo op can
927 be used to delete builtin in register name aliases (eg 'r0'). This
928 should only be done if it is really necessary.
930 @cindex @code{.unwind_raw} directive, ARM
931 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
932 Insert one of more arbitary unwind opcode bytes, which are known to adjust
933 the stack pointer by @var{offset} bytes.
935 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
938 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
940 @cindex @code{.vsave} directive, ARM
941 @item .vsave @var{vfp-reglist}
942 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
943 using FLDMD. Also works for VFPv3 registers
944 that are to be restored using VLDM.
945 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
949 @exdent @emph{VFP registers}
950 .vsave @{d8, d9, d10@}
951 fstmdd sp!, @{d8, d9, d10@}
952 @exdent @emph{VFPv3 registers}
953 .vsave @{d15, d16, d17@}
954 vstm sp!, @{d15, d16, d17@}
957 Since FLDMX and FSTMX are now deprecated, this directive should be
958 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
960 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
961 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
962 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
963 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
971 @cindex opcodes for ARM
972 @code{@value{AS}} implements all the standard ARM opcodes. It also
973 implements several pseudo opcodes, including several synthetic load
978 @cindex @code{NOP} pseudo op, ARM
984 This pseudo op will always evaluate to a legal ARM instruction that does
985 nothing. Currently it will evaluate to MOV r0, r0.
987 @cindex @code{LDR reg,=<label>} pseudo op, ARM
990 ldr <register> , = <expression>
993 If expression evaluates to a numeric constant then a MOV or MVN
994 instruction will be used in place of the LDR instruction, if the
995 constant can be generated by either of these instructions. Otherwise
996 the constant will be placed into the nearest literal pool (if it not
997 already there) and a PC relative LDR instruction will be generated.
999 @cindex @code{ADR reg,<label>} pseudo op, ARM
1002 adr <register> <label>
1005 This instruction will load the address of @var{label} into the indicated
1006 register. The instruction will evaluate to a PC relative ADD or SUB
1007 instruction depending upon where the label is located. If the label is
1008 out of range, or if it is not defined in the same file (and section) as
1009 the ADR instruction, then an error will be generated. This instruction
1010 will not make use of the literal pool.
1012 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1015 adrl <register> <label>
1018 This instruction will load the address of @var{label} into the indicated
1019 register. The instruction will evaluate to one or two PC relative ADD
1020 or SUB instructions depending upon where the label is located. If a
1021 second instruction is not needed a NOP instruction will be generated in
1022 its place, so that this instruction is always 8 bytes long.
1024 If the label is out of range, or if it is not defined in the same file
1025 (and section) as the ADRL instruction, then an error will be generated.
1026 This instruction will not make use of the literal pool.
1030 For information on the ARM or Thumb instruction sets, see @cite{ARM
1031 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1034 @node ARM Mapping Symbols
1035 @section Mapping Symbols
1037 The ARM ELF specification requires that special symbols be inserted
1038 into object files to mark certain features:
1044 At the start of a region of code containing ARM instructions.
1048 At the start of a region of code containing THUMB instructions.
1052 At the start of a region of data.
1056 The assembler will automatically insert these symbols for you - there
1057 is no need to code them yourself. Support for tagging symbols ($b,
1058 $f, $p and $m) which is also mentioned in the current ARM ELF
1059 specification is not implemented. This is because they have been
1060 dropped from the new EABI and so tools cannot rely upon their
1063 @node ARM Unwinding Tutorial
1066 The ABI for the ARM Architecture specifies a standard format for
1067 exception unwind information. This information is used when an
1068 exception is thrown to determine where control should be transferred.
1069 In particular, the unwind information is used to determine which
1070 function called the function that threw the exception, and which
1071 function called that one, and so forth. This information is also used
1072 to restore the values of callee-saved registers in the function
1073 catching the exception.
1075 If you are writing functions in assembly code, and those functions
1076 call other functions that throw exceptions, you must use assembly
1077 pseudo ops to ensure that appropriate exception unwind information is
1078 generated. Otherwise, if one of the functions called by your assembly
1079 code throws an exception, the run-time library will be unable to
1080 unwind the stack through your assembly code and your program will not
1083 To illustrate the use of these pseudo ops, we will examine the code
1084 that G++ generates for the following C++ input:
1087 void callee (int *);
1098 This example does not show how to throw or catch an exception from
1099 assembly code. That is a much more complex operation and should
1100 always be done in a high-level language, such as C++, that directly
1101 supports exceptions.
1103 The code generated by one particular version of G++ when compiling the
1110 @ Function supports interworking.
1111 @ args = 0, pretend = 0, frame = 8
1112 @ frame_needed = 1, uses_anonymous_args = 0
1134 Of course, the sequence of instructions varies based on the options
1135 you pass to GCC and on the version of GCC in use. The exact
1136 instructions are not important since we are focusing on the pseudo ops
1137 that are used to generate unwind information.
1139 An important assumption made by the unwinder is that the stack frame
1140 does not change during the body of the function. In particular, since
1141 we assume that the assembly code does not itself throw an exception,
1142 the only point where an exception can be thrown is from a call, such
1143 as the @code{bl} instruction above. At each call site, the same saved
1144 registers (including @code{lr}, which indicates the return address)
1145 must be located in the same locations relative to the frame pointer.
1147 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1148 op appears immediately before the first instruction of the function
1149 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1150 op appears immediately after the last instruction of the function.
1151 These pseudo ops specify the range of the function.
1153 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1154 @code{.pad}) matters; their exact locations are irrelevant. In the
1155 example above, the compiler emits the pseudo ops with particular
1156 instructions. That makes it easier to understand the code, but it is
1157 not required for correctness. It would work just as well to emit all
1158 of the pseudo ops other than @code{.fnend} in the same order, but
1159 immediately after @code{.fnstart}.
1161 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1162 indicates registers that have been saved to the stack so that they can
1163 be restored before the function returns. The argument to the
1164 @code{.save} pseudo op is a list of registers to save. If a register
1165 is ``callee-saved'' (as specified by the ABI) and is modified by the
1166 function you are writing, then your code must save the value before it
1167 is modified and restore the original value before the function
1168 returns. If an exception is thrown, the run-time library restores the
1169 values of these registers from their locations on the stack before
1170 returning control to the exception handler. (Of course, if an
1171 exception is not thrown, the function that contains the @code{.save}
1172 pseudo op restores these registers in the function epilogue, as is
1173 done with the @code{ldmfd} instruction above.)
1175 You do not have to save callee-saved registers at the very beginning
1176 of the function and you do not need to use the @code{.save} pseudo op
1177 immediately following the point at which the registers are saved.
1178 However, if you modify a callee-saved register, you must save it on
1179 the stack before modifying it and before calling any functions which
1180 might throw an exception. And, you must use the @code{.save} pseudo
1181 op to indicate that you have done so.
1183 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1184 modification of the stack pointer that does not save any registers.
1185 The argument is the number of bytes (in decimal) that are subtracted
1186 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1187 subtracting from the stack pointer increases the size of the stack.)
1189 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1190 indicates the register that contains the frame pointer. The first
1191 argument is the register that is set, which is typically @code{fp}.
1192 The second argument indicates the register from which the frame
1193 pointer takes its value. The third argument, if present, is the value
1194 (in decimal) added to the register specified by the second argument to
1195 compute the value of the frame pointer. You should not modify the
1196 frame pointer in the body of the function.
1198 If you do not use a frame pointer, then you should not use the
1199 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1200 should avoid modifying the stack pointer outside of the function
1201 prologue. Otherwise, the run-time library will be unable to find
1202 saved registers when it is unwinding the stack.
1204 The pseudo ops described above are sufficient for writing assembly
1205 code that calls functions which may throw exceptions. If you need to
1206 know more about the object-file format used to represent unwind
1207 information, you may consult the @cite{Exception Handling ABI for the
1208 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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