[ARM] Add crypto-neon-fp-armv8.1 as an fpu option
[deliverable/binutils-gdb.git] / gas / doc / c-arm.texi
1 @c Copyright (C) 1996-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
4
5 @ifset GENERIC
6 @page
7 @node ARM-Dependent
8 @chapter ARM Dependent Features
9 @end ifset
10
11 @ifclear GENERIC
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
14 @end ifclear
15
16 @cindex ARM support
17 @cindex Thumb support
18 @menu
19 * ARM Options:: Options
20 * ARM Syntax:: Syntax
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
26 @end menu
27
28 @node ARM Options
29 @section Options
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
32
33 @table @code
34
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
40 recognized:
41 @code{arm1},
42 @code{arm2},
43 @code{arm250},
44 @code{arm3},
45 @code{arm6},
46 @code{arm60},
47 @code{arm600},
48 @code{arm610},
49 @code{arm620},
50 @code{arm7},
51 @code{arm7m},
52 @code{arm7d},
53 @code{arm7dm},
54 @code{arm7di},
55 @code{arm7dmi},
56 @code{arm70},
57 @code{arm700},
58 @code{arm700i},
59 @code{arm710},
60 @code{arm710t},
61 @code{arm720},
62 @code{arm720t},
63 @code{arm740t},
64 @code{arm710c},
65 @code{arm7100},
66 @code{arm7500},
67 @code{arm7500fe},
68 @code{arm7t},
69 @code{arm7tdmi},
70 @code{arm7tdmi-s},
71 @code{arm8},
72 @code{arm810},
73 @code{strongarm},
74 @code{strongarm1},
75 @code{strongarm110},
76 @code{strongarm1100},
77 @code{strongarm1110},
78 @code{arm9},
79 @code{arm920},
80 @code{arm920t},
81 @code{arm922t},
82 @code{arm940t},
83 @code{arm9tdmi},
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
86 @code{arm9e},
87 @code{arm926e},
88 @code{arm926ej-s},
89 @code{arm946e-r0},
90 @code{arm946e},
91 @code{arm946e-s},
92 @code{arm966e-r0},
93 @code{arm966e},
94 @code{arm966e-s},
95 @code{arm968e-s},
96 @code{arm10t},
97 @code{arm10tdmi},
98 @code{arm10e},
99 @code{arm1020},
100 @code{arm1020t},
101 @code{arm1020e},
102 @code{arm1022e},
103 @code{arm1026ej-s},
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
109 @code{arm1136j-s},
110 @code{arm1136jf-s},
111 @code{arm1156t2-s},
112 @code{arm1156t2f-s},
113 @code{arm1176jz-s},
114 @code{arm1176jzf-s},
115 @code{mpcore},
116 @code{mpcorenovfp},
117 @code{cortex-a5},
118 @code{cortex-a7},
119 @code{cortex-a8},
120 @code{cortex-a9},
121 @code{cortex-a15},
122 @code{cortex-a53},
123 @code{cortex-a57},
124 @code{cortex-a72},
125 @code{cortex-r4},
126 @code{cortex-r4f},
127 @code{cortex-r5},
128 @code{cortex-r7},
129 @code{cortex-m7},
130 @code{cortex-m4},
131 @code{cortex-m3},
132 @code{cortex-m1},
133 @code{cortex-m0},
134 @code{cortex-m0plus},
135 @code{exynos-m1},
136 @code{marvell-pj4},
137 @code{marvell-whitney},
138 @code{xgene1},
139 @code{xgene2},
140 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
141 @code{i80200} (Intel XScale processor)
142 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
143 and
144 @code{xscale}.
145 The special name @code{all} may be used to allow the
146 assembler to accept instructions valid for any ARM processor.
147
148 In addition to the basic instruction set, the assembler can be told to
149 accept various extension mnemonics that extend the processor using the
150 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
151 is equivalent to specifying @code{-mcpu=ep9312}.
152
153 Multiple extensions may be specified, separated by a @code{+}. The
154 extensions should be specified in ascending alphabetical order.
155
156 Some extensions may be restricted to particular architectures; this is
157 documented in the list of extensions below.
158
159 Extension mnemonics may also be removed from those the assembler accepts.
160 This is done be prepending @code{no} to the option that adds the extension.
161 Extensions that are removed should be listed after all extensions which have
162 been added, again in ascending alphabetical order. For example,
163 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
164
165
166 The following extensions are currently supported:
167 @code{crc}
168 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
169 @code{fp} (Floating Point Extensions for v8-A architecture),
170 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
171 @code{iwmmxt},
172 @code{iwmmxt2},
173 @code{xscale},
174 @code{maverick},
175 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
176 architectures),
177 @code{os} (Operating System for v6M architecture),
178 @code{sec} (Security Extensions for v6K and v7-A architectures),
179 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
180 @code{virt} (Virtualization Extensions for v7-A architecture, implies
181 @code{idiv}),
182 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
183 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
184 @code{simd})
185 and
186 @code{xscale}.
187
188 @cindex @code{-march=} command line option, ARM
189 @item -march=@var{architecture}[+@var{extension}@dots{}]
190 This option specifies the target architecture. The assembler will issue
191 an error message if an attempt is made to assemble an instruction which
192 will not execute on the target architecture. The following architecture
193 names are recognized:
194 @code{armv1},
195 @code{armv2},
196 @code{armv2a},
197 @code{armv2s},
198 @code{armv3},
199 @code{armv3m},
200 @code{armv4},
201 @code{armv4xm},
202 @code{armv4t},
203 @code{armv4txm},
204 @code{armv5},
205 @code{armv5t},
206 @code{armv5txm},
207 @code{armv5te},
208 @code{armv5texp},
209 @code{armv6},
210 @code{armv6j},
211 @code{armv6k},
212 @code{armv6z},
213 @code{armv6zk},
214 @code{armv6-m},
215 @code{armv6s-m},
216 @code{armv7},
217 @code{armv7-a},
218 @code{armv7ve},
219 @code{armv7-r},
220 @code{armv7-m},
221 @code{armv7e-m},
222 @code{armv8-a},
223 @code{armv8.1-a},
224 @code{iwmmxt}
225 @code{iwmmxt2}
226 and
227 @code{xscale}.
228 If both @code{-mcpu} and
229 @code{-march} are specified, the assembler will use
230 the setting for @code{-mcpu}.
231
232 The architecture option can be extended with the same instruction set
233 extension options as the @code{-mcpu} option.
234
235 @cindex @code{-mfpu=} command line option, ARM
236 @item -mfpu=@var{floating-point-format}
237
238 This option specifies the floating point format to assemble for. The
239 assembler will issue an error message if an attempt is made to assemble
240 an instruction which will not execute on the target floating point unit.
241 The following format options are recognized:
242 @code{softfpa},
243 @code{fpe},
244 @code{fpe2},
245 @code{fpe3},
246 @code{fpa},
247 @code{fpa10},
248 @code{fpa11},
249 @code{arm7500fe},
250 @code{softvfp},
251 @code{softvfp+vfp},
252 @code{vfp},
253 @code{vfp10},
254 @code{vfp10-r0},
255 @code{vfp9},
256 @code{vfpxd},
257 @code{vfpv2},
258 @code{vfpv3},
259 @code{vfpv3-fp16},
260 @code{vfpv3-d16},
261 @code{vfpv3-d16-fp16},
262 @code{vfpv3xd},
263 @code{vfpv3xd-d16},
264 @code{vfpv4},
265 @code{vfpv4-d16},
266 @code{fpv4-sp-d16},
267 @code{fpv5-sp-d16},
268 @code{fpv5-d16},
269 @code{fp-armv8},
270 @code{arm1020t},
271 @code{arm1020e},
272 @code{arm1136jf-s},
273 @code{maverick},
274 @code{neon},
275 @code{neon-vfpv4},
276 @code{neon-fp-armv8},
277 @code{crypto-neon-fp-armv8},
278 @code{neon-fp-armv8.1}
279 and
280 @code{crypto-neon-fp-armv8.1}.
281
282 In addition to determining which instructions are assembled, this option
283 also affects the way in which the @code{.double} assembler directive behaves
284 when assembling little-endian code.
285
286 The default is dependent on the processor selected. For Architecture 5 or
287 later, the default is to assembler for VFP instructions; for earlier
288 architectures the default is to assemble for FPA instructions.
289
290 @cindex @code{-mthumb} command line option, ARM
291 @item -mthumb
292 This option specifies that the assembler should start assembling Thumb
293 instructions; that is, it should behave as though the file starts with a
294 @code{.code 16} directive.
295
296 @cindex @code{-mthumb-interwork} command line option, ARM
297 @item -mthumb-interwork
298 This option specifies that the output generated by the assembler should
299 be marked as supporting interworking.
300
301 @cindex @code{-mimplicit-it} command line option, ARM
302 @item -mimplicit-it=never
303 @itemx -mimplicit-it=always
304 @itemx -mimplicit-it=arm
305 @itemx -mimplicit-it=thumb
306 The @code{-mimplicit-it} option controls the behavior of the assembler when
307 conditional instructions are not enclosed in IT blocks.
308 There are four possible behaviors.
309 If @code{never} is specified, such constructs cause a warning in ARM
310 code and an error in Thumb-2 code.
311 If @code{always} is specified, such constructs are accepted in both
312 ARM and Thumb-2 code, where the IT instruction is added implicitly.
313 If @code{arm} is specified, such constructs are accepted in ARM code
314 and cause an error in Thumb-2 code.
315 If @code{thumb} is specified, such constructs cause a warning in ARM
316 code and are accepted in Thumb-2 code. If you omit this option, the
317 behavior is equivalent to @code{-mimplicit-it=arm}.
318
319 @cindex @code{-mapcs-26} command line option, ARM
320 @cindex @code{-mapcs-32} command line option, ARM
321 @item -mapcs-26
322 @itemx -mapcs-32
323 These options specify that the output generated by the assembler should
324 be marked as supporting the indicated version of the Arm Procedure.
325 Calling Standard.
326
327 @cindex @code{-matpcs} command line option, ARM
328 @item -matpcs
329 This option specifies that the output generated by the assembler should
330 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
331 enabled this option will cause the assembler to create an empty
332 debugging section in the object file called .arm.atpcs. Debuggers can
333 use this to determine the ABI being used by.
334
335 @cindex @code{-mapcs-float} command line option, ARM
336 @item -mapcs-float
337 This indicates the floating point variant of the APCS should be
338 used. In this variant floating point arguments are passed in FP
339 registers rather than integer registers.
340
341 @cindex @code{-mapcs-reentrant} command line option, ARM
342 @item -mapcs-reentrant
343 This indicates that the reentrant variant of the APCS should be used.
344 This variant supports position independent code.
345
346 @cindex @code{-mfloat-abi=} command line option, ARM
347 @item -mfloat-abi=@var{abi}
348 This option specifies that the output generated by the assembler should be
349 marked as using specified floating point ABI.
350 The following values are recognized:
351 @code{soft},
352 @code{softfp}
353 and
354 @code{hard}.
355
356 @cindex @code{-eabi=} command line option, ARM
357 @item -meabi=@var{ver}
358 This option specifies which EABI version the produced object files should
359 conform to.
360 The following values are recognized:
361 @code{gnu},
362 @code{4}
363 and
364 @code{5}.
365
366 @cindex @code{-EB} command line option, ARM
367 @item -EB
368 This option specifies that the output generated by the assembler should
369 be marked as being encoded for a big-endian processor.
370
371 Note: If a program is being built for a system with big-endian data
372 and little-endian instructions then it should be assembled with the
373 @option{-EB} option, (all of it, code and data) and then linked with
374 the @option{--be8} option. This will reverse the endianness of the
375 instructions back to little-endian, but leave the data as big-endian.
376
377 @cindex @code{-EL} command line option, ARM
378 @item -EL
379 This option specifies that the output generated by the assembler should
380 be marked as being encoded for a little-endian processor.
381
382 @cindex @code{-k} command line option, ARM
383 @cindex PIC code generation for ARM
384 @item -k
385 This option specifies that the output of the assembler should be marked
386 as position-independent code (PIC).
387
388 @cindex @code{--fix-v4bx} command line option, ARM
389 @item --fix-v4bx
390 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
391 the linker option of the same name.
392
393 @cindex @code{-mwarn-deprecated} command line option, ARM
394 @item -mwarn-deprecated
395 @itemx -mno-warn-deprecated
396 Enable or disable warnings about using deprecated options or
397 features. The default is to warn.
398
399 @cindex @code{-mccs} command line option, ARM
400 @item -mccs
401 Turns on CodeComposer Studio assembly syntax compatibility mode.
402
403 @cindex @code{-mwarn-syms} command line option, ARM
404 @item -mwarn-syms
405 @itemx -mno-warn-syms
406 Enable or disable warnings about symbols that match the names of ARM
407 instructions. The default is to warn.
408
409 @end table
410
411
412 @node ARM Syntax
413 @section Syntax
414 @menu
415 * ARM-Instruction-Set:: Instruction Set
416 * ARM-Chars:: Special Characters
417 * ARM-Regs:: Register Names
418 * ARM-Relocations:: Relocations
419 * ARM-Neon-Alignment:: NEON Alignment Specifiers
420 @end menu
421
422 @node ARM-Instruction-Set
423 @subsection Instruction Set Syntax
424 Two slightly different syntaxes are support for ARM and THUMB
425 instructions. The default, @code{divided}, uses the old style where
426 ARM and THUMB instructions had their own, separate syntaxes. The new,
427 @code{unified} syntax, which can be selected via the @code{.syntax}
428 directive, and has the following main features:
429
430 @itemize @bullet
431 @item
432 Immediate operands do not require a @code{#} prefix.
433
434 @item
435 The @code{IT} instruction may appear, and if it does it is validated
436 against subsequent conditional affixes. In ARM mode it does not
437 generate machine code, in THUMB mode it does.
438
439 @item
440 For ARM instructions the conditional affixes always appear at the end
441 of the instruction. For THUMB instructions conditional affixes can be
442 used, but only inside the scope of an @code{IT} instruction.
443
444 @item
445 All of the instructions new to the V6T2 architecture (and later) are
446 available. (Only a few such instructions can be written in the
447 @code{divided} syntax).
448
449 @item
450 The @code{.N} and @code{.W} suffixes are recognized and honored.
451
452 @item
453 All instructions set the flags if and only if they have an @code{s}
454 affix.
455 @end itemize
456
457 @node ARM-Chars
458 @subsection Special Characters
459
460 @cindex line comment character, ARM
461 @cindex ARM line comment character
462 The presence of a @samp{@@} anywhere on a line indicates the start of
463 a comment that extends to the end of that line.
464
465 If a @samp{#} appears as the first character of a line then the whole
466 line is treated as a comment, but in this case the line could also be
467 a logical line number directive (@pxref{Comments}) or a preprocessor
468 control command (@pxref{Preprocessing}).
469
470 @cindex line separator, ARM
471 @cindex statement separator, ARM
472 @cindex ARM line separator
473 The @samp{;} character can be used instead of a newline to separate
474 statements.
475
476 @cindex immediate character, ARM
477 @cindex ARM immediate character
478 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
479
480 @cindex identifiers, ARM
481 @cindex ARM identifiers
482 *TODO* Explain about /data modifier on symbols.
483
484 @node ARM-Regs
485 @subsection Register Names
486
487 @cindex ARM register names
488 @cindex register names, ARM
489 *TODO* Explain about ARM register naming, and the predefined names.
490
491 @node ARM-Relocations
492 @subsection ARM relocation generation
493
494 @cindex data relocations, ARM
495 @cindex ARM data relocations
496 Specific data relocations can be generated by putting the relocation name
497 in parentheses after the symbol name. For example:
498
499 @smallexample
500 .word foo(TARGET1)
501 @end smallexample
502
503 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
504 @var{foo}.
505 The following relocations are supported:
506 @code{GOT},
507 @code{GOTOFF},
508 @code{TARGET1},
509 @code{TARGET2},
510 @code{SBREL},
511 @code{TLSGD},
512 @code{TLSLDM},
513 @code{TLSLDO},
514 @code{TLSDESC},
515 @code{TLSCALL},
516 @code{GOTTPOFF},
517 @code{GOT_PREL}
518 and
519 @code{TPOFF}.
520
521 For compatibility with older toolchains the assembler also accepts
522 @code{(PLT)} after branch targets. On legacy targets this will
523 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
524 targets it will encode either the @samp{R_ARM_CALL} or
525 @samp{R_ARM_JUMP24} relocation, as appropriate.
526
527 @cindex MOVW and MOVT relocations, ARM
528 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
529 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
530 respectively. For example to load the 32-bit address of foo into r0:
531
532 @smallexample
533 MOVW r0, #:lower16:foo
534 MOVT r0, #:upper16:foo
535 @end smallexample
536
537 @node ARM-Neon-Alignment
538 @subsection NEON Alignment Specifiers
539
540 @cindex alignment for NEON instructions
541 Some NEON load/store instructions allow an optional address
542 alignment qualifier.
543 The ARM documentation specifies that this is indicated by
544 @samp{@@ @var{align}}. However GAS already interprets
545 the @samp{@@} character as a "line comment" start,
546 so @samp{: @var{align}} is used instead. For example:
547
548 @smallexample
549 vld1.8 @{q0@}, [r0, :128]
550 @end smallexample
551
552 @node ARM Floating Point
553 @section Floating Point
554
555 @cindex floating point, ARM (@sc{ieee})
556 @cindex ARM floating point (@sc{ieee})
557 The ARM family uses @sc{ieee} floating-point numbers.
558
559 @node ARM Directives
560 @section ARM Machine Directives
561
562 @cindex machine directives, ARM
563 @cindex ARM machine directives
564 @table @code
565
566 @c AAAAAAAAAAAAAAAAAAAAAAAAA
567
568 @cindex @code{.2byte} directive, ARM
569 @cindex @code{.4byte} directive, ARM
570 @cindex @code{.8byte} directive, ARM
571 @item .2byte @var{expression} [, @var{expression}]*
572 @itemx .4byte @var{expression} [, @var{expression}]*
573 @itemx .8byte @var{expression} [, @var{expression}]*
574 These directives write 2, 4 or 8 byte values to the output section.
575
576 @cindex @code{.align} directive, ARM
577 @item .align @var{expression} [, @var{expression}]
578 This is the generic @var{.align} directive. For the ARM however if the
579 first argument is zero (ie no alignment is needed) the assembler will
580 behave as if the argument had been 2 (ie pad to the next four byte
581 boundary). This is for compatibility with ARM's own assembler.
582
583 @cindex @code{.arch} directive, ARM
584 @item .arch @var{name}
585 Select the target architecture. Valid values for @var{name} are the same as
586 for the @option{-march} commandline option.
587
588 Specifying @code{.arch} clears any previously selected architecture
589 extensions.
590
591 @cindex @code{.arch_extension} directive, ARM
592 @item .arch_extension @var{name}
593 Add or remove an architecture extension to the target architecture. Valid
594 values for @var{name} are the same as those accepted as architectural
595 extensions by the @option{-mcpu} commandline option.
596
597 @code{.arch_extension} may be used multiple times to add or remove extensions
598 incrementally to the architecture being compiled for.
599
600 @cindex @code{.arm} directive, ARM
601 @item .arm
602 This performs the same action as @var{.code 32}.
603
604 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
605
606 @cindex @code{.bss} directive, ARM
607 @item .bss
608 This directive switches to the @code{.bss} section.
609
610 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
611
612 @cindex @code{.cantunwind} directive, ARM
613 @item .cantunwind
614 Prevents unwinding through the current function. No personality routine
615 or exception table data is required or permitted.
616
617 @cindex @code{.code} directive, ARM
618 @item .code @code{[16|32]}
619 This directive selects the instruction set being generated. The value 16
620 selects Thumb, with the value 32 selecting ARM.
621
622 @cindex @code{.cpu} directive, ARM
623 @item .cpu @var{name}
624 Select the target processor. Valid values for @var{name} are the same as
625 for the @option{-mcpu} commandline option.
626
627 Specifying @code{.cpu} clears any previously selected architecture
628 extensions.
629
630 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
631
632 @cindex @code{.dn} and @code{.qn} directives, ARM
633 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
634 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
635
636 The @code{dn} and @code{qn} directives are used to create typed
637 and/or indexed register aliases for use in Advanced SIMD Extension
638 (Neon) instructions. The former should be used to create aliases
639 of double-precision registers, and the latter to create aliases of
640 quad-precision registers.
641
642 If these directives are used to create typed aliases, those aliases can
643 be used in Neon instructions instead of writing types after the mnemonic
644 or after each operand. For example:
645
646 @smallexample
647 x .dn d2.f32
648 y .dn d3.f32
649 z .dn d4.f32[1]
650 vmul x,y,z
651 @end smallexample
652
653 This is equivalent to writing the following:
654
655 @smallexample
656 vmul.f32 d2,d3,d4[1]
657 @end smallexample
658
659 Aliases created using @code{dn} or @code{qn} can be destroyed using
660 @code{unreq}.
661
662 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
663
664 @cindex @code{.eabi_attribute} directive, ARM
665 @item .eabi_attribute @var{tag}, @var{value}
666 Set the EABI object attribute @var{tag} to @var{value}.
667
668 The @var{tag} is either an attribute number, or one of the following:
669 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
670 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
671 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
672 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
673 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
674 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
675 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
676 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
677 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
678 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
679 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
680 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
681 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
682 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
683 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
684 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
685 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
686 @code{Tag_conformance}, @code{Tag_T2EE_use},
687 @code{Tag_Virtualization_use}
688
689 The @var{value} is either a @code{number}, @code{"string"}, or
690 @code{number, "string"} depending on the tag.
691
692 Note - the following legacy values are also accepted by @var{tag}:
693 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
694 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
695
696 @cindex @code{.even} directive, ARM
697 @item .even
698 This directive aligns to an even-numbered address.
699
700 @cindex @code{.extend} directive, ARM
701 @cindex @code{.ldouble} directive, ARM
702 @item .extend @var{expression} [, @var{expression}]*
703 @itemx .ldouble @var{expression} [, @var{expression}]*
704 These directives write 12byte long double floating-point values to the
705 output section. These are not compatible with current ARM processors
706 or ABIs.
707
708 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
709
710 @anchor{arm_fnend}
711 @cindex @code{.fnend} directive, ARM
712 @item .fnend
713 Marks the end of a function with an unwind table entry. The unwind index
714 table entry is created when this directive is processed.
715
716 If no personality routine has been specified then standard personality
717 routine 0 or 1 will be used, depending on the number of unwind opcodes
718 required.
719
720 @anchor{arm_fnstart}
721 @cindex @code{.fnstart} directive, ARM
722 @item .fnstart
723 Marks the start of a function with an unwind table entry.
724
725 @cindex @code{.force_thumb} directive, ARM
726 @item .force_thumb
727 This directive forces the selection of Thumb instructions, even if the
728 target processor does not support those instructions
729
730 @cindex @code{.fpu} directive, ARM
731 @item .fpu @var{name}
732 Select the floating-point unit to assemble for. Valid values for @var{name}
733 are the same as for the @option{-mfpu} commandline option.
734
735 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
736 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
737
738 @cindex @code{.handlerdata} directive, ARM
739 @item .handlerdata
740 Marks the end of the current function, and the start of the exception table
741 entry for that function. Anything between this directive and the
742 @code{.fnend} directive will be added to the exception table entry.
743
744 Must be preceded by a @code{.personality} or @code{.personalityindex}
745 directive.
746
747 @c IIIIIIIIIIIIIIIIIIIIIIIIII
748
749 @cindex @code{.inst} directive, ARM
750 @item .inst @var{opcode} [ , @dots{} ]
751 @itemx .inst.n @var{opcode} [ , @dots{} ]
752 @itemx .inst.w @var{opcode} [ , @dots{} ]
753 Generates the instruction corresponding to the numerical value @var{opcode}.
754 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
755 specified explicitly, overriding the normal encoding rules.
756
757 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
758 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
759 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
760
761 @item .ldouble @var{expression} [, @var{expression}]*
762 See @code{.extend}.
763
764 @cindex @code{.ltorg} directive, ARM
765 @item .ltorg
766 This directive causes the current contents of the literal pool to be
767 dumped into the current section (which is assumed to be the .text
768 section) at the current location (aligned to a word boundary).
769 @code{GAS} maintains a separate literal pool for each section and each
770 sub-section. The @code{.ltorg} directive will only affect the literal
771 pool of the current section and sub-section. At the end of assembly
772 all remaining, un-empty literal pools will automatically be dumped.
773
774 Note - older versions of @code{GAS} would dump the current literal
775 pool any time a section change occurred. This is no longer done, since
776 it prevents accurate control of the placement of literal pools.
777
778 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
779
780 @cindex @code{.movsp} directive, ARM
781 @item .movsp @var{reg} [, #@var{offset}]
782 Tell the unwinder that @var{reg} contains an offset from the current
783 stack pointer. If @var{offset} is not specified then it is assumed to be
784 zero.
785
786 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
787 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
788
789 @cindex @code{.object_arch} directive, ARM
790 @item .object_arch @var{name}
791 Override the architecture recorded in the EABI object attribute section.
792 Valid values for @var{name} are the same as for the @code{.arch} directive.
793 Typically this is useful when code uses runtime detection of CPU features.
794
795 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
796
797 @cindex @code{.packed} directive, ARM
798 @item .packed @var{expression} [, @var{expression}]*
799 This directive writes 12-byte packed floating-point values to the
800 output section. These are not compatible with current ARM processors
801 or ABIs.
802
803 @anchor{arm_pad}
804 @cindex @code{.pad} directive, ARM
805 @item .pad #@var{count}
806 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
807 A positive value indicates the function prologue allocated stack space by
808 decrementing the stack pointer.
809
810 @cindex @code{.personality} directive, ARM
811 @item .personality @var{name}
812 Sets the personality routine for the current function to @var{name}.
813
814 @cindex @code{.personalityindex} directive, ARM
815 @item .personalityindex @var{index}
816 Sets the personality routine for the current function to the EABI standard
817 routine number @var{index}
818
819 @cindex @code{.pool} directive, ARM
820 @item .pool
821 This is a synonym for .ltorg.
822
823 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
824 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
825
826 @cindex @code{.req} directive, ARM
827 @item @var{name} .req @var{register name}
828 This creates an alias for @var{register name} called @var{name}. For
829 example:
830
831 @smallexample
832 foo .req r0
833 @end smallexample
834
835 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
836
837 @anchor{arm_save}
838 @cindex @code{.save} directive, ARM
839 @item .save @var{reglist}
840 Generate unwinder annotations to restore the registers in @var{reglist}.
841 The format of @var{reglist} is the same as the corresponding store-multiple
842 instruction.
843
844 @smallexample
845 @exdent @emph{core registers}
846 .save @{r4, r5, r6, lr@}
847 stmfd sp!, @{r4, r5, r6, lr@}
848 @exdent @emph{FPA registers}
849 .save f4, 2
850 sfmfd f4, 2, [sp]!
851 @exdent @emph{VFP registers}
852 .save @{d8, d9, d10@}
853 fstmdx sp!, @{d8, d9, d10@}
854 @exdent @emph{iWMMXt registers}
855 .save @{wr10, wr11@}
856 wstrd wr11, [sp, #-8]!
857 wstrd wr10, [sp, #-8]!
858 or
859 .save wr11
860 wstrd wr11, [sp, #-8]!
861 .save wr10
862 wstrd wr10, [sp, #-8]!
863 @end smallexample
864
865 @anchor{arm_setfp}
866 @cindex @code{.setfp} directive, ARM
867 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
868 Make all unwinder annotations relative to a frame pointer. Without this
869 the unwinder will use offsets from the stack pointer.
870
871 The syntax of this directive is the same as the @code{add} or @code{mov}
872 instruction used to set the frame pointer. @var{spreg} must be either
873 @code{sp} or mentioned in a previous @code{.movsp} directive.
874
875 @smallexample
876 .movsp ip
877 mov ip, sp
878 @dots{}
879 .setfp fp, ip, #4
880 add fp, ip, #4
881 @end smallexample
882
883 @cindex @code{.secrel32} directive, ARM
884 @item .secrel32 @var{expression} [, @var{expression}]*
885 This directive emits relocations that evaluate to the section-relative
886 offset of each expression's symbol. This directive is only supported
887 for PE targets.
888
889 @cindex @code{.syntax} directive, ARM
890 @item .syntax [@code{unified} | @code{divided}]
891 This directive sets the Instruction Set Syntax as described in the
892 @ref{ARM-Instruction-Set} section.
893
894 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
895
896 @cindex @code{.thumb} directive, ARM
897 @item .thumb
898 This performs the same action as @var{.code 16}.
899
900 @cindex @code{.thumb_func} directive, ARM
901 @item .thumb_func
902 This directive specifies that the following symbol is the name of a
903 Thumb encoded function. This information is necessary in order to allow
904 the assembler and linker to generate correct code for interworking
905 between Arm and Thumb instructions and should be used even if
906 interworking is not going to be performed. The presence of this
907 directive also implies @code{.thumb}
908
909 This directive is not neccessary when generating EABI objects. On these
910 targets the encoding is implicit when generating Thumb code.
911
912 @cindex @code{.thumb_set} directive, ARM
913 @item .thumb_set
914 This performs the equivalent of a @code{.set} directive in that it
915 creates a symbol which is an alias for another symbol (possibly not yet
916 defined). This directive also has the added property in that it marks
917 the aliased symbol as being a thumb function entry point, in the same
918 way that the @code{.thumb_func} directive does.
919
920 @cindex @code{.tlsdescseq} directive, ARM
921 @item .tlsdescseq @var{tls-variable}
922 This directive is used to annotate parts of an inlined TLS descriptor
923 trampoline. Normally the trampoline is provided by the linker, and
924 this directive is not needed.
925
926 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
927
928 @cindex @code{.unreq} directive, ARM
929 @item .unreq @var{alias-name}
930 This undefines a register alias which was previously defined using the
931 @code{req}, @code{dn} or @code{qn} directives. For example:
932
933 @smallexample
934 foo .req r0
935 .unreq foo
936 @end smallexample
937
938 An error occurs if the name is undefined. Note - this pseudo op can
939 be used to delete builtin in register name aliases (eg 'r0'). This
940 should only be done if it is really necessary.
941
942 @cindex @code{.unwind_raw} directive, ARM
943 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
944 Insert one of more arbitary unwind opcode bytes, which are known to adjust
945 the stack pointer by @var{offset} bytes.
946
947 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
948 @code{.save @{r0@}}
949
950 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
951
952 @cindex @code{.vsave} directive, ARM
953 @item .vsave @var{vfp-reglist}
954 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
955 using FLDMD. Also works for VFPv3 registers
956 that are to be restored using VLDM.
957 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
958 instruction.
959
960 @smallexample
961 @exdent @emph{VFP registers}
962 .vsave @{d8, d9, d10@}
963 fstmdd sp!, @{d8, d9, d10@}
964 @exdent @emph{VFPv3 registers}
965 .vsave @{d15, d16, d17@}
966 vstm sp!, @{d15, d16, d17@}
967 @end smallexample
968
969 Since FLDMX and FSTMX are now deprecated, this directive should be
970 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
971
972 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
973 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
974 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
975 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
976
977 @end table
978
979 @node ARM Opcodes
980 @section Opcodes
981
982 @cindex ARM opcodes
983 @cindex opcodes for ARM
984 @code{@value{AS}} implements all the standard ARM opcodes. It also
985 implements several pseudo opcodes, including several synthetic load
986 instructions.
987
988 @table @code
989
990 @cindex @code{NOP} pseudo op, ARM
991 @item NOP
992 @smallexample
993 nop
994 @end smallexample
995
996 This pseudo op will always evaluate to a legal ARM instruction that does
997 nothing. Currently it will evaluate to MOV r0, r0.
998
999 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1000 @item LDR
1001 @smallexample
1002 ldr <register> , = <expression>
1003 @end smallexample
1004
1005 If expression evaluates to a numeric constant then a MOV or MVN
1006 instruction will be used in place of the LDR instruction, if the
1007 constant can be generated by either of these instructions. Otherwise
1008 the constant will be placed into the nearest literal pool (if it not
1009 already there) and a PC relative LDR instruction will be generated.
1010
1011 @cindex @code{ADR reg,<label>} pseudo op, ARM
1012 @item ADR
1013 @smallexample
1014 adr <register> <label>
1015 @end smallexample
1016
1017 This instruction will load the address of @var{label} into the indicated
1018 register. The instruction will evaluate to a PC relative ADD or SUB
1019 instruction depending upon where the label is located. If the label is
1020 out of range, or if it is not defined in the same file (and section) as
1021 the ADR instruction, then an error will be generated. This instruction
1022 will not make use of the literal pool.
1023
1024 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1025 @item ADRL
1026 @smallexample
1027 adrl <register> <label>
1028 @end smallexample
1029
1030 This instruction will load the address of @var{label} into the indicated
1031 register. The instruction will evaluate to one or two PC relative ADD
1032 or SUB instructions depending upon where the label is located. If a
1033 second instruction is not needed a NOP instruction will be generated in
1034 its place, so that this instruction is always 8 bytes long.
1035
1036 If the label is out of range, or if it is not defined in the same file
1037 (and section) as the ADRL instruction, then an error will be generated.
1038 This instruction will not make use of the literal pool.
1039
1040 @end table
1041
1042 For information on the ARM or Thumb instruction sets, see @cite{ARM
1043 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1044 Ltd.
1045
1046 @node ARM Mapping Symbols
1047 @section Mapping Symbols
1048
1049 The ARM ELF specification requires that special symbols be inserted
1050 into object files to mark certain features:
1051
1052 @table @code
1053
1054 @cindex @code{$a}
1055 @item $a
1056 At the start of a region of code containing ARM instructions.
1057
1058 @cindex @code{$t}
1059 @item $t
1060 At the start of a region of code containing THUMB instructions.
1061
1062 @cindex @code{$d}
1063 @item $d
1064 At the start of a region of data.
1065
1066 @end table
1067
1068 The assembler will automatically insert these symbols for you - there
1069 is no need to code them yourself. Support for tagging symbols ($b,
1070 $f, $p and $m) which is also mentioned in the current ARM ELF
1071 specification is not implemented. This is because they have been
1072 dropped from the new EABI and so tools cannot rely upon their
1073 presence.
1074
1075 @node ARM Unwinding Tutorial
1076 @section Unwinding
1077
1078 The ABI for the ARM Architecture specifies a standard format for
1079 exception unwind information. This information is used when an
1080 exception is thrown to determine where control should be transferred.
1081 In particular, the unwind information is used to determine which
1082 function called the function that threw the exception, and which
1083 function called that one, and so forth. This information is also used
1084 to restore the values of callee-saved registers in the function
1085 catching the exception.
1086
1087 If you are writing functions in assembly code, and those functions
1088 call other functions that throw exceptions, you must use assembly
1089 pseudo ops to ensure that appropriate exception unwind information is
1090 generated. Otherwise, if one of the functions called by your assembly
1091 code throws an exception, the run-time library will be unable to
1092 unwind the stack through your assembly code and your program will not
1093 behave correctly.
1094
1095 To illustrate the use of these pseudo ops, we will examine the code
1096 that G++ generates for the following C++ input:
1097
1098 @verbatim
1099 void callee (int *);
1100
1101 int
1102 caller ()
1103 {
1104 int i;
1105 callee (&i);
1106 return i;
1107 }
1108 @end verbatim
1109
1110 This example does not show how to throw or catch an exception from
1111 assembly code. That is a much more complex operation and should
1112 always be done in a high-level language, such as C++, that directly
1113 supports exceptions.
1114
1115 The code generated by one particular version of G++ when compiling the
1116 example above is:
1117
1118 @verbatim
1119 _Z6callerv:
1120 .fnstart
1121 .LFB2:
1122 @ Function supports interworking.
1123 @ args = 0, pretend = 0, frame = 8
1124 @ frame_needed = 1, uses_anonymous_args = 0
1125 stmfd sp!, {fp, lr}
1126 .save {fp, lr}
1127 .LCFI0:
1128 .setfp fp, sp, #4
1129 add fp, sp, #4
1130 .LCFI1:
1131 .pad #8
1132 sub sp, sp, #8
1133 .LCFI2:
1134 sub r3, fp, #8
1135 mov r0, r3
1136 bl _Z6calleePi
1137 ldr r3, [fp, #-8]
1138 mov r0, r3
1139 sub sp, fp, #4
1140 ldmfd sp!, {fp, lr}
1141 bx lr
1142 .LFE2:
1143 .fnend
1144 @end verbatim
1145
1146 Of course, the sequence of instructions varies based on the options
1147 you pass to GCC and on the version of GCC in use. The exact
1148 instructions are not important since we are focusing on the pseudo ops
1149 that are used to generate unwind information.
1150
1151 An important assumption made by the unwinder is that the stack frame
1152 does not change during the body of the function. In particular, since
1153 we assume that the assembly code does not itself throw an exception,
1154 the only point where an exception can be thrown is from a call, such
1155 as the @code{bl} instruction above. At each call site, the same saved
1156 registers (including @code{lr}, which indicates the return address)
1157 must be located in the same locations relative to the frame pointer.
1158
1159 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1160 op appears immediately before the first instruction of the function
1161 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1162 op appears immediately after the last instruction of the function.
1163 These pseudo ops specify the range of the function.
1164
1165 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1166 @code{.pad}) matters; their exact locations are irrelevant. In the
1167 example above, the compiler emits the pseudo ops with particular
1168 instructions. That makes it easier to understand the code, but it is
1169 not required for correctness. It would work just as well to emit all
1170 of the pseudo ops other than @code{.fnend} in the same order, but
1171 immediately after @code{.fnstart}.
1172
1173 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1174 indicates registers that have been saved to the stack so that they can
1175 be restored before the function returns. The argument to the
1176 @code{.save} pseudo op is a list of registers to save. If a register
1177 is ``callee-saved'' (as specified by the ABI) and is modified by the
1178 function you are writing, then your code must save the value before it
1179 is modified and restore the original value before the function
1180 returns. If an exception is thrown, the run-time library restores the
1181 values of these registers from their locations on the stack before
1182 returning control to the exception handler. (Of course, if an
1183 exception is not thrown, the function that contains the @code{.save}
1184 pseudo op restores these registers in the function epilogue, as is
1185 done with the @code{ldmfd} instruction above.)
1186
1187 You do not have to save callee-saved registers at the very beginning
1188 of the function and you do not need to use the @code{.save} pseudo op
1189 immediately following the point at which the registers are saved.
1190 However, if you modify a callee-saved register, you must save it on
1191 the stack before modifying it and before calling any functions which
1192 might throw an exception. And, you must use the @code{.save} pseudo
1193 op to indicate that you have done so.
1194
1195 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1196 modification of the stack pointer that does not save any registers.
1197 The argument is the number of bytes (in decimal) that are subtracted
1198 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1199 subtracting from the stack pointer increases the size of the stack.)
1200
1201 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1202 indicates the register that contains the frame pointer. The first
1203 argument is the register that is set, which is typically @code{fp}.
1204 The second argument indicates the register from which the frame
1205 pointer takes its value. The third argument, if present, is the value
1206 (in decimal) added to the register specified by the second argument to
1207 compute the value of the frame pointer. You should not modify the
1208 frame pointer in the body of the function.
1209
1210 If you do not use a frame pointer, then you should not use the
1211 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1212 should avoid modifying the stack pointer outside of the function
1213 prologue. Otherwise, the run-time library will be unable to find
1214 saved registers when it is unwinding the stack.
1215
1216 The pseudo ops described above are sufficient for writing assembly
1217 code that calls functions which may throw exceptions. If you need to
1218 know more about the object-file format used to represent unwind
1219 information, you may consult the @cite{Exception Handling ABI for the
1220 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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