1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
95 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
96 @code{i80200} (Intel XScale processor)
97 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
100 The special name @code{all} may be used to allow the
101 assembler to accept instructions valid for any ARM processor.
103 In addition to the basic instruction set, the assembler can be told to
104 accept various extension mnemonics that extend the processor using the
105 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
106 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
107 are currently supported:
113 @cindex @code{-march=} command line option, ARM
114 @item -march=@var{architecture}[+@var{extension}@dots{}]
115 This option specifies the target architecture. The assembler will issue
116 an error message if an attempt is made to assemble an instruction which
117 will not execute on the target architecture. The following architecture
118 names are recognized:
138 If both @code{-mcpu} and
139 @code{-march} are specified, the assembler will use
140 the setting for @code{-mcpu}.
142 The architecture option can be extended with the same instruction set
143 extension options as the @code{-mcpu} option.
145 @cindex @code{-mfpu=} command line option, ARM
146 @item -mfpu=@var{floating-point-format}
148 This option specifies the floating point format to assemble for. The
149 assembler will issue an error message if an attempt is made to assemble
150 an instruction which will not execute on the target floating point unit.
151 The following format options are recognized:
172 In addition to determining which instructions are assembled, this option
173 also affects the way in which the @code{.double} assembler directive behaves
174 when assembling little-endian code.
176 The default is dependent on the processor selected. For Architecture 5 or
177 later, the default is to assembler for VFP instructions; for earlier
178 architectures the default is to assemble for FPA instructions.
180 @cindex @code{-mthumb} command line option, ARM
182 This option specifies that the assembler should start assembling Thumb
183 instructions; that is, it should behave as though the file starts with a
184 @code{.code 16} directive.
186 @cindex @code{-mthumb-interwork} command line option, ARM
187 @item -mthumb-interwork
188 This option specifies that the output generated by the assembler should
189 be marked as supporting interworking.
191 @cindex @code{-mapcs} command line option, ARM
192 @item -mapcs @code{[26|32]}
193 This option specifies that the output generated by the assembler should
194 be marked as supporting the indicated version of the Arm Procedure.
197 @cindex @code{-matpcs} command line option, ARM
199 This option specifies that the output generated by the assembler should
200 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
201 enabled this option will cause the assembler to create an empty
202 debugging section in the object file called .arm.atpcs. Debuggers can
203 use this to determine the ABI being used by.
205 @cindex @code{-mapcs-float} command line option, ARM
207 This indicates the floating point variant of the APCS should be
208 used. In this variant floating point arguments are passed in FP
209 registers rather than integer registers.
211 @cindex @code{-mapcs-reentrant} command line option, ARM
212 @item -mapcs-reentrant
213 This indicates that the reentrant variant of the APCS should be used.
214 This variant supports position independent code.
216 @cindex @code{-EB} command line option, ARM
218 This option specifies that the output generated by the assembler should
219 be marked as being encoded for a big-endian processor.
221 @cindex @code{-EL} command line option, ARM
223 This option specifies that the output generated by the assembler should
224 be marked as being encoded for a little-endian processor.
226 @cindex @code{-k} command line option, ARM
227 @cindex PIC code generation for ARM
229 This option specifies that the output of the assembler should be marked
230 as position-independent code (PIC).
232 @cindex @code{-moabi} command line option, ARM
234 This indicates that the code should be assembled using the old ARM ELF
235 conventions, based on a beta release release of the ARM-ELF
236 specifications, rather than the default conventions which are based on
237 the final release of the ARM-ELF specifications.
245 * ARM-Chars:: Special Characters
246 * ARM-Regs:: Register Names
250 @subsection Special Characters
252 @cindex line comment character, ARM
253 @cindex ARM line comment character
254 The presence of a @samp{@@} on a line indicates the start of a comment
255 that extends to the end of the current line. If a @samp{#} appears as
256 the first character of a line, the whole line is treated as a comment.
258 @cindex line separator, ARM
259 @cindex statement separator, ARM
260 @cindex ARM line separator
261 The @samp{;} character can be used instead of a newline to separate
264 @cindex immediate character, ARM
265 @cindex ARM immediate character
266 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
268 @cindex identifiers, ARM
269 @cindex ARM identifiers
270 *TODO* Explain about /data modifier on symbols.
273 @subsection Register Names
275 @cindex ARM register names
276 @cindex register names, ARM
277 *TODO* Explain about ARM register naming, and the predefined names.
279 @node ARM Floating Point
280 @section Floating Point
282 @cindex floating point, ARM (@sc{ieee})
283 @cindex ARM floating point (@sc{ieee})
284 The ARM family uses @sc{ieee} floating-point numbers.
289 @section ARM Machine Directives
291 @cindex machine directives, ARM
292 @cindex ARM machine directives
295 @cindex @code{align} directive, ARM
296 @item .align @var{expression} [, @var{expression}]
297 This is the generic @var{.align} directive. For the ARM however if the
298 first argument is zero (ie no alignment is needed) the assembler will
299 behave as if the argument had been 2 (ie pad to the next four byte
300 boundary). This is for compatibility with ARM's own assembler.
302 @cindex @code{req} directive, ARM
303 @item @var{name} .req @var{register name}
304 This creates an alias for @var{register name} called @var{name}. For
311 @cindex @code{unreq} directive, ARM
312 @item .unreq @var{alias-name}
313 This undefines a register alias which was previously defined using the
314 @code{req} directive. For example:
321 An error occurs if the name is undefined. Note - this pseudo op can
322 be used to delete builtin in register name aliases (eg 'r0'). This
323 should only be done if it is really necessary.
325 @cindex @code{code} directive, ARM
326 @item .code @code{[16|32]}
327 This directive selects the instruction set being generated. The value 16
328 selects Thumb, with the value 32 selecting ARM.
330 @cindex @code{thumb} directive, ARM
332 This performs the same action as @var{.code 16}.
334 @cindex @code{arm} directive, ARM
336 This performs the same action as @var{.code 32}.
338 @cindex @code{force_thumb} directive, ARM
340 This directive forces the selection of Thumb instructions, even if the
341 target processor does not support those instructions
343 @cindex @code{thumb_func} directive, ARM
345 This directive specifies that the following symbol is the name of a
346 Thumb encoded function. This information is necessary in order to allow
347 the assembler and linker to generate correct code for interworking
348 between Arm and Thumb instructions and should be used even if
349 interworking is not going to be performed. The presence of this
350 directive also implies @code{.thumb}
352 @cindex @code{thumb_set} directive, ARM
354 This performs the equivalent of a @code{.set} directive in that it
355 creates a symbol which is an alias for another symbol (possibly not yet
356 defined). This directive also has the added property in that it marks
357 the aliased symbol as being a thumb function entry point, in the same
358 way that the @code{.thumb_func} directive does.
360 @cindex @code{.ltorg} directive, ARM
362 This directive causes the current contents of the literal pool to be
363 dumped into the current section (which is assumed to be the .text
364 section) at the current location (aligned to a word boundary).
365 @code{GAS} maintains a separate literal pool for each section and each
366 sub-section. The @code{.ltorg} directive will only affect the literal
367 pool of the current section and sub-section. At the end of assembly
368 all remaining, un-empty literal pools will automatically be dumped.
370 Note - older versions of @code{GAS} would dump the current literal
371 pool any time a section change occurred. This is no longer done, since
372 it prevents accurate control of the placement of literal pools.
374 @cindex @code{.pool} directive, ARM
376 This is a synonym for .ltorg.
384 @cindex opcodes for ARM
385 @code{@value{AS}} implements all the standard ARM opcodes. It also
386 implements several pseudo opcodes, including several synthetic load
391 @cindex @code{NOP} pseudo op, ARM
397 This pseudo op will always evaluate to a legal ARM instruction that does
398 nothing. Currently it will evaluate to MOV r0, r0.
400 @cindex @code{LDR reg,=<label>} pseudo op, ARM
403 ldr <register> , = <expression>
406 If expression evaluates to a numeric constant then a MOV or MVN
407 instruction will be used in place of the LDR instruction, if the
408 constant can be generated by either of these instructions. Otherwise
409 the constant will be placed into the nearest literal pool (if it not
410 already there) and a PC relative LDR instruction will be generated.
412 @cindex @code{ADR reg,<label>} pseudo op, ARM
415 adr <register> <label>
418 This instruction will load the address of @var{label} into the indicated
419 register. The instruction will evaluate to a PC relative ADD or SUB
420 instruction depending upon where the label is located. If the label is
421 out of range, or if it is not defined in the same file (and section) as
422 the ADR instruction, then an error will be generated. This instruction
423 will not make use of the literal pool.
425 @cindex @code{ADRL reg,<label>} pseudo op, ARM
428 adrl <register> <label>
431 This instruction will load the address of @var{label} into the indicated
432 register. The instruction will evaluate to one or two PC relative ADD
433 or SUB instructions depending upon where the label is located. If a
434 second instruction is not needed a NOP instruction will be generated in
435 its place, so that this instruction is always 8 bytes long.
437 If the label is out of range, or if it is not defined in the same file
438 (and section) as the ADRL instruction, then an error will be generated.
439 This instruction will not make use of the literal pool.
443 For information on the ARM or Thumb instruction sets, see @cite{ARM
444 Software Development Toolkit Reference Manual}, Advanced RISC Machines
447 @node ARM Mapping Symbols
448 @section Mapping Symbols
450 The ARM ELF specification requires that special symbols be inserted
451 into object files to mark certain features:
457 At the start of a region of code containing ARM instructions.
461 At the start of a region of code containing THUMB instructions.
465 At the start of a region of data.
469 The assembler will automatically insert these symbols for you - there
470 is no need to code them yourself. Support for tagging symbols ($b,
471 $f, $p and $m) which is also mentioned in the current ARM ELF
472 specification is not implemented. This is because they have been
473 dropped from the new EABI and so tools cannot rely upon their