1 @c Copyright (C) 1996-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
142 @code{cortex-m0plus},
145 @code{marvell-whitney},
148 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
149 @code{i80200} (Intel XScale processor)
150 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
153 The special name @code{all} may be used to allow the
154 assembler to accept instructions valid for any ARM processor.
156 In addition to the basic instruction set, the assembler can be told to
157 accept various extension mnemonics that extend the processor using the
158 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
159 is equivalent to specifying @code{-mcpu=ep9312}.
161 Multiple extensions may be specified, separated by a @code{+}. The
162 extensions should be specified in ascending alphabetical order.
164 Some extensions may be restricted to particular architectures; this is
165 documented in the list of extensions below.
167 Extension mnemonics may also be removed from those the assembler accepts.
168 This is done be prepending @code{no} to the option that adds the extension.
169 Extensions that are removed should be listed after all extensions which have
170 been added, again in ascending alphabetical order. For example,
171 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
174 The following extensions are currently supported:
176 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
177 @code{fp} (Floating Point Extensions for v8-A architecture),
178 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
183 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
185 @code{os} (Operating System for v6M architecture),
186 @code{sec} (Security Extensions for v6K and v7-A architectures),
187 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
188 @code{virt} (Virtualization Extensions for v7-A architecture, implies
190 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
191 @code{ras} (Reliability, Availability and Serviceability extensions
192 for v8-A architecture),
193 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
198 @cindex @code{-march=} command line option, ARM
199 @item -march=@var{architecture}[+@var{extension}@dots{}]
200 This option specifies the target architecture. The assembler will issue
201 an error message if an attempt is made to assemble an instruction which
202 will not execute on the target architecture. The following architecture
203 names are recognized:
241 If both @code{-mcpu} and
242 @code{-march} are specified, the assembler will use
243 the setting for @code{-mcpu}.
245 The architecture option can be extended with the same instruction set
246 extension options as the @code{-mcpu} option.
248 @cindex @code{-mfpu=} command line option, ARM
249 @item -mfpu=@var{floating-point-format}
251 This option specifies the floating point format to assemble for. The
252 assembler will issue an error message if an attempt is made to assemble
253 an instruction which will not execute on the target floating point unit.
254 The following format options are recognized:
274 @code{vfpv3-d16-fp16},
291 @code{neon-fp-armv8},
292 @code{crypto-neon-fp-armv8},
293 @code{neon-fp-armv8.1}
295 @code{crypto-neon-fp-armv8.1}.
297 In addition to determining which instructions are assembled, this option
298 also affects the way in which the @code{.double} assembler directive behaves
299 when assembling little-endian code.
301 The default is dependent on the processor selected. For Architecture 5 or
302 later, the default is to assemble for VFP instructions; for earlier
303 architectures the default is to assemble for FPA instructions.
305 @cindex @code{-mthumb} command line option, ARM
307 This option specifies that the assembler should start assembling Thumb
308 instructions; that is, it should behave as though the file starts with a
309 @code{.code 16} directive.
311 @cindex @code{-mthumb-interwork} command line option, ARM
312 @item -mthumb-interwork
313 This option specifies that the output generated by the assembler should
314 be marked as supporting interworking.
316 @cindex @code{-mimplicit-it} command line option, ARM
317 @item -mimplicit-it=never
318 @itemx -mimplicit-it=always
319 @itemx -mimplicit-it=arm
320 @itemx -mimplicit-it=thumb
321 The @code{-mimplicit-it} option controls the behavior of the assembler when
322 conditional instructions are not enclosed in IT blocks.
323 There are four possible behaviors.
324 If @code{never} is specified, such constructs cause a warning in ARM
325 code and an error in Thumb-2 code.
326 If @code{always} is specified, such constructs are accepted in both
327 ARM and Thumb-2 code, where the IT instruction is added implicitly.
328 If @code{arm} is specified, such constructs are accepted in ARM code
329 and cause an error in Thumb-2 code.
330 If @code{thumb} is specified, such constructs cause a warning in ARM
331 code and are accepted in Thumb-2 code. If you omit this option, the
332 behavior is equivalent to @code{-mimplicit-it=arm}.
334 @cindex @code{-mapcs-26} command line option, ARM
335 @cindex @code{-mapcs-32} command line option, ARM
338 These options specify that the output generated by the assembler should
339 be marked as supporting the indicated version of the Arm Procedure.
342 @cindex @code{-matpcs} command line option, ARM
344 This option specifies that the output generated by the assembler should
345 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
346 enabled this option will cause the assembler to create an empty
347 debugging section in the object file called .arm.atpcs. Debuggers can
348 use this to determine the ABI being used by.
350 @cindex @code{-mapcs-float} command line option, ARM
352 This indicates the floating point variant of the APCS should be
353 used. In this variant floating point arguments are passed in FP
354 registers rather than integer registers.
356 @cindex @code{-mapcs-reentrant} command line option, ARM
357 @item -mapcs-reentrant
358 This indicates that the reentrant variant of the APCS should be used.
359 This variant supports position independent code.
361 @cindex @code{-mfloat-abi=} command line option, ARM
362 @item -mfloat-abi=@var{abi}
363 This option specifies that the output generated by the assembler should be
364 marked as using specified floating point ABI.
365 The following values are recognized:
371 @cindex @code{-eabi=} command line option, ARM
372 @item -meabi=@var{ver}
373 This option specifies which EABI version the produced object files should
375 The following values are recognized:
381 @cindex @code{-EB} command line option, ARM
383 This option specifies that the output generated by the assembler should
384 be marked as being encoded for a big-endian processor.
386 Note: If a program is being built for a system with big-endian data
387 and little-endian instructions then it should be assembled with the
388 @option{-EB} option, (all of it, code and data) and then linked with
389 the @option{--be8} option. This will reverse the endianness of the
390 instructions back to little-endian, but leave the data as big-endian.
392 @cindex @code{-EL} command line option, ARM
394 This option specifies that the output generated by the assembler should
395 be marked as being encoded for a little-endian processor.
397 @cindex @code{-k} command line option, ARM
398 @cindex PIC code generation for ARM
400 This option specifies that the output of the assembler should be marked
401 as position-independent code (PIC).
403 @cindex @code{--fix-v4bx} command line option, ARM
405 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
406 the linker option of the same name.
408 @cindex @code{-mwarn-deprecated} command line option, ARM
409 @item -mwarn-deprecated
410 @itemx -mno-warn-deprecated
411 Enable or disable warnings about using deprecated options or
412 features. The default is to warn.
414 @cindex @code{-mccs} command line option, ARM
416 Turns on CodeComposer Studio assembly syntax compatibility mode.
418 @cindex @code{-mwarn-syms} command line option, ARM
420 @itemx -mno-warn-syms
421 Enable or disable warnings about symbols that match the names of ARM
422 instructions. The default is to warn.
430 * ARM-Instruction-Set:: Instruction Set
431 * ARM-Chars:: Special Characters
432 * ARM-Regs:: Register Names
433 * ARM-Relocations:: Relocations
434 * ARM-Neon-Alignment:: NEON Alignment Specifiers
437 @node ARM-Instruction-Set
438 @subsection Instruction Set Syntax
439 Two slightly different syntaxes are support for ARM and THUMB
440 instructions. The default, @code{divided}, uses the old style where
441 ARM and THUMB instructions had their own, separate syntaxes. The new,
442 @code{unified} syntax, which can be selected via the @code{.syntax}
443 directive, and has the following main features:
447 Immediate operands do not require a @code{#} prefix.
450 The @code{IT} instruction may appear, and if it does it is validated
451 against subsequent conditional affixes. In ARM mode it does not
452 generate machine code, in THUMB mode it does.
455 For ARM instructions the conditional affixes always appear at the end
456 of the instruction. For THUMB instructions conditional affixes can be
457 used, but only inside the scope of an @code{IT} instruction.
460 All of the instructions new to the V6T2 architecture (and later) are
461 available. (Only a few such instructions can be written in the
462 @code{divided} syntax).
465 The @code{.N} and @code{.W} suffixes are recognized and honored.
468 All instructions set the flags if and only if they have an @code{s}
473 @subsection Special Characters
475 @cindex line comment character, ARM
476 @cindex ARM line comment character
477 The presence of a @samp{@@} anywhere on a line indicates the start of
478 a comment that extends to the end of that line.
480 If a @samp{#} appears as the first character of a line then the whole
481 line is treated as a comment, but in this case the line could also be
482 a logical line number directive (@pxref{Comments}) or a preprocessor
483 control command (@pxref{Preprocessing}).
485 @cindex line separator, ARM
486 @cindex statement separator, ARM
487 @cindex ARM line separator
488 The @samp{;} character can be used instead of a newline to separate
491 @cindex immediate character, ARM
492 @cindex ARM immediate character
493 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
495 @cindex identifiers, ARM
496 @cindex ARM identifiers
497 *TODO* Explain about /data modifier on symbols.
500 @subsection Register Names
502 @cindex ARM register names
503 @cindex register names, ARM
504 *TODO* Explain about ARM register naming, and the predefined names.
506 @node ARM-Relocations
507 @subsection ARM relocation generation
509 @cindex data relocations, ARM
510 @cindex ARM data relocations
511 Specific data relocations can be generated by putting the relocation name
512 in parentheses after the symbol name. For example:
518 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
520 The following relocations are supported:
536 For compatibility with older toolchains the assembler also accepts
537 @code{(PLT)} after branch targets. On legacy targets this will
538 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
539 targets it will encode either the @samp{R_ARM_CALL} or
540 @samp{R_ARM_JUMP24} relocation, as appropriate.
542 @cindex MOVW and MOVT relocations, ARM
543 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
544 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
545 respectively. For example to load the 32-bit address of foo into r0:
548 MOVW r0, #:lower16:foo
549 MOVT r0, #:upper16:foo
552 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
553 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
554 generated by prefixing the value with @samp{#:lower0_7:#},
555 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
556 respectively. For example to load the 32-bit address of foo into r0:
559 MOVS r0, #:upper8_15:#foo
561 ADDS r0, #:upper0_7:#foo
563 ADDS r0, #:lower8_15:#foo
565 ADDS r0, #:lower0_7:#foo
568 @node ARM-Neon-Alignment
569 @subsection NEON Alignment Specifiers
571 @cindex alignment for NEON instructions
572 Some NEON load/store instructions allow an optional address
574 The ARM documentation specifies that this is indicated by
575 @samp{@@ @var{align}}. However GAS already interprets
576 the @samp{@@} character as a "line comment" start,
577 so @samp{: @var{align}} is used instead. For example:
580 vld1.8 @{q0@}, [r0, :128]
583 @node ARM Floating Point
584 @section Floating Point
586 @cindex floating point, ARM (@sc{ieee})
587 @cindex ARM floating point (@sc{ieee})
588 The ARM family uses @sc{ieee} floating-point numbers.
591 @section ARM Machine Directives
593 @cindex machine directives, ARM
594 @cindex ARM machine directives
597 @c AAAAAAAAAAAAAAAAAAAAAAAAA
600 @cindex @code{.2byte} directive, ARM
601 @cindex @code{.4byte} directive, ARM
602 @cindex @code{.8byte} directive, ARM
603 @item .2byte @var{expression} [, @var{expression}]*
604 @itemx .4byte @var{expression} [, @var{expression}]*
605 @itemx .8byte @var{expression} [, @var{expression}]*
606 These directives write 2, 4 or 8 byte values to the output section.
609 @cindex @code{.align} directive, ARM
610 @item .align @var{expression} [, @var{expression}]
611 This is the generic @var{.align} directive. For the ARM however if the
612 first argument is zero (ie no alignment is needed) the assembler will
613 behave as if the argument had been 2 (ie pad to the next four byte
614 boundary). This is for compatibility with ARM's own assembler.
616 @cindex @code{.arch} directive, ARM
617 @item .arch @var{name}
618 Select the target architecture. Valid values for @var{name} are the same as
619 for the @option{-march} commandline option.
621 Specifying @code{.arch} clears any previously selected architecture
624 @cindex @code{.arch_extension} directive, ARM
625 @item .arch_extension @var{name}
626 Add or remove an architecture extension to the target architecture. Valid
627 values for @var{name} are the same as those accepted as architectural
628 extensions by the @option{-mcpu} commandline option.
630 @code{.arch_extension} may be used multiple times to add or remove extensions
631 incrementally to the architecture being compiled for.
633 @cindex @code{.arm} directive, ARM
635 This performs the same action as @var{.code 32}.
637 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
639 @cindex @code{.bss} directive, ARM
641 This directive switches to the @code{.bss} section.
643 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
645 @cindex @code{.cantunwind} directive, ARM
647 Prevents unwinding through the current function. No personality routine
648 or exception table data is required or permitted.
650 @cindex @code{.code} directive, ARM
651 @item .code @code{[16|32]}
652 This directive selects the instruction set being generated. The value 16
653 selects Thumb, with the value 32 selecting ARM.
655 @cindex @code{.cpu} directive, ARM
656 @item .cpu @var{name}
657 Select the target processor. Valid values for @var{name} are the same as
658 for the @option{-mcpu} commandline option.
660 Specifying @code{.cpu} clears any previously selected architecture
663 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
665 @cindex @code{.dn} and @code{.qn} directives, ARM
666 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
667 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
669 The @code{dn} and @code{qn} directives are used to create typed
670 and/or indexed register aliases for use in Advanced SIMD Extension
671 (Neon) instructions. The former should be used to create aliases
672 of double-precision registers, and the latter to create aliases of
673 quad-precision registers.
675 If these directives are used to create typed aliases, those aliases can
676 be used in Neon instructions instead of writing types after the mnemonic
677 or after each operand. For example:
686 This is equivalent to writing the following:
692 Aliases created using @code{dn} or @code{qn} can be destroyed using
695 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
697 @cindex @code{.eabi_attribute} directive, ARM
698 @item .eabi_attribute @var{tag}, @var{value}
699 Set the EABI object attribute @var{tag} to @var{value}.
701 The @var{tag} is either an attribute number, or one of the following:
702 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
703 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
704 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
705 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
706 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
707 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
708 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
709 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
710 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
711 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
712 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
713 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
714 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
715 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
716 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
717 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
718 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
719 @code{Tag_conformance}, @code{Tag_T2EE_use},
720 @code{Tag_Virtualization_use}
722 The @var{value} is either a @code{number}, @code{"string"}, or
723 @code{number, "string"} depending on the tag.
725 Note - the following legacy values are also accepted by @var{tag}:
726 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
727 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
729 @cindex @code{.even} directive, ARM
731 This directive aligns to an even-numbered address.
733 @cindex @code{.extend} directive, ARM
734 @cindex @code{.ldouble} directive, ARM
735 @item .extend @var{expression} [, @var{expression}]*
736 @itemx .ldouble @var{expression} [, @var{expression}]*
737 These directives write 12byte long double floating-point values to the
738 output section. These are not compatible with current ARM processors
741 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
744 @cindex @code{.fnend} directive, ARM
746 Marks the end of a function with an unwind table entry. The unwind index
747 table entry is created when this directive is processed.
749 If no personality routine has been specified then standard personality
750 routine 0 or 1 will be used, depending on the number of unwind opcodes
754 @cindex @code{.fnstart} directive, ARM
756 Marks the start of a function with an unwind table entry.
758 @cindex @code{.force_thumb} directive, ARM
760 This directive forces the selection of Thumb instructions, even if the
761 target processor does not support those instructions
763 @cindex @code{.fpu} directive, ARM
764 @item .fpu @var{name}
765 Select the floating-point unit to assemble for. Valid values for @var{name}
766 are the same as for the @option{-mfpu} commandline option.
768 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
769 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
771 @cindex @code{.handlerdata} directive, ARM
773 Marks the end of the current function, and the start of the exception table
774 entry for that function. Anything between this directive and the
775 @code{.fnend} directive will be added to the exception table entry.
777 Must be preceded by a @code{.personality} or @code{.personalityindex}
780 @c IIIIIIIIIIIIIIIIIIIIIIIIII
782 @cindex @code{.inst} directive, ARM
783 @item .inst @var{opcode} [ , @dots{} ]
784 @itemx .inst.n @var{opcode} [ , @dots{} ]
785 @itemx .inst.w @var{opcode} [ , @dots{} ]
786 Generates the instruction corresponding to the numerical value @var{opcode}.
787 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
788 specified explicitly, overriding the normal encoding rules.
790 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
791 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
792 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
794 @item .ldouble @var{expression} [, @var{expression}]*
797 @cindex @code{.ltorg} directive, ARM
799 This directive causes the current contents of the literal pool to be
800 dumped into the current section (which is assumed to be the .text
801 section) at the current location (aligned to a word boundary).
802 @code{GAS} maintains a separate literal pool for each section and each
803 sub-section. The @code{.ltorg} directive will only affect the literal
804 pool of the current section and sub-section. At the end of assembly
805 all remaining, un-empty literal pools will automatically be dumped.
807 Note - older versions of @code{GAS} would dump the current literal
808 pool any time a section change occurred. This is no longer done, since
809 it prevents accurate control of the placement of literal pools.
811 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
813 @cindex @code{.movsp} directive, ARM
814 @item .movsp @var{reg} [, #@var{offset}]
815 Tell the unwinder that @var{reg} contains an offset from the current
816 stack pointer. If @var{offset} is not specified then it is assumed to be
819 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
820 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
822 @cindex @code{.object_arch} directive, ARM
823 @item .object_arch @var{name}
824 Override the architecture recorded in the EABI object attribute section.
825 Valid values for @var{name} are the same as for the @code{.arch} directive.
826 Typically this is useful when code uses runtime detection of CPU features.
828 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
830 @cindex @code{.packed} directive, ARM
831 @item .packed @var{expression} [, @var{expression}]*
832 This directive writes 12-byte packed floating-point values to the
833 output section. These are not compatible with current ARM processors
837 @cindex @code{.pad} directive, ARM
838 @item .pad #@var{count}
839 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
840 A positive value indicates the function prologue allocated stack space by
841 decrementing the stack pointer.
843 @cindex @code{.personality} directive, ARM
844 @item .personality @var{name}
845 Sets the personality routine for the current function to @var{name}.
847 @cindex @code{.personalityindex} directive, ARM
848 @item .personalityindex @var{index}
849 Sets the personality routine for the current function to the EABI standard
850 routine number @var{index}
852 @cindex @code{.pool} directive, ARM
854 This is a synonym for .ltorg.
856 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
857 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
859 @cindex @code{.req} directive, ARM
860 @item @var{name} .req @var{register name}
861 This creates an alias for @var{register name} called @var{name}. For
868 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
871 @cindex @code{.save} directive, ARM
872 @item .save @var{reglist}
873 Generate unwinder annotations to restore the registers in @var{reglist}.
874 The format of @var{reglist} is the same as the corresponding store-multiple
878 @exdent @emph{core registers}
879 .save @{r4, r5, r6, lr@}
880 stmfd sp!, @{r4, r5, r6, lr@}
881 @exdent @emph{FPA registers}
884 @exdent @emph{VFP registers}
885 .save @{d8, d9, d10@}
886 fstmdx sp!, @{d8, d9, d10@}
887 @exdent @emph{iWMMXt registers}
889 wstrd wr11, [sp, #-8]!
890 wstrd wr10, [sp, #-8]!
893 wstrd wr11, [sp, #-8]!
895 wstrd wr10, [sp, #-8]!
899 @cindex @code{.setfp} directive, ARM
900 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
901 Make all unwinder annotations relative to a frame pointer. Without this
902 the unwinder will use offsets from the stack pointer.
904 The syntax of this directive is the same as the @code{add} or @code{mov}
905 instruction used to set the frame pointer. @var{spreg} must be either
906 @code{sp} or mentioned in a previous @code{.movsp} directive.
916 @cindex @code{.secrel32} directive, ARM
917 @item .secrel32 @var{expression} [, @var{expression}]*
918 This directive emits relocations that evaluate to the section-relative
919 offset of each expression's symbol. This directive is only supported
922 @cindex @code{.syntax} directive, ARM
923 @item .syntax [@code{unified} | @code{divided}]
924 This directive sets the Instruction Set Syntax as described in the
925 @ref{ARM-Instruction-Set} section.
927 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
929 @cindex @code{.thumb} directive, ARM
931 This performs the same action as @var{.code 16}.
933 @cindex @code{.thumb_func} directive, ARM
935 This directive specifies that the following symbol is the name of a
936 Thumb encoded function. This information is necessary in order to allow
937 the assembler and linker to generate correct code for interworking
938 between Arm and Thumb instructions and should be used even if
939 interworking is not going to be performed. The presence of this
940 directive also implies @code{.thumb}
942 This directive is not necessary when generating EABI objects. On these
943 targets the encoding is implicit when generating Thumb code.
945 @cindex @code{.thumb_set} directive, ARM
947 This performs the equivalent of a @code{.set} directive in that it
948 creates a symbol which is an alias for another symbol (possibly not yet
949 defined). This directive also has the added property in that it marks
950 the aliased symbol as being a thumb function entry point, in the same
951 way that the @code{.thumb_func} directive does.
953 @cindex @code{.tlsdescseq} directive, ARM
954 @item .tlsdescseq @var{tls-variable}
955 This directive is used to annotate parts of an inlined TLS descriptor
956 trampoline. Normally the trampoline is provided by the linker, and
957 this directive is not needed.
959 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
961 @cindex @code{.unreq} directive, ARM
962 @item .unreq @var{alias-name}
963 This undefines a register alias which was previously defined using the
964 @code{req}, @code{dn} or @code{qn} directives. For example:
971 An error occurs if the name is undefined. Note - this pseudo op can
972 be used to delete builtin in register name aliases (eg 'r0'). This
973 should only be done if it is really necessary.
975 @cindex @code{.unwind_raw} directive, ARM
976 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
977 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
978 the stack pointer by @var{offset} bytes.
980 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
983 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
985 @cindex @code{.vsave} directive, ARM
986 @item .vsave @var{vfp-reglist}
987 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
988 using FLDMD. Also works for VFPv3 registers
989 that are to be restored using VLDM.
990 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
994 @exdent @emph{VFP registers}
995 .vsave @{d8, d9, d10@}
996 fstmdd sp!, @{d8, d9, d10@}
997 @exdent @emph{VFPv3 registers}
998 .vsave @{d15, d16, d17@}
999 vstm sp!, @{d15, d16, d17@}
1002 Since FLDMX and FSTMX are now deprecated, this directive should be
1003 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1005 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1006 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1007 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1008 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1016 @cindex opcodes for ARM
1017 @code{@value{AS}} implements all the standard ARM opcodes. It also
1018 implements several pseudo opcodes, including several synthetic load
1023 @cindex @code{NOP} pseudo op, ARM
1029 This pseudo op will always evaluate to a legal ARM instruction that does
1030 nothing. Currently it will evaluate to MOV r0, r0.
1032 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1035 ldr <register> , = <expression>
1038 If expression evaluates to a numeric constant then a MOV or MVN
1039 instruction will be used in place of the LDR instruction, if the
1040 constant can be generated by either of these instructions. Otherwise
1041 the constant will be placed into the nearest literal pool (if it not
1042 already there) and a PC relative LDR instruction will be generated.
1044 @cindex @code{ADR reg,<label>} pseudo op, ARM
1047 adr <register> <label>
1050 This instruction will load the address of @var{label} into the indicated
1051 register. The instruction will evaluate to a PC relative ADD or SUB
1052 instruction depending upon where the label is located. If the label is
1053 out of range, or if it is not defined in the same file (and section) as
1054 the ADR instruction, then an error will be generated. This instruction
1055 will not make use of the literal pool.
1057 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1060 adrl <register> <label>
1063 This instruction will load the address of @var{label} into the indicated
1064 register. The instruction will evaluate to one or two PC relative ADD
1065 or SUB instructions depending upon where the label is located. If a
1066 second instruction is not needed a NOP instruction will be generated in
1067 its place, so that this instruction is always 8 bytes long.
1069 If the label is out of range, or if it is not defined in the same file
1070 (and section) as the ADRL instruction, then an error will be generated.
1071 This instruction will not make use of the literal pool.
1075 For information on the ARM or Thumb instruction sets, see @cite{ARM
1076 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1079 @node ARM Mapping Symbols
1080 @section Mapping Symbols
1082 The ARM ELF specification requires that special symbols be inserted
1083 into object files to mark certain features:
1089 At the start of a region of code containing ARM instructions.
1093 At the start of a region of code containing THUMB instructions.
1097 At the start of a region of data.
1101 The assembler will automatically insert these symbols for you - there
1102 is no need to code them yourself. Support for tagging symbols ($b,
1103 $f, $p and $m) which is also mentioned in the current ARM ELF
1104 specification is not implemented. This is because they have been
1105 dropped from the new EABI and so tools cannot rely upon their
1108 @node ARM Unwinding Tutorial
1111 The ABI for the ARM Architecture specifies a standard format for
1112 exception unwind information. This information is used when an
1113 exception is thrown to determine where control should be transferred.
1114 In particular, the unwind information is used to determine which
1115 function called the function that threw the exception, and which
1116 function called that one, and so forth. This information is also used
1117 to restore the values of callee-saved registers in the function
1118 catching the exception.
1120 If you are writing functions in assembly code, and those functions
1121 call other functions that throw exceptions, you must use assembly
1122 pseudo ops to ensure that appropriate exception unwind information is
1123 generated. Otherwise, if one of the functions called by your assembly
1124 code throws an exception, the run-time library will be unable to
1125 unwind the stack through your assembly code and your program will not
1128 To illustrate the use of these pseudo ops, we will examine the code
1129 that G++ generates for the following C++ input:
1132 void callee (int *);
1143 This example does not show how to throw or catch an exception from
1144 assembly code. That is a much more complex operation and should
1145 always be done in a high-level language, such as C++, that directly
1146 supports exceptions.
1148 The code generated by one particular version of G++ when compiling the
1155 @ Function supports interworking.
1156 @ args = 0, pretend = 0, frame = 8
1157 @ frame_needed = 1, uses_anonymous_args = 0
1179 Of course, the sequence of instructions varies based on the options
1180 you pass to GCC and on the version of GCC in use. The exact
1181 instructions are not important since we are focusing on the pseudo ops
1182 that are used to generate unwind information.
1184 An important assumption made by the unwinder is that the stack frame
1185 does not change during the body of the function. In particular, since
1186 we assume that the assembly code does not itself throw an exception,
1187 the only point where an exception can be thrown is from a call, such
1188 as the @code{bl} instruction above. At each call site, the same saved
1189 registers (including @code{lr}, which indicates the return address)
1190 must be located in the same locations relative to the frame pointer.
1192 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1193 op appears immediately before the first instruction of the function
1194 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1195 op appears immediately after the last instruction of the function.
1196 These pseudo ops specify the range of the function.
1198 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1199 @code{.pad}) matters; their exact locations are irrelevant. In the
1200 example above, the compiler emits the pseudo ops with particular
1201 instructions. That makes it easier to understand the code, but it is
1202 not required for correctness. It would work just as well to emit all
1203 of the pseudo ops other than @code{.fnend} in the same order, but
1204 immediately after @code{.fnstart}.
1206 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1207 indicates registers that have been saved to the stack so that they can
1208 be restored before the function returns. The argument to the
1209 @code{.save} pseudo op is a list of registers to save. If a register
1210 is ``callee-saved'' (as specified by the ABI) and is modified by the
1211 function you are writing, then your code must save the value before it
1212 is modified and restore the original value before the function
1213 returns. If an exception is thrown, the run-time library restores the
1214 values of these registers from their locations on the stack before
1215 returning control to the exception handler. (Of course, if an
1216 exception is not thrown, the function that contains the @code{.save}
1217 pseudo op restores these registers in the function epilogue, as is
1218 done with the @code{ldmfd} instruction above.)
1220 You do not have to save callee-saved registers at the very beginning
1221 of the function and you do not need to use the @code{.save} pseudo op
1222 immediately following the point at which the registers are saved.
1223 However, if you modify a callee-saved register, you must save it on
1224 the stack before modifying it and before calling any functions which
1225 might throw an exception. And, you must use the @code{.save} pseudo
1226 op to indicate that you have done so.
1228 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1229 modification of the stack pointer that does not save any registers.
1230 The argument is the number of bytes (in decimal) that are subtracted
1231 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1232 subtracting from the stack pointer increases the size of the stack.)
1234 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1235 indicates the register that contains the frame pointer. The first
1236 argument is the register that is set, which is typically @code{fp}.
1237 The second argument indicates the register from which the frame
1238 pointer takes its value. The third argument, if present, is the value
1239 (in decimal) added to the register specified by the second argument to
1240 compute the value of the frame pointer. You should not modify the
1241 frame pointer in the body of the function.
1243 If you do not use a frame pointer, then you should not use the
1244 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1245 should avoid modifying the stack pointer outside of the function
1246 prologue. Otherwise, the run-time library will be unable to find
1247 saved registers when it is unwinding the stack.
1249 The pseudo ops described above are sufficient for writing assembly
1250 code that calls functions which may throw exceptions. If you need to
1251 know more about the object-file format used to represent unwind
1252 information, you may consult the @cite{Exception Handling ABI for the
1253 ARM Architecture} available from @uref{http://infocenter.arm.com}.
projects / deliverable / binutils-gdb.git / blob