1 @c Copyright (C) 1996-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
144 @code{cortex-m0plus},
147 @code{marvell-whitney},
150 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
151 @code{i80200} (Intel XScale processor)
152 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
155 The special name @code{all} may be used to allow the
156 assembler to accept instructions valid for any ARM processor.
158 In addition to the basic instruction set, the assembler can be told to
159 accept various extension mnemonics that extend the processor using the
160 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
161 is equivalent to specifying @code{-mcpu=ep9312}.
163 Multiple extensions may be specified, separated by a @code{+}. The
164 extensions should be specified in ascending alphabetical order.
166 Some extensions may be restricted to particular architectures; this is
167 documented in the list of extensions below.
169 Extension mnemonics may also be removed from those the assembler accepts.
170 This is done be prepending @code{no} to the option that adds the extension.
171 Extensions that are removed should be listed after all extensions which have
172 been added, again in ascending alphabetical order. For example,
173 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
176 The following extensions are currently supported:
178 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
179 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
180 @code{fp} (Floating Point Extensions for v8-A architecture),
181 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
186 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
188 @code{os} (Operating System for v6M architecture),
189 @code{sec} (Security Extensions for v6K and v7-A architectures),
190 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
191 @code{virt} (Virtualization Extensions for v7-A architecture, implies
193 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
194 @code{ras} (Reliability, Availability and Serviceability extensions
195 for v8-A architecture),
196 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
201 @cindex @code{-march=} command line option, ARM
202 @item -march=@var{architecture}[+@var{extension}@dots{}]
203 This option specifies the target architecture. The assembler will issue
204 an error message if an attempt is made to assemble an instruction which
205 will not execute on the target architecture. The following architecture
206 names are recognized:
244 If both @code{-mcpu} and
245 @code{-march} are specified, the assembler will use
246 the setting for @code{-mcpu}.
248 The architecture option can be extended with the same instruction set
249 extension options as the @code{-mcpu} option.
251 @cindex @code{-mfpu=} command line option, ARM
252 @item -mfpu=@var{floating-point-format}
254 This option specifies the floating point format to assemble for. The
255 assembler will issue an error message if an attempt is made to assemble
256 an instruction which will not execute on the target floating point unit.
257 The following format options are recognized:
277 @code{vfpv3-d16-fp16},
294 @code{neon-fp-armv8},
295 @code{crypto-neon-fp-armv8},
296 @code{neon-fp-armv8.1}
298 @code{crypto-neon-fp-armv8.1}.
300 In addition to determining which instructions are assembled, this option
301 also affects the way in which the @code{.double} assembler directive behaves
302 when assembling little-endian code.
304 The default is dependent on the processor selected. For Architecture 5 or
305 later, the default is to assemble for VFP instructions; for earlier
306 architectures the default is to assemble for FPA instructions.
308 @cindex @code{-mthumb} command line option, ARM
310 This option specifies that the assembler should start assembling Thumb
311 instructions; that is, it should behave as though the file starts with a
312 @code{.code 16} directive.
314 @cindex @code{-mthumb-interwork} command line option, ARM
315 @item -mthumb-interwork
316 This option specifies that the output generated by the assembler should
317 be marked as supporting interworking.
319 @cindex @code{-mimplicit-it} command line option, ARM
320 @item -mimplicit-it=never
321 @itemx -mimplicit-it=always
322 @itemx -mimplicit-it=arm
323 @itemx -mimplicit-it=thumb
324 The @code{-mimplicit-it} option controls the behavior of the assembler when
325 conditional instructions are not enclosed in IT blocks.
326 There are four possible behaviors.
327 If @code{never} is specified, such constructs cause a warning in ARM
328 code and an error in Thumb-2 code.
329 If @code{always} is specified, such constructs are accepted in both
330 ARM and Thumb-2 code, where the IT instruction is added implicitly.
331 If @code{arm} is specified, such constructs are accepted in ARM code
332 and cause an error in Thumb-2 code.
333 If @code{thumb} is specified, such constructs cause a warning in ARM
334 code and are accepted in Thumb-2 code. If you omit this option, the
335 behavior is equivalent to @code{-mimplicit-it=arm}.
337 @cindex @code{-mapcs-26} command line option, ARM
338 @cindex @code{-mapcs-32} command line option, ARM
341 These options specify that the output generated by the assembler should
342 be marked as supporting the indicated version of the Arm Procedure.
345 @cindex @code{-matpcs} command line option, ARM
347 This option specifies that the output generated by the assembler should
348 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
349 enabled this option will cause the assembler to create an empty
350 debugging section in the object file called .arm.atpcs. Debuggers can
351 use this to determine the ABI being used by.
353 @cindex @code{-mapcs-float} command line option, ARM
355 This indicates the floating point variant of the APCS should be
356 used. In this variant floating point arguments are passed in FP
357 registers rather than integer registers.
359 @cindex @code{-mapcs-reentrant} command line option, ARM
360 @item -mapcs-reentrant
361 This indicates that the reentrant variant of the APCS should be used.
362 This variant supports position independent code.
364 @cindex @code{-mfloat-abi=} command line option, ARM
365 @item -mfloat-abi=@var{abi}
366 This option specifies that the output generated by the assembler should be
367 marked as using specified floating point ABI.
368 The following values are recognized:
374 @cindex @code{-eabi=} command line option, ARM
375 @item -meabi=@var{ver}
376 This option specifies which EABI version the produced object files should
378 The following values are recognized:
384 @cindex @code{-EB} command line option, ARM
386 This option specifies that the output generated by the assembler should
387 be marked as being encoded for a big-endian processor.
389 Note: If a program is being built for a system with big-endian data
390 and little-endian instructions then it should be assembled with the
391 @option{-EB} option, (all of it, code and data) and then linked with
392 the @option{--be8} option. This will reverse the endianness of the
393 instructions back to little-endian, but leave the data as big-endian.
395 @cindex @code{-EL} command line option, ARM
397 This option specifies that the output generated by the assembler should
398 be marked as being encoded for a little-endian processor.
400 @cindex @code{-k} command line option, ARM
401 @cindex PIC code generation for ARM
403 This option specifies that the output of the assembler should be marked
404 as position-independent code (PIC).
406 @cindex @code{--fix-v4bx} command line option, ARM
408 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
409 the linker option of the same name.
411 @cindex @code{-mwarn-deprecated} command line option, ARM
412 @item -mwarn-deprecated
413 @itemx -mno-warn-deprecated
414 Enable or disable warnings about using deprecated options or
415 features. The default is to warn.
417 @cindex @code{-mccs} command line option, ARM
419 Turns on CodeComposer Studio assembly syntax compatibility mode.
421 @cindex @code{-mwarn-syms} command line option, ARM
423 @itemx -mno-warn-syms
424 Enable or disable warnings about symbols that match the names of ARM
425 instructions. The default is to warn.
433 * ARM-Instruction-Set:: Instruction Set
434 * ARM-Chars:: Special Characters
435 * ARM-Regs:: Register Names
436 * ARM-Relocations:: Relocations
437 * ARM-Neon-Alignment:: NEON Alignment Specifiers
440 @node ARM-Instruction-Set
441 @subsection Instruction Set Syntax
442 Two slightly different syntaxes are support for ARM and THUMB
443 instructions. The default, @code{divided}, uses the old style where
444 ARM and THUMB instructions had their own, separate syntaxes. The new,
445 @code{unified} syntax, which can be selected via the @code{.syntax}
446 directive, and has the following main features:
450 Immediate operands do not require a @code{#} prefix.
453 The @code{IT} instruction may appear, and if it does it is validated
454 against subsequent conditional affixes. In ARM mode it does not
455 generate machine code, in THUMB mode it does.
458 For ARM instructions the conditional affixes always appear at the end
459 of the instruction. For THUMB instructions conditional affixes can be
460 used, but only inside the scope of an @code{IT} instruction.
463 All of the instructions new to the V6T2 architecture (and later) are
464 available. (Only a few such instructions can be written in the
465 @code{divided} syntax).
468 The @code{.N} and @code{.W} suffixes are recognized and honored.
471 All instructions set the flags if and only if they have an @code{s}
476 @subsection Special Characters
478 @cindex line comment character, ARM
479 @cindex ARM line comment character
480 The presence of a @samp{@@} anywhere on a line indicates the start of
481 a comment that extends to the end of that line.
483 If a @samp{#} appears as the first character of a line then the whole
484 line is treated as a comment, but in this case the line could also be
485 a logical line number directive (@pxref{Comments}) or a preprocessor
486 control command (@pxref{Preprocessing}).
488 @cindex line separator, ARM
489 @cindex statement separator, ARM
490 @cindex ARM line separator
491 The @samp{;} character can be used instead of a newline to separate
494 @cindex immediate character, ARM
495 @cindex ARM immediate character
496 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
498 @cindex identifiers, ARM
499 @cindex ARM identifiers
500 *TODO* Explain about /data modifier on symbols.
503 @subsection Register Names
505 @cindex ARM register names
506 @cindex register names, ARM
507 *TODO* Explain about ARM register naming, and the predefined names.
509 @node ARM-Relocations
510 @subsection ARM relocation generation
512 @cindex data relocations, ARM
513 @cindex ARM data relocations
514 Specific data relocations can be generated by putting the relocation name
515 in parentheses after the symbol name. For example:
521 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
523 The following relocations are supported:
539 For compatibility with older toolchains the assembler also accepts
540 @code{(PLT)} after branch targets. On legacy targets this will
541 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
542 targets it will encode either the @samp{R_ARM_CALL} or
543 @samp{R_ARM_JUMP24} relocation, as appropriate.
545 @cindex MOVW and MOVT relocations, ARM
546 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
547 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
548 respectively. For example to load the 32-bit address of foo into r0:
551 MOVW r0, #:lower16:foo
552 MOVT r0, #:upper16:foo
555 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
556 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
557 generated by prefixing the value with @samp{#:lower0_7:#},
558 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
559 respectively. For example to load the 32-bit address of foo into r0:
562 MOVS r0, #:upper8_15:#foo
564 ADDS r0, #:upper0_7:#foo
566 ADDS r0, #:lower8_15:#foo
568 ADDS r0, #:lower0_7:#foo
571 @node ARM-Neon-Alignment
572 @subsection NEON Alignment Specifiers
574 @cindex alignment for NEON instructions
575 Some NEON load/store instructions allow an optional address
577 The ARM documentation specifies that this is indicated by
578 @samp{@@ @var{align}}. However GAS already interprets
579 the @samp{@@} character as a "line comment" start,
580 so @samp{: @var{align}} is used instead. For example:
583 vld1.8 @{q0@}, [r0, :128]
586 @node ARM Floating Point
587 @section Floating Point
589 @cindex floating point, ARM (@sc{ieee})
590 @cindex ARM floating point (@sc{ieee})
591 The ARM family uses @sc{ieee} floating-point numbers.
594 @section ARM Machine Directives
596 @cindex machine directives, ARM
597 @cindex ARM machine directives
600 @c AAAAAAAAAAAAAAAAAAAAAAAAA
603 @cindex @code{.2byte} directive, ARM
604 @cindex @code{.4byte} directive, ARM
605 @cindex @code{.8byte} directive, ARM
606 @item .2byte @var{expression} [, @var{expression}]*
607 @itemx .4byte @var{expression} [, @var{expression}]*
608 @itemx .8byte @var{expression} [, @var{expression}]*
609 These directives write 2, 4 or 8 byte values to the output section.
612 @cindex @code{.align} directive, ARM
613 @item .align @var{expression} [, @var{expression}]
614 This is the generic @var{.align} directive. For the ARM however if the
615 first argument is zero (ie no alignment is needed) the assembler will
616 behave as if the argument had been 2 (ie pad to the next four byte
617 boundary). This is for compatibility with ARM's own assembler.
619 @cindex @code{.arch} directive, ARM
620 @item .arch @var{name}
621 Select the target architecture. Valid values for @var{name} are the same as
622 for the @option{-march} commandline option.
624 Specifying @code{.arch} clears any previously selected architecture
627 @cindex @code{.arch_extension} directive, ARM
628 @item .arch_extension @var{name}
629 Add or remove an architecture extension to the target architecture. Valid
630 values for @var{name} are the same as those accepted as architectural
631 extensions by the @option{-mcpu} commandline option.
633 @code{.arch_extension} may be used multiple times to add or remove extensions
634 incrementally to the architecture being compiled for.
636 @cindex @code{.arm} directive, ARM
638 This performs the same action as @var{.code 32}.
640 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
642 @cindex @code{.bss} directive, ARM
644 This directive switches to the @code{.bss} section.
646 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
648 @cindex @code{.cantunwind} directive, ARM
650 Prevents unwinding through the current function. No personality routine
651 or exception table data is required or permitted.
653 @cindex @code{.code} directive, ARM
654 @item .code @code{[16|32]}
655 This directive selects the instruction set being generated. The value 16
656 selects Thumb, with the value 32 selecting ARM.
658 @cindex @code{.cpu} directive, ARM
659 @item .cpu @var{name}
660 Select the target processor. Valid values for @var{name} are the same as
661 for the @option{-mcpu} commandline option.
663 Specifying @code{.cpu} clears any previously selected architecture
666 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
668 @cindex @code{.dn} and @code{.qn} directives, ARM
669 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
670 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
672 The @code{dn} and @code{qn} directives are used to create typed
673 and/or indexed register aliases for use in Advanced SIMD Extension
674 (Neon) instructions. The former should be used to create aliases
675 of double-precision registers, and the latter to create aliases of
676 quad-precision registers.
678 If these directives are used to create typed aliases, those aliases can
679 be used in Neon instructions instead of writing types after the mnemonic
680 or after each operand. For example:
689 This is equivalent to writing the following:
695 Aliases created using @code{dn} or @code{qn} can be destroyed using
698 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
700 @cindex @code{.eabi_attribute} directive, ARM
701 @item .eabi_attribute @var{tag}, @var{value}
702 Set the EABI object attribute @var{tag} to @var{value}.
704 The @var{tag} is either an attribute number, or one of the following:
705 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
706 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
707 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
708 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
709 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
710 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
711 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
712 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
713 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
714 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
715 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
716 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
717 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
718 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
719 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
720 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
721 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
722 @code{Tag_conformance}, @code{Tag_T2EE_use},
723 @code{Tag_Virtualization_use}
725 The @var{value} is either a @code{number}, @code{"string"}, or
726 @code{number, "string"} depending on the tag.
728 Note - the following legacy values are also accepted by @var{tag}:
729 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
730 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
732 @cindex @code{.even} directive, ARM
734 This directive aligns to an even-numbered address.
736 @cindex @code{.extend} directive, ARM
737 @cindex @code{.ldouble} directive, ARM
738 @item .extend @var{expression} [, @var{expression}]*
739 @itemx .ldouble @var{expression} [, @var{expression}]*
740 These directives write 12byte long double floating-point values to the
741 output section. These are not compatible with current ARM processors
744 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
747 @cindex @code{.fnend} directive, ARM
749 Marks the end of a function with an unwind table entry. The unwind index
750 table entry is created when this directive is processed.
752 If no personality routine has been specified then standard personality
753 routine 0 or 1 will be used, depending on the number of unwind opcodes
757 @cindex @code{.fnstart} directive, ARM
759 Marks the start of a function with an unwind table entry.
761 @cindex @code{.force_thumb} directive, ARM
763 This directive forces the selection of Thumb instructions, even if the
764 target processor does not support those instructions
766 @cindex @code{.fpu} directive, ARM
767 @item .fpu @var{name}
768 Select the floating-point unit to assemble for. Valid values for @var{name}
769 are the same as for the @option{-mfpu} commandline option.
771 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
772 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
774 @cindex @code{.handlerdata} directive, ARM
776 Marks the end of the current function, and the start of the exception table
777 entry for that function. Anything between this directive and the
778 @code{.fnend} directive will be added to the exception table entry.
780 Must be preceded by a @code{.personality} or @code{.personalityindex}
783 @c IIIIIIIIIIIIIIIIIIIIIIIIII
785 @cindex @code{.inst} directive, ARM
786 @item .inst @var{opcode} [ , @dots{} ]
787 @itemx .inst.n @var{opcode} [ , @dots{} ]
788 @itemx .inst.w @var{opcode} [ , @dots{} ]
789 Generates the instruction corresponding to the numerical value @var{opcode}.
790 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
791 specified explicitly, overriding the normal encoding rules.
793 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
794 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
795 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
797 @item .ldouble @var{expression} [, @var{expression}]*
800 @cindex @code{.ltorg} directive, ARM
802 This directive causes the current contents of the literal pool to be
803 dumped into the current section (which is assumed to be the .text
804 section) at the current location (aligned to a word boundary).
805 @code{GAS} maintains a separate literal pool for each section and each
806 sub-section. The @code{.ltorg} directive will only affect the literal
807 pool of the current section and sub-section. At the end of assembly
808 all remaining, un-empty literal pools will automatically be dumped.
810 Note - older versions of @code{GAS} would dump the current literal
811 pool any time a section change occurred. This is no longer done, since
812 it prevents accurate control of the placement of literal pools.
814 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
816 @cindex @code{.movsp} directive, ARM
817 @item .movsp @var{reg} [, #@var{offset}]
818 Tell the unwinder that @var{reg} contains an offset from the current
819 stack pointer. If @var{offset} is not specified then it is assumed to be
822 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
823 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
825 @cindex @code{.object_arch} directive, ARM
826 @item .object_arch @var{name}
827 Override the architecture recorded in the EABI object attribute section.
828 Valid values for @var{name} are the same as for the @code{.arch} directive.
829 Typically this is useful when code uses runtime detection of CPU features.
831 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
833 @cindex @code{.packed} directive, ARM
834 @item .packed @var{expression} [, @var{expression}]*
835 This directive writes 12-byte packed floating-point values to the
836 output section. These are not compatible with current ARM processors
840 @cindex @code{.pad} directive, ARM
841 @item .pad #@var{count}
842 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
843 A positive value indicates the function prologue allocated stack space by
844 decrementing the stack pointer.
846 @cindex @code{.personality} directive, ARM
847 @item .personality @var{name}
848 Sets the personality routine for the current function to @var{name}.
850 @cindex @code{.personalityindex} directive, ARM
851 @item .personalityindex @var{index}
852 Sets the personality routine for the current function to the EABI standard
853 routine number @var{index}
855 @cindex @code{.pool} directive, ARM
857 This is a synonym for .ltorg.
859 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
860 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
862 @cindex @code{.req} directive, ARM
863 @item @var{name} .req @var{register name}
864 This creates an alias for @var{register name} called @var{name}. For
871 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
874 @cindex @code{.save} directive, ARM
875 @item .save @var{reglist}
876 Generate unwinder annotations to restore the registers in @var{reglist}.
877 The format of @var{reglist} is the same as the corresponding store-multiple
881 @exdent @emph{core registers}
882 .save @{r4, r5, r6, lr@}
883 stmfd sp!, @{r4, r5, r6, lr@}
884 @exdent @emph{FPA registers}
887 @exdent @emph{VFP registers}
888 .save @{d8, d9, d10@}
889 fstmdx sp!, @{d8, d9, d10@}
890 @exdent @emph{iWMMXt registers}
892 wstrd wr11, [sp, #-8]!
893 wstrd wr10, [sp, #-8]!
896 wstrd wr11, [sp, #-8]!
898 wstrd wr10, [sp, #-8]!
902 @cindex @code{.setfp} directive, ARM
903 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
904 Make all unwinder annotations relative to a frame pointer. Without this
905 the unwinder will use offsets from the stack pointer.
907 The syntax of this directive is the same as the @code{add} or @code{mov}
908 instruction used to set the frame pointer. @var{spreg} must be either
909 @code{sp} or mentioned in a previous @code{.movsp} directive.
919 @cindex @code{.secrel32} directive, ARM
920 @item .secrel32 @var{expression} [, @var{expression}]*
921 This directive emits relocations that evaluate to the section-relative
922 offset of each expression's symbol. This directive is only supported
925 @cindex @code{.syntax} directive, ARM
926 @item .syntax [@code{unified} | @code{divided}]
927 This directive sets the Instruction Set Syntax as described in the
928 @ref{ARM-Instruction-Set} section.
930 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
932 @cindex @code{.thumb} directive, ARM
934 This performs the same action as @var{.code 16}.
936 @cindex @code{.thumb_func} directive, ARM
938 This directive specifies that the following symbol is the name of a
939 Thumb encoded function. This information is necessary in order to allow
940 the assembler and linker to generate correct code for interworking
941 between Arm and Thumb instructions and should be used even if
942 interworking is not going to be performed. The presence of this
943 directive also implies @code{.thumb}
945 This directive is not necessary when generating EABI objects. On these
946 targets the encoding is implicit when generating Thumb code.
948 @cindex @code{.thumb_set} directive, ARM
950 This performs the equivalent of a @code{.set} directive in that it
951 creates a symbol which is an alias for another symbol (possibly not yet
952 defined). This directive also has the added property in that it marks
953 the aliased symbol as being a thumb function entry point, in the same
954 way that the @code{.thumb_func} directive does.
956 @cindex @code{.tlsdescseq} directive, ARM
957 @item .tlsdescseq @var{tls-variable}
958 This directive is used to annotate parts of an inlined TLS descriptor
959 trampoline. Normally the trampoline is provided by the linker, and
960 this directive is not needed.
962 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
964 @cindex @code{.unreq} directive, ARM
965 @item .unreq @var{alias-name}
966 This undefines a register alias which was previously defined using the
967 @code{req}, @code{dn} or @code{qn} directives. For example:
974 An error occurs if the name is undefined. Note - this pseudo op can
975 be used to delete builtin in register name aliases (eg 'r0'). This
976 should only be done if it is really necessary.
978 @cindex @code{.unwind_raw} directive, ARM
979 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
980 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
981 the stack pointer by @var{offset} bytes.
983 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
986 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
988 @cindex @code{.vsave} directive, ARM
989 @item .vsave @var{vfp-reglist}
990 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
991 using FLDMD. Also works for VFPv3 registers
992 that are to be restored using VLDM.
993 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
997 @exdent @emph{VFP registers}
998 .vsave @{d8, d9, d10@}
999 fstmdd sp!, @{d8, d9, d10@}
1000 @exdent @emph{VFPv3 registers}
1001 .vsave @{d15, d16, d17@}
1002 vstm sp!, @{d15, d16, d17@}
1005 Since FLDMX and FSTMX are now deprecated, this directive should be
1006 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1008 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1009 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1010 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1011 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1019 @cindex opcodes for ARM
1020 @code{@value{AS}} implements all the standard ARM opcodes. It also
1021 implements several pseudo opcodes, including several synthetic load
1026 @cindex @code{NOP} pseudo op, ARM
1032 This pseudo op will always evaluate to a legal ARM instruction that does
1033 nothing. Currently it will evaluate to MOV r0, r0.
1035 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1038 ldr <register> , = <expression>
1041 If expression evaluates to a numeric constant then a MOV or MVN
1042 instruction will be used in place of the LDR instruction, if the
1043 constant can be generated by either of these instructions. Otherwise
1044 the constant will be placed into the nearest literal pool (if it not
1045 already there) and a PC relative LDR instruction will be generated.
1047 @cindex @code{ADR reg,<label>} pseudo op, ARM
1050 adr <register> <label>
1053 This instruction will load the address of @var{label} into the indicated
1054 register. The instruction will evaluate to a PC relative ADD or SUB
1055 instruction depending upon where the label is located. If the label is
1056 out of range, or if it is not defined in the same file (and section) as
1057 the ADR instruction, then an error will be generated. This instruction
1058 will not make use of the literal pool.
1060 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1063 adrl <register> <label>
1066 This instruction will load the address of @var{label} into the indicated
1067 register. The instruction will evaluate to one or two PC relative ADD
1068 or SUB instructions depending upon where the label is located. If a
1069 second instruction is not needed a NOP instruction will be generated in
1070 its place, so that this instruction is always 8 bytes long.
1072 If the label is out of range, or if it is not defined in the same file
1073 (and section) as the ADRL instruction, then an error will be generated.
1074 This instruction will not make use of the literal pool.
1078 For information on the ARM or Thumb instruction sets, see @cite{ARM
1079 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1082 @node ARM Mapping Symbols
1083 @section Mapping Symbols
1085 The ARM ELF specification requires that special symbols be inserted
1086 into object files to mark certain features:
1092 At the start of a region of code containing ARM instructions.
1096 At the start of a region of code containing THUMB instructions.
1100 At the start of a region of data.
1104 The assembler will automatically insert these symbols for you - there
1105 is no need to code them yourself. Support for tagging symbols ($b,
1106 $f, $p and $m) which is also mentioned in the current ARM ELF
1107 specification is not implemented. This is because they have been
1108 dropped from the new EABI and so tools cannot rely upon their
1111 @node ARM Unwinding Tutorial
1114 The ABI for the ARM Architecture specifies a standard format for
1115 exception unwind information. This information is used when an
1116 exception is thrown to determine where control should be transferred.
1117 In particular, the unwind information is used to determine which
1118 function called the function that threw the exception, and which
1119 function called that one, and so forth. This information is also used
1120 to restore the values of callee-saved registers in the function
1121 catching the exception.
1123 If you are writing functions in assembly code, and those functions
1124 call other functions that throw exceptions, you must use assembly
1125 pseudo ops to ensure that appropriate exception unwind information is
1126 generated. Otherwise, if one of the functions called by your assembly
1127 code throws an exception, the run-time library will be unable to
1128 unwind the stack through your assembly code and your program will not
1131 To illustrate the use of these pseudo ops, we will examine the code
1132 that G++ generates for the following C++ input:
1135 void callee (int *);
1146 This example does not show how to throw or catch an exception from
1147 assembly code. That is a much more complex operation and should
1148 always be done in a high-level language, such as C++, that directly
1149 supports exceptions.
1151 The code generated by one particular version of G++ when compiling the
1158 @ Function supports interworking.
1159 @ args = 0, pretend = 0, frame = 8
1160 @ frame_needed = 1, uses_anonymous_args = 0
1182 Of course, the sequence of instructions varies based on the options
1183 you pass to GCC and on the version of GCC in use. The exact
1184 instructions are not important since we are focusing on the pseudo ops
1185 that are used to generate unwind information.
1187 An important assumption made by the unwinder is that the stack frame
1188 does not change during the body of the function. In particular, since
1189 we assume that the assembly code does not itself throw an exception,
1190 the only point where an exception can be thrown is from a call, such
1191 as the @code{bl} instruction above. At each call site, the same saved
1192 registers (including @code{lr}, which indicates the return address)
1193 must be located in the same locations relative to the frame pointer.
1195 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1196 op appears immediately before the first instruction of the function
1197 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1198 op appears immediately after the last instruction of the function.
1199 These pseudo ops specify the range of the function.
1201 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1202 @code{.pad}) matters; their exact locations are irrelevant. In the
1203 example above, the compiler emits the pseudo ops with particular
1204 instructions. That makes it easier to understand the code, but it is
1205 not required for correctness. It would work just as well to emit all
1206 of the pseudo ops other than @code{.fnend} in the same order, but
1207 immediately after @code{.fnstart}.
1209 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1210 indicates registers that have been saved to the stack so that they can
1211 be restored before the function returns. The argument to the
1212 @code{.save} pseudo op is a list of registers to save. If a register
1213 is ``callee-saved'' (as specified by the ABI) and is modified by the
1214 function you are writing, then your code must save the value before it
1215 is modified and restore the original value before the function
1216 returns. If an exception is thrown, the run-time library restores the
1217 values of these registers from their locations on the stack before
1218 returning control to the exception handler. (Of course, if an
1219 exception is not thrown, the function that contains the @code{.save}
1220 pseudo op restores these registers in the function epilogue, as is
1221 done with the @code{ldmfd} instruction above.)
1223 You do not have to save callee-saved registers at the very beginning
1224 of the function and you do not need to use the @code{.save} pseudo op
1225 immediately following the point at which the registers are saved.
1226 However, if you modify a callee-saved register, you must save it on
1227 the stack before modifying it and before calling any functions which
1228 might throw an exception. And, you must use the @code{.save} pseudo
1229 op to indicate that you have done so.
1231 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1232 modification of the stack pointer that does not save any registers.
1233 The argument is the number of bytes (in decimal) that are subtracted
1234 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1235 subtracting from the stack pointer increases the size of the stack.)
1237 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1238 indicates the register that contains the frame pointer. The first
1239 argument is the register that is set, which is typically @code{fp}.
1240 The second argument indicates the register from which the frame
1241 pointer takes its value. The third argument, if present, is the value
1242 (in decimal) added to the register specified by the second argument to
1243 compute the value of the frame pointer. You should not modify the
1244 frame pointer in the body of the function.
1246 If you do not use a frame pointer, then you should not use the
1247 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1248 should avoid modifying the stack pointer outside of the function
1249 prologue. Otherwise, the run-time library will be unable to find
1250 saved registers when it is unwinding the stack.
1252 The pseudo ops described above are sufficient for writing assembly
1253 code that calls functions which may throw exceptions. If you need to
1254 know more about the object-file format used to represent unwind
1255 information, you may consult the @cite{Exception Handling ABI for the
1256 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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