1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
95 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
96 @code{i80200} (Intel XScale processor)
97 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
100 The special name @code{all} may be used to allow the
101 assembler to accept instructions valid for any ARM processor.
103 In addition to the basic instruction set, the assembler can be told to
104 accept various extension mnemonics that extend the processor using the
105 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
106 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
107 are currently supported:
113 @cindex @code{-march=} command line option, ARM
114 @item -march=@var{architecture}[+@var{extension}@dots{}]
115 This option specifies the target architecture. The assembler will issue
116 an error message if an attempt is made to assemble an instruction which
117 will not execute on the target architecture. The following architecture
118 names are recognized:
138 If both @code{-mcpu} and
139 @code{-march} are specified, the assembler will use
140 the setting for @code{-mcpu}.
142 The architecture option can be extended with the same instruction set
143 extension options as the @code{-mcpu} option.
145 @cindex @code{-mfpu=} command line option, ARM
146 @item -mfpu=@var{floating-point-format}
148 This option specifies the floating point format to assemble for. The
149 assembler will issue an error message if an attempt is made to assemble
150 an instruction which will not execute on the target floating point unit.
151 The following format options are recognized:
173 In addition to determining which instructions are assembled, this option
174 also affects the way in which the @code{.double} assembler directive behaves
175 when assembling little-endian code.
177 The default is dependent on the processor selected. For Architecture 5 or
178 later, the default is to assembler for VFP instructions; for earlier
179 architectures the default is to assemble for FPA instructions.
181 @cindex @code{-mthumb} command line option, ARM
183 This option specifies that the assembler should start assembling Thumb
184 instructions; that is, it should behave as though the file starts with a
185 @code{.code 16} directive.
187 @cindex @code{-mthumb-interwork} command line option, ARM
188 @item -mthumb-interwork
189 This option specifies that the output generated by the assembler should
190 be marked as supporting interworking.
192 @cindex @code{-mapcs} command line option, ARM
193 @item -mapcs @code{[26|32]}
194 This option specifies that the output generated by the assembler should
195 be marked as supporting the indicated version of the Arm Procedure.
198 @cindex @code{-matpcs} command line option, ARM
200 This option specifies that the output generated by the assembler should
201 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
202 enabled this option will cause the assembler to create an empty
203 debugging section in the object file called .arm.atpcs. Debuggers can
204 use this to determine the ABI being used by.
206 @cindex @code{-mapcs-float} command line option, ARM
208 This indicates the floating point variant of the APCS should be
209 used. In this variant floating point arguments are passed in FP
210 registers rather than integer registers.
212 @cindex @code{-mapcs-reentrant} command line option, ARM
213 @item -mapcs-reentrant
214 This indicates that the reentrant variant of the APCS should be used.
215 This variant supports position independent code.
217 @cindex @code{-mfloat-abi=} command line option, ARM
218 @item -mfloat-abi=@var{abi}
219 This option specifies that the output generated by the assembler should be
220 marked as using specified floating point ABI.
221 The following values are recognized:
227 @cindex @code{-EB} command line option, ARM
229 This option specifies that the output generated by the assembler should
230 be marked as being encoded for a big-endian processor.
232 @cindex @code{-EL} command line option, ARM
234 This option specifies that the output generated by the assembler should
235 be marked as being encoded for a little-endian processor.
237 @cindex @code{-k} command line option, ARM
238 @cindex PIC code generation for ARM
240 This option specifies that the output of the assembler should be marked
241 as position-independent code (PIC).
243 @cindex @code{-moabi} command line option, ARM
245 This indicates that the code should be assembled using the old ARM ELF
246 conventions, based on a beta release release of the ARM-ELF
247 specifications, rather than the default conventions which are based on
248 the final release of the ARM-ELF specifications.
256 * ARM-Chars:: Special Characters
257 * ARM-Regs:: Register Names
261 @subsection Special Characters
263 @cindex line comment character, ARM
264 @cindex ARM line comment character
265 The presence of a @samp{@@} on a line indicates the start of a comment
266 that extends to the end of the current line. If a @samp{#} appears as
267 the first character of a line, the whole line is treated as a comment.
269 @cindex line separator, ARM
270 @cindex statement separator, ARM
271 @cindex ARM line separator
272 The @samp{;} character can be used instead of a newline to separate
275 @cindex immediate character, ARM
276 @cindex ARM immediate character
277 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
279 @cindex identifiers, ARM
280 @cindex ARM identifiers
281 *TODO* Explain about /data modifier on symbols.
284 @subsection Register Names
286 @cindex ARM register names
287 @cindex register names, ARM
288 *TODO* Explain about ARM register naming, and the predefined names.
290 @node ARM Floating Point
291 @section Floating Point
293 @cindex floating point, ARM (@sc{ieee})
294 @cindex ARM floating point (@sc{ieee})
295 The ARM family uses @sc{ieee} floating-point numbers.
300 @section ARM Machine Directives
302 @cindex machine directives, ARM
303 @cindex ARM machine directives
306 @cindex @code{align} directive, ARM
307 @item .align @var{expression} [, @var{expression}]
308 This is the generic @var{.align} directive. For the ARM however if the
309 first argument is zero (ie no alignment is needed) the assembler will
310 behave as if the argument had been 2 (ie pad to the next four byte
311 boundary). This is for compatibility with ARM's own assembler.
313 @cindex @code{req} directive, ARM
314 @item @var{name} .req @var{register name}
315 This creates an alias for @var{register name} called @var{name}. For
322 @cindex @code{unreq} directive, ARM
323 @item .unreq @var{alias-name}
324 This undefines a register alias which was previously defined using the
325 @code{req} directive. For example:
332 An error occurs if the name is undefined. Note - this pseudo op can
333 be used to delete builtin in register name aliases (eg 'r0'). This
334 should only be done if it is really necessary.
336 @cindex @code{code} directive, ARM
337 @item .code @code{[16|32]}
338 This directive selects the instruction set being generated. The value 16
339 selects Thumb, with the value 32 selecting ARM.
341 @cindex @code{thumb} directive, ARM
343 This performs the same action as @var{.code 16}.
345 @cindex @code{arm} directive, ARM
347 This performs the same action as @var{.code 32}.
349 @cindex @code{force_thumb} directive, ARM
351 This directive forces the selection of Thumb instructions, even if the
352 target processor does not support those instructions
354 @cindex @code{thumb_func} directive, ARM
356 This directive specifies that the following symbol is the name of a
357 Thumb encoded function. This information is necessary in order to allow
358 the assembler and linker to generate correct code for interworking
359 between Arm and Thumb instructions and should be used even if
360 interworking is not going to be performed. The presence of this
361 directive also implies @code{.thumb}
363 @cindex @code{thumb_set} directive, ARM
365 This performs the equivalent of a @code{.set} directive in that it
366 creates a symbol which is an alias for another symbol (possibly not yet
367 defined). This directive also has the added property in that it marks
368 the aliased symbol as being a thumb function entry point, in the same
369 way that the @code{.thumb_func} directive does.
371 @cindex @code{.ltorg} directive, ARM
373 This directive causes the current contents of the literal pool to be
374 dumped into the current section (which is assumed to be the .text
375 section) at the current location (aligned to a word boundary).
376 @code{GAS} maintains a separate literal pool for each section and each
377 sub-section. The @code{.ltorg} directive will only affect the literal
378 pool of the current section and sub-section. At the end of assembly
379 all remaining, un-empty literal pools will automatically be dumped.
381 Note - older versions of @code{GAS} would dump the current literal
382 pool any time a section change occurred. This is no longer done, since
383 it prevents accurate control of the placement of literal pools.
385 @cindex @code{.pool} directive, ARM
387 This is a synonym for .ltorg.
395 @cindex opcodes for ARM
396 @code{@value{AS}} implements all the standard ARM opcodes. It also
397 implements several pseudo opcodes, including several synthetic load
402 @cindex @code{NOP} pseudo op, ARM
408 This pseudo op will always evaluate to a legal ARM instruction that does
409 nothing. Currently it will evaluate to MOV r0, r0.
411 @cindex @code{LDR reg,=<label>} pseudo op, ARM
414 ldr <register> , = <expression>
417 If expression evaluates to a numeric constant then a MOV or MVN
418 instruction will be used in place of the LDR instruction, if the
419 constant can be generated by either of these instructions. Otherwise
420 the constant will be placed into the nearest literal pool (if it not
421 already there) and a PC relative LDR instruction will be generated.
423 @cindex @code{ADR reg,<label>} pseudo op, ARM
426 adr <register> <label>
429 This instruction will load the address of @var{label} into the indicated
430 register. The instruction will evaluate to a PC relative ADD or SUB
431 instruction depending upon where the label is located. If the label is
432 out of range, or if it is not defined in the same file (and section) as
433 the ADR instruction, then an error will be generated. This instruction
434 will not make use of the literal pool.
436 @cindex @code{ADRL reg,<label>} pseudo op, ARM
439 adrl <register> <label>
442 This instruction will load the address of @var{label} into the indicated
443 register. The instruction will evaluate to one or two PC relative ADD
444 or SUB instructions depending upon where the label is located. If a
445 second instruction is not needed a NOP instruction will be generated in
446 its place, so that this instruction is always 8 bytes long.
448 If the label is out of range, or if it is not defined in the same file
449 (and section) as the ADRL instruction, then an error will be generated.
450 This instruction will not make use of the literal pool.
454 For information on the ARM or Thumb instruction sets, see @cite{ARM
455 Software Development Toolkit Reference Manual}, Advanced RISC Machines
458 @node ARM Mapping Symbols
459 @section Mapping Symbols
461 The ARM ELF specification requires that special symbols be inserted
462 into object files to mark certain features:
468 At the start of a region of code containing ARM instructions.
472 At the start of a region of code containing THUMB instructions.
476 At the start of a region of data.
480 The assembler will automatically insert these symbols for you - there
481 is no need to code them yourself. Support for tagging symbols ($b,
482 $f, $p and $m) which is also mentioned in the current ARM ELF
483 specification is not implemented. This is because they have been
484 dropped from the new EABI and so tools cannot rely upon their