1 @c Copyright (C) 1996-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
139 @code{cortex-m0plus},
142 @code{marvell-whitney},
147 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
148 @code{i80200} (Intel XScale processor)
149 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
152 The special name @code{all} may be used to allow the
153 assembler to accept instructions valid for any ARM processor.
155 In addition to the basic instruction set, the assembler can be told to
156 accept various extension mnemonics that extend the processor using the
157 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
158 is equivalent to specifying @code{-mcpu=ep9312}.
160 Multiple extensions may be specified, separated by a @code{+}. The
161 extensions should be specified in ascending alphabetical order.
163 Some extensions may be restricted to particular architectures; this is
164 documented in the list of extensions below.
166 Extension mnemonics may also be removed from those the assembler accepts.
167 This is done be prepending @code{no} to the option that adds the extension.
168 Extensions that are removed should be listed after all extensions which have
169 been added, again in ascending alphabetical order. For example,
170 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
173 The following extensions are currently supported:
175 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
176 @code{fp} (Floating Point Extensions for v8-A architecture),
177 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
182 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
184 @code{os} (Operating System for v6M architecture),
185 @code{sec} (Security Extensions for v6K and v7-A architectures),
186 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
187 @code{virt} (Virtualization Extensions for v7-A architecture, implies
189 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
190 @code{ras} (Reliability, Availability and Serviceability extensions
191 for v8-A architecture),
192 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
197 @cindex @code{-march=} command line option, ARM
198 @item -march=@var{architecture}[+@var{extension}@dots{}]
199 This option specifies the target architecture. The assembler will issue
200 an error message if an attempt is made to assemble an instruction which
201 will not execute on the target architecture. The following architecture
202 names are recognized:
238 If both @code{-mcpu} and
239 @code{-march} are specified, the assembler will use
240 the setting for @code{-mcpu}.
242 The architecture option can be extended with the same instruction set
243 extension options as the @code{-mcpu} option.
245 @cindex @code{-mfpu=} command line option, ARM
246 @item -mfpu=@var{floating-point-format}
248 This option specifies the floating point format to assemble for. The
249 assembler will issue an error message if an attempt is made to assemble
250 an instruction which will not execute on the target floating point unit.
251 The following format options are recognized:
271 @code{vfpv3-d16-fp16},
286 @code{neon-fp-armv8},
287 @code{crypto-neon-fp-armv8},
288 @code{neon-fp-armv8.1}
290 @code{crypto-neon-fp-armv8.1}.
292 In addition to determining which instructions are assembled, this option
293 also affects the way in which the @code{.double} assembler directive behaves
294 when assembling little-endian code.
296 The default is dependent on the processor selected. For Architecture 5 or
297 later, the default is to assembler for VFP instructions; for earlier
298 architectures the default is to assemble for FPA instructions.
300 @cindex @code{-mthumb} command line option, ARM
302 This option specifies that the assembler should start assembling Thumb
303 instructions; that is, it should behave as though the file starts with a
304 @code{.code 16} directive.
306 @cindex @code{-mthumb-interwork} command line option, ARM
307 @item -mthumb-interwork
308 This option specifies that the output generated by the assembler should
309 be marked as supporting interworking.
311 @cindex @code{-mimplicit-it} command line option, ARM
312 @item -mimplicit-it=never
313 @itemx -mimplicit-it=always
314 @itemx -mimplicit-it=arm
315 @itemx -mimplicit-it=thumb
316 The @code{-mimplicit-it} option controls the behavior of the assembler when
317 conditional instructions are not enclosed in IT blocks.
318 There are four possible behaviors.
319 If @code{never} is specified, such constructs cause a warning in ARM
320 code and an error in Thumb-2 code.
321 If @code{always} is specified, such constructs are accepted in both
322 ARM and Thumb-2 code, where the IT instruction is added implicitly.
323 If @code{arm} is specified, such constructs are accepted in ARM code
324 and cause an error in Thumb-2 code.
325 If @code{thumb} is specified, such constructs cause a warning in ARM
326 code and are accepted in Thumb-2 code. If you omit this option, the
327 behavior is equivalent to @code{-mimplicit-it=arm}.
329 @cindex @code{-mapcs-26} command line option, ARM
330 @cindex @code{-mapcs-32} command line option, ARM
333 These options specify that the output generated by the assembler should
334 be marked as supporting the indicated version of the Arm Procedure.
337 @cindex @code{-matpcs} command line option, ARM
339 This option specifies that the output generated by the assembler should
340 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
341 enabled this option will cause the assembler to create an empty
342 debugging section in the object file called .arm.atpcs. Debuggers can
343 use this to determine the ABI being used by.
345 @cindex @code{-mapcs-float} command line option, ARM
347 This indicates the floating point variant of the APCS should be
348 used. In this variant floating point arguments are passed in FP
349 registers rather than integer registers.
351 @cindex @code{-mapcs-reentrant} command line option, ARM
352 @item -mapcs-reentrant
353 This indicates that the reentrant variant of the APCS should be used.
354 This variant supports position independent code.
356 @cindex @code{-mfloat-abi=} command line option, ARM
357 @item -mfloat-abi=@var{abi}
358 This option specifies that the output generated by the assembler should be
359 marked as using specified floating point ABI.
360 The following values are recognized:
366 @cindex @code{-eabi=} command line option, ARM
367 @item -meabi=@var{ver}
368 This option specifies which EABI version the produced object files should
370 The following values are recognized:
376 @cindex @code{-EB} command line option, ARM
378 This option specifies that the output generated by the assembler should
379 be marked as being encoded for a big-endian processor.
381 Note: If a program is being built for a system with big-endian data
382 and little-endian instructions then it should be assembled with the
383 @option{-EB} option, (all of it, code and data) and then linked with
384 the @option{--be8} option. This will reverse the endianness of the
385 instructions back to little-endian, but leave the data as big-endian.
387 @cindex @code{-EL} command line option, ARM
389 This option specifies that the output generated by the assembler should
390 be marked as being encoded for a little-endian processor.
392 @cindex @code{-k} command line option, ARM
393 @cindex PIC code generation for ARM
395 This option specifies that the output of the assembler should be marked
396 as position-independent code (PIC).
398 @cindex @code{--fix-v4bx} command line option, ARM
400 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
401 the linker option of the same name.
403 @cindex @code{-mwarn-deprecated} command line option, ARM
404 @item -mwarn-deprecated
405 @itemx -mno-warn-deprecated
406 Enable or disable warnings about using deprecated options or
407 features. The default is to warn.
409 @cindex @code{-mccs} command line option, ARM
411 Turns on CodeComposer Studio assembly syntax compatibility mode.
413 @cindex @code{-mwarn-syms} command line option, ARM
415 @itemx -mno-warn-syms
416 Enable or disable warnings about symbols that match the names of ARM
417 instructions. The default is to warn.
425 * ARM-Instruction-Set:: Instruction Set
426 * ARM-Chars:: Special Characters
427 * ARM-Regs:: Register Names
428 * ARM-Relocations:: Relocations
429 * ARM-Neon-Alignment:: NEON Alignment Specifiers
432 @node ARM-Instruction-Set
433 @subsection Instruction Set Syntax
434 Two slightly different syntaxes are support for ARM and THUMB
435 instructions. The default, @code{divided}, uses the old style where
436 ARM and THUMB instructions had their own, separate syntaxes. The new,
437 @code{unified} syntax, which can be selected via the @code{.syntax}
438 directive, and has the following main features:
442 Immediate operands do not require a @code{#} prefix.
445 The @code{IT} instruction may appear, and if it does it is validated
446 against subsequent conditional affixes. In ARM mode it does not
447 generate machine code, in THUMB mode it does.
450 For ARM instructions the conditional affixes always appear at the end
451 of the instruction. For THUMB instructions conditional affixes can be
452 used, but only inside the scope of an @code{IT} instruction.
455 All of the instructions new to the V6T2 architecture (and later) are
456 available. (Only a few such instructions can be written in the
457 @code{divided} syntax).
460 The @code{.N} and @code{.W} suffixes are recognized and honored.
463 All instructions set the flags if and only if they have an @code{s}
468 @subsection Special Characters
470 @cindex line comment character, ARM
471 @cindex ARM line comment character
472 The presence of a @samp{@@} anywhere on a line indicates the start of
473 a comment that extends to the end of that line.
475 If a @samp{#} appears as the first character of a line then the whole
476 line is treated as a comment, but in this case the line could also be
477 a logical line number directive (@pxref{Comments}) or a preprocessor
478 control command (@pxref{Preprocessing}).
480 @cindex line separator, ARM
481 @cindex statement separator, ARM
482 @cindex ARM line separator
483 The @samp{;} character can be used instead of a newline to separate
486 @cindex immediate character, ARM
487 @cindex ARM immediate character
488 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
490 @cindex identifiers, ARM
491 @cindex ARM identifiers
492 *TODO* Explain about /data modifier on symbols.
495 @subsection Register Names
497 @cindex ARM register names
498 @cindex register names, ARM
499 *TODO* Explain about ARM register naming, and the predefined names.
501 @node ARM-Relocations
502 @subsection ARM relocation generation
504 @cindex data relocations, ARM
505 @cindex ARM data relocations
506 Specific data relocations can be generated by putting the relocation name
507 in parentheses after the symbol name. For example:
513 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
515 The following relocations are supported:
531 For compatibility with older toolchains the assembler also accepts
532 @code{(PLT)} after branch targets. On legacy targets this will
533 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
534 targets it will encode either the @samp{R_ARM_CALL} or
535 @samp{R_ARM_JUMP24} relocation, as appropriate.
537 @cindex MOVW and MOVT relocations, ARM
538 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
539 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
540 respectively. For example to load the 32-bit address of foo into r0:
543 MOVW r0, #:lower16:foo
544 MOVT r0, #:upper16:foo
547 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
548 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
549 generated by prefixing the value with @samp{#:lower0_7:#},
550 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
551 respectively. For example to load the 32-bit address of foo into r0:
554 MOVS r0, #:upper8_15:#foo
556 ADDS r0, #:upper0_7:#foo
558 ADDS r0, #:lower8_15:#foo
560 ADDS r0, #:lower0_7:#foo
563 @node ARM-Neon-Alignment
564 @subsection NEON Alignment Specifiers
566 @cindex alignment for NEON instructions
567 Some NEON load/store instructions allow an optional address
569 The ARM documentation specifies that this is indicated by
570 @samp{@@ @var{align}}. However GAS already interprets
571 the @samp{@@} character as a "line comment" start,
572 so @samp{: @var{align}} is used instead. For example:
575 vld1.8 @{q0@}, [r0, :128]
578 @node ARM Floating Point
579 @section Floating Point
581 @cindex floating point, ARM (@sc{ieee})
582 @cindex ARM floating point (@sc{ieee})
583 The ARM family uses @sc{ieee} floating-point numbers.
586 @section ARM Machine Directives
588 @cindex machine directives, ARM
589 @cindex ARM machine directives
592 @c AAAAAAAAAAAAAAAAAAAAAAAAA
594 @cindex @code{.2byte} directive, ARM
595 @cindex @code{.4byte} directive, ARM
596 @cindex @code{.8byte} directive, ARM
597 @item .2byte @var{expression} [, @var{expression}]*
598 @itemx .4byte @var{expression} [, @var{expression}]*
599 @itemx .8byte @var{expression} [, @var{expression}]*
600 These directives write 2, 4 or 8 byte values to the output section.
602 @cindex @code{.align} directive, ARM
603 @item .align @var{expression} [, @var{expression}]
604 This is the generic @var{.align} directive. For the ARM however if the
605 first argument is zero (ie no alignment is needed) the assembler will
606 behave as if the argument had been 2 (ie pad to the next four byte
607 boundary). This is for compatibility with ARM's own assembler.
609 @cindex @code{.arch} directive, ARM
610 @item .arch @var{name}
611 Select the target architecture. Valid values for @var{name} are the same as
612 for the @option{-march} commandline option.
614 Specifying @code{.arch} clears any previously selected architecture
617 @cindex @code{.arch_extension} directive, ARM
618 @item .arch_extension @var{name}
619 Add or remove an architecture extension to the target architecture. Valid
620 values for @var{name} are the same as those accepted as architectural
621 extensions by the @option{-mcpu} commandline option.
623 @code{.arch_extension} may be used multiple times to add or remove extensions
624 incrementally to the architecture being compiled for.
626 @cindex @code{.arm} directive, ARM
628 This performs the same action as @var{.code 32}.
630 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
632 @cindex @code{.bss} directive, ARM
634 This directive switches to the @code{.bss} section.
636 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
638 @cindex @code{.cantunwind} directive, ARM
640 Prevents unwinding through the current function. No personality routine
641 or exception table data is required or permitted.
643 @cindex @code{.code} directive, ARM
644 @item .code @code{[16|32]}
645 This directive selects the instruction set being generated. The value 16
646 selects Thumb, with the value 32 selecting ARM.
648 @cindex @code{.cpu} directive, ARM
649 @item .cpu @var{name}
650 Select the target processor. Valid values for @var{name} are the same as
651 for the @option{-mcpu} commandline option.
653 Specifying @code{.cpu} clears any previously selected architecture
656 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
658 @cindex @code{.dn} and @code{.qn} directives, ARM
659 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
660 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
662 The @code{dn} and @code{qn} directives are used to create typed
663 and/or indexed register aliases for use in Advanced SIMD Extension
664 (Neon) instructions. The former should be used to create aliases
665 of double-precision registers, and the latter to create aliases of
666 quad-precision registers.
668 If these directives are used to create typed aliases, those aliases can
669 be used in Neon instructions instead of writing types after the mnemonic
670 or after each operand. For example:
679 This is equivalent to writing the following:
685 Aliases created using @code{dn} or @code{qn} can be destroyed using
688 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
690 @cindex @code{.eabi_attribute} directive, ARM
691 @item .eabi_attribute @var{tag}, @var{value}
692 Set the EABI object attribute @var{tag} to @var{value}.
694 The @var{tag} is either an attribute number, or one of the following:
695 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
696 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
697 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
698 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
699 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
700 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
701 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
702 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
703 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
704 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
705 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
706 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
707 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
708 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
709 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
710 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
711 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
712 @code{Tag_conformance}, @code{Tag_T2EE_use},
713 @code{Tag_Virtualization_use}
715 The @var{value} is either a @code{number}, @code{"string"}, or
716 @code{number, "string"} depending on the tag.
718 Note - the following legacy values are also accepted by @var{tag}:
719 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
720 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
722 @cindex @code{.even} directive, ARM
724 This directive aligns to an even-numbered address.
726 @cindex @code{.extend} directive, ARM
727 @cindex @code{.ldouble} directive, ARM
728 @item .extend @var{expression} [, @var{expression}]*
729 @itemx .ldouble @var{expression} [, @var{expression}]*
730 These directives write 12byte long double floating-point values to the
731 output section. These are not compatible with current ARM processors
734 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
737 @cindex @code{.fnend} directive, ARM
739 Marks the end of a function with an unwind table entry. The unwind index
740 table entry is created when this directive is processed.
742 If no personality routine has been specified then standard personality
743 routine 0 or 1 will be used, depending on the number of unwind opcodes
747 @cindex @code{.fnstart} directive, ARM
749 Marks the start of a function with an unwind table entry.
751 @cindex @code{.force_thumb} directive, ARM
753 This directive forces the selection of Thumb instructions, even if the
754 target processor does not support those instructions
756 @cindex @code{.fpu} directive, ARM
757 @item .fpu @var{name}
758 Select the floating-point unit to assemble for. Valid values for @var{name}
759 are the same as for the @option{-mfpu} commandline option.
761 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
762 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
764 @cindex @code{.handlerdata} directive, ARM
766 Marks the end of the current function, and the start of the exception table
767 entry for that function. Anything between this directive and the
768 @code{.fnend} directive will be added to the exception table entry.
770 Must be preceded by a @code{.personality} or @code{.personalityindex}
773 @c IIIIIIIIIIIIIIIIIIIIIIIIII
775 @cindex @code{.inst} directive, ARM
776 @item .inst @var{opcode} [ , @dots{} ]
777 @itemx .inst.n @var{opcode} [ , @dots{} ]
778 @itemx .inst.w @var{opcode} [ , @dots{} ]
779 Generates the instruction corresponding to the numerical value @var{opcode}.
780 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
781 specified explicitly, overriding the normal encoding rules.
783 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
784 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
785 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
787 @item .ldouble @var{expression} [, @var{expression}]*
790 @cindex @code{.ltorg} directive, ARM
792 This directive causes the current contents of the literal pool to be
793 dumped into the current section (which is assumed to be the .text
794 section) at the current location (aligned to a word boundary).
795 @code{GAS} maintains a separate literal pool for each section and each
796 sub-section. The @code{.ltorg} directive will only affect the literal
797 pool of the current section and sub-section. At the end of assembly
798 all remaining, un-empty literal pools will automatically be dumped.
800 Note - older versions of @code{GAS} would dump the current literal
801 pool any time a section change occurred. This is no longer done, since
802 it prevents accurate control of the placement of literal pools.
804 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
806 @cindex @code{.movsp} directive, ARM
807 @item .movsp @var{reg} [, #@var{offset}]
808 Tell the unwinder that @var{reg} contains an offset from the current
809 stack pointer. If @var{offset} is not specified then it is assumed to be
812 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
813 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
815 @cindex @code{.object_arch} directive, ARM
816 @item .object_arch @var{name}
817 Override the architecture recorded in the EABI object attribute section.
818 Valid values for @var{name} are the same as for the @code{.arch} directive.
819 Typically this is useful when code uses runtime detection of CPU features.
821 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
823 @cindex @code{.packed} directive, ARM
824 @item .packed @var{expression} [, @var{expression}]*
825 This directive writes 12-byte packed floating-point values to the
826 output section. These are not compatible with current ARM processors
830 @cindex @code{.pad} directive, ARM
831 @item .pad #@var{count}
832 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
833 A positive value indicates the function prologue allocated stack space by
834 decrementing the stack pointer.
836 @cindex @code{.personality} directive, ARM
837 @item .personality @var{name}
838 Sets the personality routine for the current function to @var{name}.
840 @cindex @code{.personalityindex} directive, ARM
841 @item .personalityindex @var{index}
842 Sets the personality routine for the current function to the EABI standard
843 routine number @var{index}
845 @cindex @code{.pool} directive, ARM
847 This is a synonym for .ltorg.
849 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
850 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
852 @cindex @code{.req} directive, ARM
853 @item @var{name} .req @var{register name}
854 This creates an alias for @var{register name} called @var{name}. For
861 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
864 @cindex @code{.save} directive, ARM
865 @item .save @var{reglist}
866 Generate unwinder annotations to restore the registers in @var{reglist}.
867 The format of @var{reglist} is the same as the corresponding store-multiple
871 @exdent @emph{core registers}
872 .save @{r4, r5, r6, lr@}
873 stmfd sp!, @{r4, r5, r6, lr@}
874 @exdent @emph{FPA registers}
877 @exdent @emph{VFP registers}
878 .save @{d8, d9, d10@}
879 fstmdx sp!, @{d8, d9, d10@}
880 @exdent @emph{iWMMXt registers}
882 wstrd wr11, [sp, #-8]!
883 wstrd wr10, [sp, #-8]!
886 wstrd wr11, [sp, #-8]!
888 wstrd wr10, [sp, #-8]!
892 @cindex @code{.setfp} directive, ARM
893 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
894 Make all unwinder annotations relative to a frame pointer. Without this
895 the unwinder will use offsets from the stack pointer.
897 The syntax of this directive is the same as the @code{add} or @code{mov}
898 instruction used to set the frame pointer. @var{spreg} must be either
899 @code{sp} or mentioned in a previous @code{.movsp} directive.
909 @cindex @code{.secrel32} directive, ARM
910 @item .secrel32 @var{expression} [, @var{expression}]*
911 This directive emits relocations that evaluate to the section-relative
912 offset of each expression's symbol. This directive is only supported
915 @cindex @code{.syntax} directive, ARM
916 @item .syntax [@code{unified} | @code{divided}]
917 This directive sets the Instruction Set Syntax as described in the
918 @ref{ARM-Instruction-Set} section.
920 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
922 @cindex @code{.thumb} directive, ARM
924 This performs the same action as @var{.code 16}.
926 @cindex @code{.thumb_func} directive, ARM
928 This directive specifies that the following symbol is the name of a
929 Thumb encoded function. This information is necessary in order to allow
930 the assembler and linker to generate correct code for interworking
931 between Arm and Thumb instructions and should be used even if
932 interworking is not going to be performed. The presence of this
933 directive also implies @code{.thumb}
935 This directive is not neccessary when generating EABI objects. On these
936 targets the encoding is implicit when generating Thumb code.
938 @cindex @code{.thumb_set} directive, ARM
940 This performs the equivalent of a @code{.set} directive in that it
941 creates a symbol which is an alias for another symbol (possibly not yet
942 defined). This directive also has the added property in that it marks
943 the aliased symbol as being a thumb function entry point, in the same
944 way that the @code{.thumb_func} directive does.
946 @cindex @code{.tlsdescseq} directive, ARM
947 @item .tlsdescseq @var{tls-variable}
948 This directive is used to annotate parts of an inlined TLS descriptor
949 trampoline. Normally the trampoline is provided by the linker, and
950 this directive is not needed.
952 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
954 @cindex @code{.unreq} directive, ARM
955 @item .unreq @var{alias-name}
956 This undefines a register alias which was previously defined using the
957 @code{req}, @code{dn} or @code{qn} directives. For example:
964 An error occurs if the name is undefined. Note - this pseudo op can
965 be used to delete builtin in register name aliases (eg 'r0'). This
966 should only be done if it is really necessary.
968 @cindex @code{.unwind_raw} directive, ARM
969 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
970 Insert one of more arbitary unwind opcode bytes, which are known to adjust
971 the stack pointer by @var{offset} bytes.
973 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
976 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
978 @cindex @code{.vsave} directive, ARM
979 @item .vsave @var{vfp-reglist}
980 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
981 using FLDMD. Also works for VFPv3 registers
982 that are to be restored using VLDM.
983 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
987 @exdent @emph{VFP registers}
988 .vsave @{d8, d9, d10@}
989 fstmdd sp!, @{d8, d9, d10@}
990 @exdent @emph{VFPv3 registers}
991 .vsave @{d15, d16, d17@}
992 vstm sp!, @{d15, d16, d17@}
995 Since FLDMX and FSTMX are now deprecated, this directive should be
996 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
998 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
999 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1000 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1001 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1009 @cindex opcodes for ARM
1010 @code{@value{AS}} implements all the standard ARM opcodes. It also
1011 implements several pseudo opcodes, including several synthetic load
1016 @cindex @code{NOP} pseudo op, ARM
1022 This pseudo op will always evaluate to a legal ARM instruction that does
1023 nothing. Currently it will evaluate to MOV r0, r0.
1025 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1028 ldr <register> , = <expression>
1031 If expression evaluates to a numeric constant then a MOV or MVN
1032 instruction will be used in place of the LDR instruction, if the
1033 constant can be generated by either of these instructions. Otherwise
1034 the constant will be placed into the nearest literal pool (if it not
1035 already there) and a PC relative LDR instruction will be generated.
1037 @cindex @code{ADR reg,<label>} pseudo op, ARM
1040 adr <register> <label>
1043 This instruction will load the address of @var{label} into the indicated
1044 register. The instruction will evaluate to a PC relative ADD or SUB
1045 instruction depending upon where the label is located. If the label is
1046 out of range, or if it is not defined in the same file (and section) as
1047 the ADR instruction, then an error will be generated. This instruction
1048 will not make use of the literal pool.
1050 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1053 adrl <register> <label>
1056 This instruction will load the address of @var{label} into the indicated
1057 register. The instruction will evaluate to one or two PC relative ADD
1058 or SUB instructions depending upon where the label is located. If a
1059 second instruction is not needed a NOP instruction will be generated in
1060 its place, so that this instruction is always 8 bytes long.
1062 If the label is out of range, or if it is not defined in the same file
1063 (and section) as the ADRL instruction, then an error will be generated.
1064 This instruction will not make use of the literal pool.
1068 For information on the ARM or Thumb instruction sets, see @cite{ARM
1069 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1072 @node ARM Mapping Symbols
1073 @section Mapping Symbols
1075 The ARM ELF specification requires that special symbols be inserted
1076 into object files to mark certain features:
1082 At the start of a region of code containing ARM instructions.
1086 At the start of a region of code containing THUMB instructions.
1090 At the start of a region of data.
1094 The assembler will automatically insert these symbols for you - there
1095 is no need to code them yourself. Support for tagging symbols ($b,
1096 $f, $p and $m) which is also mentioned in the current ARM ELF
1097 specification is not implemented. This is because they have been
1098 dropped from the new EABI and so tools cannot rely upon their
1101 @node ARM Unwinding Tutorial
1104 The ABI for the ARM Architecture specifies a standard format for
1105 exception unwind information. This information is used when an
1106 exception is thrown to determine where control should be transferred.
1107 In particular, the unwind information is used to determine which
1108 function called the function that threw the exception, and which
1109 function called that one, and so forth. This information is also used
1110 to restore the values of callee-saved registers in the function
1111 catching the exception.
1113 If you are writing functions in assembly code, and those functions
1114 call other functions that throw exceptions, you must use assembly
1115 pseudo ops to ensure that appropriate exception unwind information is
1116 generated. Otherwise, if one of the functions called by your assembly
1117 code throws an exception, the run-time library will be unable to
1118 unwind the stack through your assembly code and your program will not
1121 To illustrate the use of these pseudo ops, we will examine the code
1122 that G++ generates for the following C++ input:
1125 void callee (int *);
1136 This example does not show how to throw or catch an exception from
1137 assembly code. That is a much more complex operation and should
1138 always be done in a high-level language, such as C++, that directly
1139 supports exceptions.
1141 The code generated by one particular version of G++ when compiling the
1148 @ Function supports interworking.
1149 @ args = 0, pretend = 0, frame = 8
1150 @ frame_needed = 1, uses_anonymous_args = 0
1172 Of course, the sequence of instructions varies based on the options
1173 you pass to GCC and on the version of GCC in use. The exact
1174 instructions are not important since we are focusing on the pseudo ops
1175 that are used to generate unwind information.
1177 An important assumption made by the unwinder is that the stack frame
1178 does not change during the body of the function. In particular, since
1179 we assume that the assembly code does not itself throw an exception,
1180 the only point where an exception can be thrown is from a call, such
1181 as the @code{bl} instruction above. At each call site, the same saved
1182 registers (including @code{lr}, which indicates the return address)
1183 must be located in the same locations relative to the frame pointer.
1185 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1186 op appears immediately before the first instruction of the function
1187 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1188 op appears immediately after the last instruction of the function.
1189 These pseudo ops specify the range of the function.
1191 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1192 @code{.pad}) matters; their exact locations are irrelevant. In the
1193 example above, the compiler emits the pseudo ops with particular
1194 instructions. That makes it easier to understand the code, but it is
1195 not required for correctness. It would work just as well to emit all
1196 of the pseudo ops other than @code{.fnend} in the same order, but
1197 immediately after @code{.fnstart}.
1199 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1200 indicates registers that have been saved to the stack so that they can
1201 be restored before the function returns. The argument to the
1202 @code{.save} pseudo op is a list of registers to save. If a register
1203 is ``callee-saved'' (as specified by the ABI) and is modified by the
1204 function you are writing, then your code must save the value before it
1205 is modified and restore the original value before the function
1206 returns. If an exception is thrown, the run-time library restores the
1207 values of these registers from their locations on the stack before
1208 returning control to the exception handler. (Of course, if an
1209 exception is not thrown, the function that contains the @code{.save}
1210 pseudo op restores these registers in the function epilogue, as is
1211 done with the @code{ldmfd} instruction above.)
1213 You do not have to save callee-saved registers at the very beginning
1214 of the function and you do not need to use the @code{.save} pseudo op
1215 immediately following the point at which the registers are saved.
1216 However, if you modify a callee-saved register, you must save it on
1217 the stack before modifying it and before calling any functions which
1218 might throw an exception. And, you must use the @code{.save} pseudo
1219 op to indicate that you have done so.
1221 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1222 modification of the stack pointer that does not save any registers.
1223 The argument is the number of bytes (in decimal) that are subtracted
1224 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1225 subtracting from the stack pointer increases the size of the stack.)
1227 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1228 indicates the register that contains the frame pointer. The first
1229 argument is the register that is set, which is typically @code{fp}.
1230 The second argument indicates the register from which the frame
1231 pointer takes its value. The third argument, if present, is the value
1232 (in decimal) added to the register specified by the second argument to
1233 compute the value of the frame pointer. You should not modify the
1234 frame pointer in the body of the function.
1236 If you do not use a frame pointer, then you should not use the
1237 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1238 should avoid modifying the stack pointer outside of the function
1239 prologue. Otherwise, the run-time library will be unable to find
1240 saved registers when it is unwinding the stack.
1242 The pseudo ops described above are sufficient for writing assembly
1243 code that calls functions which may throw exceptions. If you need to
1244 know more about the object-file format used to represent unwind
1245 information, you may consult the @cite{Exception Handling ABI for the
1246 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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