1 @c Copyright (C) 1996-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
139 @code{cortex-m0plus},
142 @code{marvell-whitney},
146 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
147 @code{i80200} (Intel XScale processor)
148 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
151 The special name @code{all} may be used to allow the
152 assembler to accept instructions valid for any ARM processor.
154 In addition to the basic instruction set, the assembler can be told to
155 accept various extension mnemonics that extend the processor using the
156 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
157 is equivalent to specifying @code{-mcpu=ep9312}.
159 Multiple extensions may be specified, separated by a @code{+}. The
160 extensions should be specified in ascending alphabetical order.
162 Some extensions may be restricted to particular architectures; this is
163 documented in the list of extensions below.
165 Extension mnemonics may also be removed from those the assembler accepts.
166 This is done be prepending @code{no} to the option that adds the extension.
167 Extensions that are removed should be listed after all extensions which have
168 been added, again in ascending alphabetical order. For example,
169 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
172 The following extensions are currently supported:
174 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
175 @code{fp} (Floating Point Extensions for v8-A architecture),
176 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
181 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
183 @code{os} (Operating System for v6M architecture),
184 @code{sec} (Security Extensions for v6K and v7-A architectures),
185 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
186 @code{virt} (Virtualization Extensions for v7-A architecture, implies
188 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
189 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
194 @cindex @code{-march=} command line option, ARM
195 @item -march=@var{architecture}[+@var{extension}@dots{}]
196 This option specifies the target architecture. The assembler will issue
197 an error message if an attempt is made to assemble an instruction which
198 will not execute on the target architecture. The following architecture
199 names are recognized:
235 If both @code{-mcpu} and
236 @code{-march} are specified, the assembler will use
237 the setting for @code{-mcpu}.
239 The architecture option can be extended with the same instruction set
240 extension options as the @code{-mcpu} option.
242 @cindex @code{-mfpu=} command line option, ARM
243 @item -mfpu=@var{floating-point-format}
245 This option specifies the floating point format to assemble for. The
246 assembler will issue an error message if an attempt is made to assemble
247 an instruction which will not execute on the target floating point unit.
248 The following format options are recognized:
268 @code{vfpv3-d16-fp16},
283 @code{neon-fp-armv8},
284 @code{crypto-neon-fp-armv8},
285 @code{neon-fp-armv8.1}
287 @code{crypto-neon-fp-armv8.1}.
289 In addition to determining which instructions are assembled, this option
290 also affects the way in which the @code{.double} assembler directive behaves
291 when assembling little-endian code.
293 The default is dependent on the processor selected. For Architecture 5 or
294 later, the default is to assembler for VFP instructions; for earlier
295 architectures the default is to assemble for FPA instructions.
297 @cindex @code{-mthumb} command line option, ARM
299 This option specifies that the assembler should start assembling Thumb
300 instructions; that is, it should behave as though the file starts with a
301 @code{.code 16} directive.
303 @cindex @code{-mthumb-interwork} command line option, ARM
304 @item -mthumb-interwork
305 This option specifies that the output generated by the assembler should
306 be marked as supporting interworking.
308 @cindex @code{-mimplicit-it} command line option, ARM
309 @item -mimplicit-it=never
310 @itemx -mimplicit-it=always
311 @itemx -mimplicit-it=arm
312 @itemx -mimplicit-it=thumb
313 The @code{-mimplicit-it} option controls the behavior of the assembler when
314 conditional instructions are not enclosed in IT blocks.
315 There are four possible behaviors.
316 If @code{never} is specified, such constructs cause a warning in ARM
317 code and an error in Thumb-2 code.
318 If @code{always} is specified, such constructs are accepted in both
319 ARM and Thumb-2 code, where the IT instruction is added implicitly.
320 If @code{arm} is specified, such constructs are accepted in ARM code
321 and cause an error in Thumb-2 code.
322 If @code{thumb} is specified, such constructs cause a warning in ARM
323 code and are accepted in Thumb-2 code. If you omit this option, the
324 behavior is equivalent to @code{-mimplicit-it=arm}.
326 @cindex @code{-mapcs-26} command line option, ARM
327 @cindex @code{-mapcs-32} command line option, ARM
330 These options specify that the output generated by the assembler should
331 be marked as supporting the indicated version of the Arm Procedure.
334 @cindex @code{-matpcs} command line option, ARM
336 This option specifies that the output generated by the assembler should
337 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
338 enabled this option will cause the assembler to create an empty
339 debugging section in the object file called .arm.atpcs. Debuggers can
340 use this to determine the ABI being used by.
342 @cindex @code{-mapcs-float} command line option, ARM
344 This indicates the floating point variant of the APCS should be
345 used. In this variant floating point arguments are passed in FP
346 registers rather than integer registers.
348 @cindex @code{-mapcs-reentrant} command line option, ARM
349 @item -mapcs-reentrant
350 This indicates that the reentrant variant of the APCS should be used.
351 This variant supports position independent code.
353 @cindex @code{-mfloat-abi=} command line option, ARM
354 @item -mfloat-abi=@var{abi}
355 This option specifies that the output generated by the assembler should be
356 marked as using specified floating point ABI.
357 The following values are recognized:
363 @cindex @code{-eabi=} command line option, ARM
364 @item -meabi=@var{ver}
365 This option specifies which EABI version the produced object files should
367 The following values are recognized:
373 @cindex @code{-EB} command line option, ARM
375 This option specifies that the output generated by the assembler should
376 be marked as being encoded for a big-endian processor.
378 Note: If a program is being built for a system with big-endian data
379 and little-endian instructions then it should be assembled with the
380 @option{-EB} option, (all of it, code and data) and then linked with
381 the @option{--be8} option. This will reverse the endianness of the
382 instructions back to little-endian, but leave the data as big-endian.
384 @cindex @code{-EL} command line option, ARM
386 This option specifies that the output generated by the assembler should
387 be marked as being encoded for a little-endian processor.
389 @cindex @code{-k} command line option, ARM
390 @cindex PIC code generation for ARM
392 This option specifies that the output of the assembler should be marked
393 as position-independent code (PIC).
395 @cindex @code{--fix-v4bx} command line option, ARM
397 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
398 the linker option of the same name.
400 @cindex @code{-mwarn-deprecated} command line option, ARM
401 @item -mwarn-deprecated
402 @itemx -mno-warn-deprecated
403 Enable or disable warnings about using deprecated options or
404 features. The default is to warn.
406 @cindex @code{-mccs} command line option, ARM
408 Turns on CodeComposer Studio assembly syntax compatibility mode.
410 @cindex @code{-mwarn-syms} command line option, ARM
412 @itemx -mno-warn-syms
413 Enable or disable warnings about symbols that match the names of ARM
414 instructions. The default is to warn.
422 * ARM-Instruction-Set:: Instruction Set
423 * ARM-Chars:: Special Characters
424 * ARM-Regs:: Register Names
425 * ARM-Relocations:: Relocations
426 * ARM-Neon-Alignment:: NEON Alignment Specifiers
429 @node ARM-Instruction-Set
430 @subsection Instruction Set Syntax
431 Two slightly different syntaxes are support for ARM and THUMB
432 instructions. The default, @code{divided}, uses the old style where
433 ARM and THUMB instructions had their own, separate syntaxes. The new,
434 @code{unified} syntax, which can be selected via the @code{.syntax}
435 directive, and has the following main features:
439 Immediate operands do not require a @code{#} prefix.
442 The @code{IT} instruction may appear, and if it does it is validated
443 against subsequent conditional affixes. In ARM mode it does not
444 generate machine code, in THUMB mode it does.
447 For ARM instructions the conditional affixes always appear at the end
448 of the instruction. For THUMB instructions conditional affixes can be
449 used, but only inside the scope of an @code{IT} instruction.
452 All of the instructions new to the V6T2 architecture (and later) are
453 available. (Only a few such instructions can be written in the
454 @code{divided} syntax).
457 The @code{.N} and @code{.W} suffixes are recognized and honored.
460 All instructions set the flags if and only if they have an @code{s}
465 @subsection Special Characters
467 @cindex line comment character, ARM
468 @cindex ARM line comment character
469 The presence of a @samp{@@} anywhere on a line indicates the start of
470 a comment that extends to the end of that line.
472 If a @samp{#} appears as the first character of a line then the whole
473 line is treated as a comment, but in this case the line could also be
474 a logical line number directive (@pxref{Comments}) or a preprocessor
475 control command (@pxref{Preprocessing}).
477 @cindex line separator, ARM
478 @cindex statement separator, ARM
479 @cindex ARM line separator
480 The @samp{;} character can be used instead of a newline to separate
483 @cindex immediate character, ARM
484 @cindex ARM immediate character
485 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
487 @cindex identifiers, ARM
488 @cindex ARM identifiers
489 *TODO* Explain about /data modifier on symbols.
492 @subsection Register Names
494 @cindex ARM register names
495 @cindex register names, ARM
496 *TODO* Explain about ARM register naming, and the predefined names.
498 @node ARM-Relocations
499 @subsection ARM relocation generation
501 @cindex data relocations, ARM
502 @cindex ARM data relocations
503 Specific data relocations can be generated by putting the relocation name
504 in parentheses after the symbol name. For example:
510 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
512 The following relocations are supported:
528 For compatibility with older toolchains the assembler also accepts
529 @code{(PLT)} after branch targets. On legacy targets this will
530 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
531 targets it will encode either the @samp{R_ARM_CALL} or
532 @samp{R_ARM_JUMP24} relocation, as appropriate.
534 @cindex MOVW and MOVT relocations, ARM
535 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
536 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
537 respectively. For example to load the 32-bit address of foo into r0:
540 MOVW r0, #:lower16:foo
541 MOVT r0, #:upper16:foo
544 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
545 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
546 generated by prefixing the value with @samp{#:lower0_7:#},
547 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
548 respectively. For example to load the 32-bit address of foo into r0:
551 MOVS r0, #:upper8_15:#foo
553 ADDS r0, #:upper0_7:#foo
555 ADDS r0, #:lower8_15:#foo
557 ADDS r0, #:lower0_7:#foo
560 @node ARM-Neon-Alignment
561 @subsection NEON Alignment Specifiers
563 @cindex alignment for NEON instructions
564 Some NEON load/store instructions allow an optional address
566 The ARM documentation specifies that this is indicated by
567 @samp{@@ @var{align}}. However GAS already interprets
568 the @samp{@@} character as a "line comment" start,
569 so @samp{: @var{align}} is used instead. For example:
572 vld1.8 @{q0@}, [r0, :128]
575 @node ARM Floating Point
576 @section Floating Point
578 @cindex floating point, ARM (@sc{ieee})
579 @cindex ARM floating point (@sc{ieee})
580 The ARM family uses @sc{ieee} floating-point numbers.
583 @section ARM Machine Directives
585 @cindex machine directives, ARM
586 @cindex ARM machine directives
589 @c AAAAAAAAAAAAAAAAAAAAAAAAA
591 @cindex @code{.2byte} directive, ARM
592 @cindex @code{.4byte} directive, ARM
593 @cindex @code{.8byte} directive, ARM
594 @item .2byte @var{expression} [, @var{expression}]*
595 @itemx .4byte @var{expression} [, @var{expression}]*
596 @itemx .8byte @var{expression} [, @var{expression}]*
597 These directives write 2, 4 or 8 byte values to the output section.
599 @cindex @code{.align} directive, ARM
600 @item .align @var{expression} [, @var{expression}]
601 This is the generic @var{.align} directive. For the ARM however if the
602 first argument is zero (ie no alignment is needed) the assembler will
603 behave as if the argument had been 2 (ie pad to the next four byte
604 boundary). This is for compatibility with ARM's own assembler.
606 @cindex @code{.arch} directive, ARM
607 @item .arch @var{name}
608 Select the target architecture. Valid values for @var{name} are the same as
609 for the @option{-march} commandline option.
611 Specifying @code{.arch} clears any previously selected architecture
614 @cindex @code{.arch_extension} directive, ARM
615 @item .arch_extension @var{name}
616 Add or remove an architecture extension to the target architecture. Valid
617 values for @var{name} are the same as those accepted as architectural
618 extensions by the @option{-mcpu} commandline option.
620 @code{.arch_extension} may be used multiple times to add or remove extensions
621 incrementally to the architecture being compiled for.
623 @cindex @code{.arm} directive, ARM
625 This performs the same action as @var{.code 32}.
627 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
629 @cindex @code{.bss} directive, ARM
631 This directive switches to the @code{.bss} section.
633 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
635 @cindex @code{.cantunwind} directive, ARM
637 Prevents unwinding through the current function. No personality routine
638 or exception table data is required or permitted.
640 @cindex @code{.code} directive, ARM
641 @item .code @code{[16|32]}
642 This directive selects the instruction set being generated. The value 16
643 selects Thumb, with the value 32 selecting ARM.
645 @cindex @code{.cpu} directive, ARM
646 @item .cpu @var{name}
647 Select the target processor. Valid values for @var{name} are the same as
648 for the @option{-mcpu} commandline option.
650 Specifying @code{.cpu} clears any previously selected architecture
653 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
655 @cindex @code{.dn} and @code{.qn} directives, ARM
656 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
657 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
659 The @code{dn} and @code{qn} directives are used to create typed
660 and/or indexed register aliases for use in Advanced SIMD Extension
661 (Neon) instructions. The former should be used to create aliases
662 of double-precision registers, and the latter to create aliases of
663 quad-precision registers.
665 If these directives are used to create typed aliases, those aliases can
666 be used in Neon instructions instead of writing types after the mnemonic
667 or after each operand. For example:
676 This is equivalent to writing the following:
682 Aliases created using @code{dn} or @code{qn} can be destroyed using
685 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
687 @cindex @code{.eabi_attribute} directive, ARM
688 @item .eabi_attribute @var{tag}, @var{value}
689 Set the EABI object attribute @var{tag} to @var{value}.
691 The @var{tag} is either an attribute number, or one of the following:
692 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
693 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
694 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
695 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
696 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
697 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
698 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
699 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
700 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
701 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
702 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
703 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
704 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
705 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
706 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
707 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
708 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
709 @code{Tag_conformance}, @code{Tag_T2EE_use},
710 @code{Tag_Virtualization_use}
712 The @var{value} is either a @code{number}, @code{"string"}, or
713 @code{number, "string"} depending on the tag.
715 Note - the following legacy values are also accepted by @var{tag}:
716 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
717 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
719 @cindex @code{.even} directive, ARM
721 This directive aligns to an even-numbered address.
723 @cindex @code{.extend} directive, ARM
724 @cindex @code{.ldouble} directive, ARM
725 @item .extend @var{expression} [, @var{expression}]*
726 @itemx .ldouble @var{expression} [, @var{expression}]*
727 These directives write 12byte long double floating-point values to the
728 output section. These are not compatible with current ARM processors
731 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
734 @cindex @code{.fnend} directive, ARM
736 Marks the end of a function with an unwind table entry. The unwind index
737 table entry is created when this directive is processed.
739 If no personality routine has been specified then standard personality
740 routine 0 or 1 will be used, depending on the number of unwind opcodes
744 @cindex @code{.fnstart} directive, ARM
746 Marks the start of a function with an unwind table entry.
748 @cindex @code{.force_thumb} directive, ARM
750 This directive forces the selection of Thumb instructions, even if the
751 target processor does not support those instructions
753 @cindex @code{.fpu} directive, ARM
754 @item .fpu @var{name}
755 Select the floating-point unit to assemble for. Valid values for @var{name}
756 are the same as for the @option{-mfpu} commandline option.
758 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
759 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
761 @cindex @code{.handlerdata} directive, ARM
763 Marks the end of the current function, and the start of the exception table
764 entry for that function. Anything between this directive and the
765 @code{.fnend} directive will be added to the exception table entry.
767 Must be preceded by a @code{.personality} or @code{.personalityindex}
770 @c IIIIIIIIIIIIIIIIIIIIIIIIII
772 @cindex @code{.inst} directive, ARM
773 @item .inst @var{opcode} [ , @dots{} ]
774 @itemx .inst.n @var{opcode} [ , @dots{} ]
775 @itemx .inst.w @var{opcode} [ , @dots{} ]
776 Generates the instruction corresponding to the numerical value @var{opcode}.
777 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
778 specified explicitly, overriding the normal encoding rules.
780 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
781 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
782 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
784 @item .ldouble @var{expression} [, @var{expression}]*
787 @cindex @code{.ltorg} directive, ARM
789 This directive causes the current contents of the literal pool to be
790 dumped into the current section (which is assumed to be the .text
791 section) at the current location (aligned to a word boundary).
792 @code{GAS} maintains a separate literal pool for each section and each
793 sub-section. The @code{.ltorg} directive will only affect the literal
794 pool of the current section and sub-section. At the end of assembly
795 all remaining, un-empty literal pools will automatically be dumped.
797 Note - older versions of @code{GAS} would dump the current literal
798 pool any time a section change occurred. This is no longer done, since
799 it prevents accurate control of the placement of literal pools.
801 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
803 @cindex @code{.movsp} directive, ARM
804 @item .movsp @var{reg} [, #@var{offset}]
805 Tell the unwinder that @var{reg} contains an offset from the current
806 stack pointer. If @var{offset} is not specified then it is assumed to be
809 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
810 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
812 @cindex @code{.object_arch} directive, ARM
813 @item .object_arch @var{name}
814 Override the architecture recorded in the EABI object attribute section.
815 Valid values for @var{name} are the same as for the @code{.arch} directive.
816 Typically this is useful when code uses runtime detection of CPU features.
818 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
820 @cindex @code{.packed} directive, ARM
821 @item .packed @var{expression} [, @var{expression}]*
822 This directive writes 12-byte packed floating-point values to the
823 output section. These are not compatible with current ARM processors
827 @cindex @code{.pad} directive, ARM
828 @item .pad #@var{count}
829 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
830 A positive value indicates the function prologue allocated stack space by
831 decrementing the stack pointer.
833 @cindex @code{.personality} directive, ARM
834 @item .personality @var{name}
835 Sets the personality routine for the current function to @var{name}.
837 @cindex @code{.personalityindex} directive, ARM
838 @item .personalityindex @var{index}
839 Sets the personality routine for the current function to the EABI standard
840 routine number @var{index}
842 @cindex @code{.pool} directive, ARM
844 This is a synonym for .ltorg.
846 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
847 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
849 @cindex @code{.req} directive, ARM
850 @item @var{name} .req @var{register name}
851 This creates an alias for @var{register name} called @var{name}. For
858 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
861 @cindex @code{.save} directive, ARM
862 @item .save @var{reglist}
863 Generate unwinder annotations to restore the registers in @var{reglist}.
864 The format of @var{reglist} is the same as the corresponding store-multiple
868 @exdent @emph{core registers}
869 .save @{r4, r5, r6, lr@}
870 stmfd sp!, @{r4, r5, r6, lr@}
871 @exdent @emph{FPA registers}
874 @exdent @emph{VFP registers}
875 .save @{d8, d9, d10@}
876 fstmdx sp!, @{d8, d9, d10@}
877 @exdent @emph{iWMMXt registers}
879 wstrd wr11, [sp, #-8]!
880 wstrd wr10, [sp, #-8]!
883 wstrd wr11, [sp, #-8]!
885 wstrd wr10, [sp, #-8]!
889 @cindex @code{.setfp} directive, ARM
890 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
891 Make all unwinder annotations relative to a frame pointer. Without this
892 the unwinder will use offsets from the stack pointer.
894 The syntax of this directive is the same as the @code{add} or @code{mov}
895 instruction used to set the frame pointer. @var{spreg} must be either
896 @code{sp} or mentioned in a previous @code{.movsp} directive.
906 @cindex @code{.secrel32} directive, ARM
907 @item .secrel32 @var{expression} [, @var{expression}]*
908 This directive emits relocations that evaluate to the section-relative
909 offset of each expression's symbol. This directive is only supported
912 @cindex @code{.syntax} directive, ARM
913 @item .syntax [@code{unified} | @code{divided}]
914 This directive sets the Instruction Set Syntax as described in the
915 @ref{ARM-Instruction-Set} section.
917 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
919 @cindex @code{.thumb} directive, ARM
921 This performs the same action as @var{.code 16}.
923 @cindex @code{.thumb_func} directive, ARM
925 This directive specifies that the following symbol is the name of a
926 Thumb encoded function. This information is necessary in order to allow
927 the assembler and linker to generate correct code for interworking
928 between Arm and Thumb instructions and should be used even if
929 interworking is not going to be performed. The presence of this
930 directive also implies @code{.thumb}
932 This directive is not neccessary when generating EABI objects. On these
933 targets the encoding is implicit when generating Thumb code.
935 @cindex @code{.thumb_set} directive, ARM
937 This performs the equivalent of a @code{.set} directive in that it
938 creates a symbol which is an alias for another symbol (possibly not yet
939 defined). This directive also has the added property in that it marks
940 the aliased symbol as being a thumb function entry point, in the same
941 way that the @code{.thumb_func} directive does.
943 @cindex @code{.tlsdescseq} directive, ARM
944 @item .tlsdescseq @var{tls-variable}
945 This directive is used to annotate parts of an inlined TLS descriptor
946 trampoline. Normally the trampoline is provided by the linker, and
947 this directive is not needed.
949 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
951 @cindex @code{.unreq} directive, ARM
952 @item .unreq @var{alias-name}
953 This undefines a register alias which was previously defined using the
954 @code{req}, @code{dn} or @code{qn} directives. For example:
961 An error occurs if the name is undefined. Note - this pseudo op can
962 be used to delete builtin in register name aliases (eg 'r0'). This
963 should only be done if it is really necessary.
965 @cindex @code{.unwind_raw} directive, ARM
966 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
967 Insert one of more arbitary unwind opcode bytes, which are known to adjust
968 the stack pointer by @var{offset} bytes.
970 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
973 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
975 @cindex @code{.vsave} directive, ARM
976 @item .vsave @var{vfp-reglist}
977 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
978 using FLDMD. Also works for VFPv3 registers
979 that are to be restored using VLDM.
980 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
984 @exdent @emph{VFP registers}
985 .vsave @{d8, d9, d10@}
986 fstmdd sp!, @{d8, d9, d10@}
987 @exdent @emph{VFPv3 registers}
988 .vsave @{d15, d16, d17@}
989 vstm sp!, @{d15, d16, d17@}
992 Since FLDMX and FSTMX are now deprecated, this directive should be
993 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
995 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
996 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
997 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
998 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1006 @cindex opcodes for ARM
1007 @code{@value{AS}} implements all the standard ARM opcodes. It also
1008 implements several pseudo opcodes, including several synthetic load
1013 @cindex @code{NOP} pseudo op, ARM
1019 This pseudo op will always evaluate to a legal ARM instruction that does
1020 nothing. Currently it will evaluate to MOV r0, r0.
1022 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1025 ldr <register> , = <expression>
1028 If expression evaluates to a numeric constant then a MOV or MVN
1029 instruction will be used in place of the LDR instruction, if the
1030 constant can be generated by either of these instructions. Otherwise
1031 the constant will be placed into the nearest literal pool (if it not
1032 already there) and a PC relative LDR instruction will be generated.
1034 @cindex @code{ADR reg,<label>} pseudo op, ARM
1037 adr <register> <label>
1040 This instruction will load the address of @var{label} into the indicated
1041 register. The instruction will evaluate to a PC relative ADD or SUB
1042 instruction depending upon where the label is located. If the label is
1043 out of range, or if it is not defined in the same file (and section) as
1044 the ADR instruction, then an error will be generated. This instruction
1045 will not make use of the literal pool.
1047 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1050 adrl <register> <label>
1053 This instruction will load the address of @var{label} into the indicated
1054 register. The instruction will evaluate to one or two PC relative ADD
1055 or SUB instructions depending upon where the label is located. If a
1056 second instruction is not needed a NOP instruction will be generated in
1057 its place, so that this instruction is always 8 bytes long.
1059 If the label is out of range, or if it is not defined in the same file
1060 (and section) as the ADRL instruction, then an error will be generated.
1061 This instruction will not make use of the literal pool.
1065 For information on the ARM or Thumb instruction sets, see @cite{ARM
1066 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1069 @node ARM Mapping Symbols
1070 @section Mapping Symbols
1072 The ARM ELF specification requires that special symbols be inserted
1073 into object files to mark certain features:
1079 At the start of a region of code containing ARM instructions.
1083 At the start of a region of code containing THUMB instructions.
1087 At the start of a region of data.
1091 The assembler will automatically insert these symbols for you - there
1092 is no need to code them yourself. Support for tagging symbols ($b,
1093 $f, $p and $m) which is also mentioned in the current ARM ELF
1094 specification is not implemented. This is because they have been
1095 dropped from the new EABI and so tools cannot rely upon their
1098 @node ARM Unwinding Tutorial
1101 The ABI for the ARM Architecture specifies a standard format for
1102 exception unwind information. This information is used when an
1103 exception is thrown to determine where control should be transferred.
1104 In particular, the unwind information is used to determine which
1105 function called the function that threw the exception, and which
1106 function called that one, and so forth. This information is also used
1107 to restore the values of callee-saved registers in the function
1108 catching the exception.
1110 If you are writing functions in assembly code, and those functions
1111 call other functions that throw exceptions, you must use assembly
1112 pseudo ops to ensure that appropriate exception unwind information is
1113 generated. Otherwise, if one of the functions called by your assembly
1114 code throws an exception, the run-time library will be unable to
1115 unwind the stack through your assembly code and your program will not
1118 To illustrate the use of these pseudo ops, we will examine the code
1119 that G++ generates for the following C++ input:
1122 void callee (int *);
1133 This example does not show how to throw or catch an exception from
1134 assembly code. That is a much more complex operation and should
1135 always be done in a high-level language, such as C++, that directly
1136 supports exceptions.
1138 The code generated by one particular version of G++ when compiling the
1145 @ Function supports interworking.
1146 @ args = 0, pretend = 0, frame = 8
1147 @ frame_needed = 1, uses_anonymous_args = 0
1169 Of course, the sequence of instructions varies based on the options
1170 you pass to GCC and on the version of GCC in use. The exact
1171 instructions are not important since we are focusing on the pseudo ops
1172 that are used to generate unwind information.
1174 An important assumption made by the unwinder is that the stack frame
1175 does not change during the body of the function. In particular, since
1176 we assume that the assembly code does not itself throw an exception,
1177 the only point where an exception can be thrown is from a call, such
1178 as the @code{bl} instruction above. At each call site, the same saved
1179 registers (including @code{lr}, which indicates the return address)
1180 must be located in the same locations relative to the frame pointer.
1182 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1183 op appears immediately before the first instruction of the function
1184 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1185 op appears immediately after the last instruction of the function.
1186 These pseudo ops specify the range of the function.
1188 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1189 @code{.pad}) matters; their exact locations are irrelevant. In the
1190 example above, the compiler emits the pseudo ops with particular
1191 instructions. That makes it easier to understand the code, but it is
1192 not required for correctness. It would work just as well to emit all
1193 of the pseudo ops other than @code{.fnend} in the same order, but
1194 immediately after @code{.fnstart}.
1196 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1197 indicates registers that have been saved to the stack so that they can
1198 be restored before the function returns. The argument to the
1199 @code{.save} pseudo op is a list of registers to save. If a register
1200 is ``callee-saved'' (as specified by the ABI) and is modified by the
1201 function you are writing, then your code must save the value before it
1202 is modified and restore the original value before the function
1203 returns. If an exception is thrown, the run-time library restores the
1204 values of these registers from their locations on the stack before
1205 returning control to the exception handler. (Of course, if an
1206 exception is not thrown, the function that contains the @code{.save}
1207 pseudo op restores these registers in the function epilogue, as is
1208 done with the @code{ldmfd} instruction above.)
1210 You do not have to save callee-saved registers at the very beginning
1211 of the function and you do not need to use the @code{.save} pseudo op
1212 immediately following the point at which the registers are saved.
1213 However, if you modify a callee-saved register, you must save it on
1214 the stack before modifying it and before calling any functions which
1215 might throw an exception. And, you must use the @code{.save} pseudo
1216 op to indicate that you have done so.
1218 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1219 modification of the stack pointer that does not save any registers.
1220 The argument is the number of bytes (in decimal) that are subtracted
1221 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1222 subtracting from the stack pointer increases the size of the stack.)
1224 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1225 indicates the register that contains the frame pointer. The first
1226 argument is the register that is set, which is typically @code{fp}.
1227 The second argument indicates the register from which the frame
1228 pointer takes its value. The third argument, if present, is the value
1229 (in decimal) added to the register specified by the second argument to
1230 compute the value of the frame pointer. You should not modify the
1231 frame pointer in the body of the function.
1233 If you do not use a frame pointer, then you should not use the
1234 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1235 should avoid modifying the stack pointer outside of the function
1236 prologue. Otherwise, the run-time library will be unable to find
1237 saved registers when it is unwinding the stack.
1239 The pseudo ops described above are sufficient for writing assembly
1240 code that calls functions which may throw exceptions. If you need to
1241 know more about the object-file format used to represent unwind
1242 information, you may consult the @cite{Exception Handling ABI for the
1243 ARM Architecture} available from @uref{http://infocenter.arm.com}.
projects / deliverable / binutils-gdb.git / blob