gas/doc/c-arm.texi

   1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5
   6 @ifset GENERIC
   7 @page
   8 @node ARM-Dependent
   9 @chapter ARM Dependent Features
  10 @end ifset
  11
  12 @ifclear GENERIC
  13 @node Machine Dependencies
  14 @chapter ARM Dependent Features
  15 @end ifclear
  16
  17 @cindex ARM support
  18 @cindex Thumb support
  19 @menu
  20 * ARM Options::              Options
  21 * ARM Syntax::               Syntax
  22 * ARM Floating Point::       Floating Point
  23 * ARM Directives::           ARM Machine Directives
  24 * ARM Opcodes::              Opcodes
  25 * ARM Mapping Symbols::      Mapping Symbols
  26 @end menu
  27
  28 @node ARM Options
  29 @section Options
  30 @cindex ARM options (none)
  31 @cindex options for ARM (none)
  32
  33 @table @code
  34
  35 @cindex @code{-mcpu=} command line option, ARM
  36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  37 This option specifies the target processor.  The assembler will issue an
  38 error message if an attempt is made to assemble an instruction which
  39 will not execute on the target processor.  The following processor names are
  40 recognized:
  41 @code{arm1},
  42 @code{arm2},
  43 @code{arm250},
  44 @code{arm3},
  45 @code{arm6},
  46 @code{arm60},
  47 @code{arm600},
  48 @code{arm610},
  49 @code{arm620},
  50 @code{arm7},
  51 @code{arm7m},
  52 @code{arm7d},
  53 @code{arm7dm},
  54 @code{arm7di},
  55 @code{arm7dmi},
  56 @code{arm70},
  57 @code{arm700},
  58 @code{arm700i},
  59 @code{arm710},
  60 @code{arm710t},
  61 @code{arm720},
  62 @code{arm720t},
  63 @code{arm740t},
  64 @code{arm710c},
  65 @code{arm7100},
  66 @code{arm7500},
  67 @code{arm7500fe},
  68 @code{arm7t},
  69 @code{arm7tdmi},
  70 @code{arm8},
  71 @code{arm810},
  72 @code{strongarm},
  73 @code{strongarm1},
  74 @code{strongarm110},
  75 @code{strongarm1100},
  76 @code{strongarm1110},
  77 @code{arm9},
  78 @code{arm920},
  79 @code{arm920t},
  80 @code{arm922t},
  81 @code{arm940t},
  82 @code{arm9tdmi},
  83 @code{arm9e},
  84 @code{arm946e-r0},
  85 @code{arm946e},
  86 @code{arm966e-r0},
  87 @code{arm966e},
  88 @code{arm10t},
  89 @code{arm10e},
  90 @code{arm1020},
  91 @code{arm1020t},
  92 @code{arm1020e},
  93 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
  94 @code{i80200} (Intel XScale processor)
  95 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
  96 and
  97 @code{xscale}.
  98 The special name @code{all} may be used to allow the
  99 assembler to accept instructions valid for any ARM processor.
 100
 101 In addition to the basic instruction set, the assembler can be told to
 102 accept various extension mnemonics that extend the processor using the
 103 co-processor instruction space.  For example, @code{-mcpu=arm920+maverick}
 104 is equivalent to specifying @code{-mcpu=ep9312}.  The following extensions
 105 are currently supported:
 106 @code{+maverick}
 107 @code{+iwmmxt}
 108 and
 109 @code{+xscale}.
 110
 111 @cindex @code{-march=} command line option, ARM
 112 @item -march=@var{architecture}[+@var{extension}@dots{}]
 113 This option specifies the target architecture.  The assembler will issue
 114 an error message if an attempt is made to assemble an instruction which
 115 will not execute on the target architecture.  The following architecture
 116 names are recognized:
 117 @code{armv1},
 118 @code{armv2},
 119 @code{armv2a},
 120 @code{armv2s},
 121 @code{armv3},
 122 @code{armv3m},
 123 @code{armv4},
 124 @code{armv4xm},
 125 @code{armv4t},
 126 @code{armv4txm},
 127 @code{armv5},
 128 @code{armv5t},
 129 @code{armv5txm},
 130 @code{armv5te},
 131 @code{armv5texp}
 132 @code{iwmmxt}
 133 and
 134 @code{xscale}.
 135 If both @code{-mcpu} and
 136 @code{-march} are specified, the assembler will use
 137 the setting for @code{-mcpu}.
 138
 139 The architecture option can be extended with the same instruction set
 140 extension options as the @code{-mcpu} option.
 141
 142 @cindex @code{-mfpu=} command line option, ARM
 143 @item -mfpu=@var{floating-point-format}
 144
 145 This option specifies the floating point format to assemble for.  The
 146 assembler will issue an error message if an attempt is made to assemble
 147 an instruction which will not execute on the target floating point unit.
 148 The following format options are recognized:
 149 @code{softfpa},
 150 @code{fpe},
 151 @code{fpe2},
 152 @code{fpe3},
 153 @code{fpa},
 154 @code{fpa10},
 155 @code{fpa11},
 156 @code{arm7500fe},
 157 @code{softvfp},
 158 @code{softvfp+vfp},
 159 @code{vfp},
 160 @code{vfp10},
 161 @code{vfp10-r0},
 162 @code{vfp9},
 163 @code{vfpxd},
 164 @code{arm1020t}
 165 and
 166 @code{arm1020e}.
 167
 168 In addition to determining which instructions are assembled, this option
 169 also affects the way in which the @code{.double} assembler directive behaves
 170 when assembling little-endian code.
 171
 172 The default is dependent on the processor selected.  For Architecture 5 or
 173 later, the default is to assembler for VFP instructions; for earlier
 174 architectures the default is to assemble for FPA instructions.
 175
 176 @cindex @code{-mthumb} command line option, ARM
 177 @item -mthumb
 178 This option specifies that the assembler should start assembling Thumb
 179 instructions; that is, it should behave as though the file starts with a
 180 @code{.code 16} directive.
 181
 182 @cindex @code{-mthumb-interwork} command line option, ARM
 183 @item -mthumb-interwork
 184 This option specifies that the output generated by the assembler should
 185 be marked as supporting interworking.
 186
 187 @cindex @code{-mapcs} command line option, ARM
 188 @item -mapcs @code{[26|32]}
 189 This option specifies that the output generated by the assembler should
 190 be marked as supporting the indicated version of the Arm Procedure.
 191 Calling Standard.
 192
 193 @cindex @code{-matpcs} command line option, ARM
 194 @item -matpcs
 195 This option specifies that the output generated by the assembler should
 196 be marked as supporting the Arm/Thumb Procedure Calling Standard.  If
 197 enabled this option will cause the assembler to create an empty
 198 debugging section in the object file called .arm.atpcs.  Debuggers can
 199 use this to determine the ABI being used by.
 200
 201 @cindex @code{-mapcs-float} command line option, ARM
 202 @item -mapcs-float
 203 This indicates the floating point variant of the APCS should be
 204 used.  In this variant floating point arguments are passed in FP
 205 registers rather than integer registers.
 206
 207 @cindex @code{-mapcs-reentrant} command line option, ARM
 208 @item -mapcs-reentrant
 209 This indicates that the reentrant variant of the APCS should be used.
 210 This variant supports position independent code.
 211
 212 @cindex @code{-EB} command line option, ARM
 213 @item -EB
 214 This option specifies that the output generated by the assembler should
 215 be marked as being encoded for a big-endian processor.
 216
 217 @cindex @code{-EL} command line option, ARM
 218 @item -EL
 219 This option specifies that the output generated by the assembler should
 220 be marked as being encoded for a little-endian processor.
 221
 222 @cindex @code{-k} command line option, ARM
 223 @cindex PIC code generation for ARM
 224 @item -k
 225 This option specifies that the output of the assembler should be marked
 226 as position-independent code (PIC).
 227
 228 @cindex @code{-moabi} command line option, ARM
 229 @item -moabi
 230 This indicates that the code should be assembled using the old ARM ELF
 231 conventions, based on a beta release release of the ARM-ELF
 232 specifications, rather than the default conventions which are based on
 233 the final release of the ARM-ELF specifications.
 234
 235 @end table
 236
 237
 238 @node ARM Syntax
 239 @section Syntax
 240 @menu
 241 * ARM-Chars::                Special Characters
 242 * ARM-Regs::                 Register Names
 243 @end menu
 244
 245 @node ARM-Chars
 246 @subsection Special Characters
 247
 248 @cindex line comment character, ARM
 249 @cindex ARM line comment character
 250 The presence of a @samp{@@} on a line indicates the start of a comment
 251 that extends to the end of the current line.  If a @samp{#} appears as
 252 the first character of a line, the whole line is treated as a comment.
 253
 254 @cindex line separator, ARM
 255 @cindex statement separator, ARM
 256 @cindex ARM line separator
 257 The @samp{;} character can be used instead of a newline to separate
 258 statements.
 259
 260 @cindex immediate character, ARM
 261 @cindex ARM immediate character
 262 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 263
 264 @cindex identifiers, ARM
 265 @cindex ARM identifiers
 266 *TODO* Explain about /data modifier on symbols.
 267
 268 @node ARM-Regs
 269 @subsection Register Names
 270
 271 @cindex ARM register names
 272 @cindex register names, ARM
 273 *TODO* Explain about ARM register naming, and the predefined names.
 274
 275 @node ARM Floating Point
 276 @section Floating Point
 277
 278 @cindex floating point, ARM (@sc{ieee})
 279 @cindex ARM floating point (@sc{ieee})
 280 The ARM family uses @sc{ieee} floating-point numbers.
 281
 282
 283
 284 @node ARM Directives
 285 @section ARM Machine Directives
 286
 287 @cindex machine directives, ARM
 288 @cindex ARM machine directives
 289 @table @code
 290
 291 @cindex @code{align} directive, ARM
 292 @item .align @var{expression} [, @var{expression}]
 293 This is the generic @var{.align} directive.  For the ARM however if the
 294 first argument is zero (ie no alignment is needed) the assembler will
 295 behave as if the argument had been 2 (ie pad to the next four byte
 296 boundary).  This is for compatibility with ARM's own assembler.
 297
 298 @cindex @code{req} directive, ARM
 299 @item @var{name} .req @var{register name}
 300 This creates an alias for @var{register name} called @var{name}.  For
 301 example:
 302
 303 @smallexample
 304         foo .req r0
 305 @end smallexample
 306
 307 @cindex @code{unreq} directive, ARM
 308 @item .unreq @var{alias-name}
 309 This undefines a register alias which was previously defined using the
 310 @code{req} directive.  For example:
 311
 312 @smallexample
 313         foo .req r0
 314         .unreq foo
 315 @end smallexample
 316
 317 An error occurs if the name is undefined.  Note - this pseudo op can
 318 be used to delete builtin in register name aliases (eg 'r0').  This
 319 should only be done if it is really necessary.
 320
 321 @cindex @code{code} directive, ARM
 322 @item .code @code{[16|32]}
 323 This directive selects the instruction set being generated. The value 16
 324 selects Thumb, with the value 32 selecting ARM.
 325
 326 @cindex @code{thumb} directive, ARM
 327 @item .thumb
 328 This performs the same action as @var{.code 16}.
 329
 330 @cindex @code{arm} directive, ARM
 331 @item .arm
 332 This performs the same action as @var{.code 32}.
 333
 334 @cindex @code{force_thumb} directive, ARM
 335 @item .force_thumb
 336 This directive forces the selection of Thumb instructions, even if the
 337 target processor does not support those instructions
 338
 339 @cindex @code{thumb_func} directive, ARM
 340 @item .thumb_func
 341 This directive specifies that the following symbol is the name of a
 342 Thumb encoded function.  This information is necessary in order to allow
 343 the assembler and linker to generate correct code for interworking
 344 between Arm and Thumb instructions and should be used even if
 345 interworking is not going to be performed.  The presence of this
 346 directive also implies @code{.thumb}
 347
 348 @cindex @code{thumb_set} directive, ARM
 349 @item .thumb_set
 350 This performs the equivalent of a @code{.set} directive in that it
 351 creates a symbol which is an alias for another symbol (possibly not yet
 352 defined).  This directive also has the added property in that it marks
 353 the aliased symbol as being a thumb function entry point, in the same
 354 way that the @code{.thumb_func} directive does.
 355
 356 @cindex @code{.ltorg} directive, ARM
 357 @item .ltorg
 358 This directive causes the current contents of the literal pool to be
 359 dumped into the current section (which is assumed to be the .text
 360 section) at the current location (aligned to a word boundary).
 361 @code{GAS} maintains a separate literal pool for each section and each
 362 sub-section.  The @code{.ltorg} directive will only affect the literal
 363 pool of the current section and sub-section.  At the end of assembly
 364 all remaining, un-empty literal pools will automatically be dumped.
 365
 366 Note - older versions of @code{GAS} would dump the current literal
 367 pool any time a section change occurred.  This is no longer done, since
 368 it prevents accurate control of the placement of literal pools.
 369
 370 @cindex @code{.pool} directive, ARM
 371 @item .pool
 372 This is a synonym for .ltorg.
 373
 374 @end table
 375
 376 @node ARM Opcodes
 377 @section Opcodes
 378
 379 @cindex ARM opcodes
 380 @cindex opcodes for ARM
 381 @code{@value{AS}} implements all the standard ARM opcodes.  It also
 382 implements several pseudo opcodes, including several synthetic load
 383 instructions.
 384
 385 @table @code
 386
 387 @cindex @code{NOP} pseudo op, ARM
 388 @item NOP
 389 @smallexample
 390   nop
 391 @end smallexample
 392
 393 This pseudo op will always evaluate to a legal ARM instruction that does
 394 nothing.  Currently it will evaluate to MOV r0, r0.
 395
 396 @cindex @code{LDR reg,=<label>} pseudo op, ARM
 397 @item LDR
 398 @smallexample
 399   ldr <register> , = <expression>
 400 @end smallexample
 401
 402 If expression evaluates to a numeric constant then a MOV or MVN
 403 instruction will be used in place of the LDR instruction, if the
 404 constant can be generated by either of these instructions.  Otherwise
 405 the constant will be placed into the nearest literal pool (if it not
 406 already there) and a PC relative LDR instruction will be generated.
 407
 408 @cindex @code{ADR reg,<label>} pseudo op, ARM
 409 @item ADR
 410 @smallexample
 411   adr <register> <label>
 412 @end smallexample
 413
 414 This instruction will load the address of @var{label} into the indicated
 415 register.  The instruction will evaluate to a PC relative ADD or SUB
 416 instruction depending upon where the label is located.  If the label is
 417 out of range, or if it is not defined in the same file (and section) as
 418 the ADR instruction, then an error will be generated.  This instruction
 419 will not make use of the literal pool.
 420
 421 @cindex @code{ADRL reg,<label>} pseudo op, ARM
 422 @item ADRL
 423 @smallexample
 424   adrl <register> <label>
 425 @end smallexample
 426
 427 This instruction will load the address of @var{label} into the indicated
 428 register.  The instruction will evaluate to one or two PC relative ADD
 429 or SUB instructions depending upon where the label is located.  If a
 430 second instruction is not needed a NOP instruction will be generated in
 431 its place, so that this instruction is always 8 bytes long.
 432
 433 If the label is out of range, or if it is not defined in the same file
 434 (and section) as the ADRL instruction, then an error will be generated.
 435 This instruction will not make use of the literal pool.
 436
 437 @end table
 438
 439 For information on the ARM or Thumb instruction sets, see @cite{ARM
 440 Software Development Toolkit Reference Manual}, Advanced RISC Machines
 441 Ltd.
 442
 443 @node ARM Mapping Symbols
 444 @section Mapping Symbols
 445
 446 The ARM ELF specification requires that special symbols be inserted
 447 into object files to mark certain features:
 448
 449 @table @code
 450
 451 @cindex @code{$a}
 452 @item $a
 453 At the start of a region of code containing ARM instructions.
 454
 455 @cindex @code{$t}
 456 @item $t
 457 At the start of a region of code containing THUMB instructions.
 458
 459 @cindex @code{$d}
 460 @item $d
 461 At the start of a region of data.
 462
 463 @end table
 464
 465 The assembler will automatically insert these symbols for you - there
 466 is no need to code them yourself.  Support for tagging symbols ($b,
 467 $f, $p and $m) which is also mentioned in the current ARM ELF
 468 specification is not implemented.  This is because they have been
 469 dropped from the new EABI and so tools cannot rely upon their
 470 presence.
 471