1 @c Copyright (C) 1996-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
137 @code{cortex-m0plus},
140 @code{marvell-whitney},
144 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
145 @code{i80200} (Intel XScale processor)
146 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
149 The special name @code{all} may be used to allow the
150 assembler to accept instructions valid for any ARM processor.
152 In addition to the basic instruction set, the assembler can be told to
153 accept various extension mnemonics that extend the processor using the
154 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
155 is equivalent to specifying @code{-mcpu=ep9312}.
157 Multiple extensions may be specified, separated by a @code{+}. The
158 extensions should be specified in ascending alphabetical order.
160 Some extensions may be restricted to particular architectures; this is
161 documented in the list of extensions below.
163 Extension mnemonics may also be removed from those the assembler accepts.
164 This is done be prepending @code{no} to the option that adds the extension.
165 Extensions that are removed should be listed after all extensions which have
166 been added, again in ascending alphabetical order. For example,
167 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
170 The following extensions are currently supported:
172 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
173 @code{fp} (Floating Point Extensions for v8-A architecture),
174 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
179 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
181 @code{os} (Operating System for v6M architecture),
182 @code{sec} (Security Extensions for v6K and v7-A architectures),
183 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
184 @code{virt} (Virtualization Extensions for v7-A architecture, implies
186 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
187 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
192 @cindex @code{-march=} command line option, ARM
193 @item -march=@var{architecture}[+@var{extension}@dots{}]
194 This option specifies the target architecture. The assembler will issue
195 an error message if an attempt is made to assemble an instruction which
196 will not execute on the target architecture. The following architecture
197 names are recognized:
233 If both @code{-mcpu} and
234 @code{-march} are specified, the assembler will use
235 the setting for @code{-mcpu}.
237 The architecture option can be extended with the same instruction set
238 extension options as the @code{-mcpu} option.
240 @cindex @code{-mfpu=} command line option, ARM
241 @item -mfpu=@var{floating-point-format}
243 This option specifies the floating point format to assemble for. The
244 assembler will issue an error message if an attempt is made to assemble
245 an instruction which will not execute on the target floating point unit.
246 The following format options are recognized:
266 @code{vfpv3-d16-fp16},
281 @code{neon-fp-armv8},
282 @code{crypto-neon-fp-armv8},
283 @code{neon-fp-armv8.1}
285 @code{crypto-neon-fp-armv8.1}.
287 In addition to determining which instructions are assembled, this option
288 also affects the way in which the @code{.double} assembler directive behaves
289 when assembling little-endian code.
291 The default is dependent on the processor selected. For Architecture 5 or
292 later, the default is to assembler for VFP instructions; for earlier
293 architectures the default is to assemble for FPA instructions.
295 @cindex @code{-mthumb} command line option, ARM
297 This option specifies that the assembler should start assembling Thumb
298 instructions; that is, it should behave as though the file starts with a
299 @code{.code 16} directive.
301 @cindex @code{-mthumb-interwork} command line option, ARM
302 @item -mthumb-interwork
303 This option specifies that the output generated by the assembler should
304 be marked as supporting interworking.
306 @cindex @code{-mimplicit-it} command line option, ARM
307 @item -mimplicit-it=never
308 @itemx -mimplicit-it=always
309 @itemx -mimplicit-it=arm
310 @itemx -mimplicit-it=thumb
311 The @code{-mimplicit-it} option controls the behavior of the assembler when
312 conditional instructions are not enclosed in IT blocks.
313 There are four possible behaviors.
314 If @code{never} is specified, such constructs cause a warning in ARM
315 code and an error in Thumb-2 code.
316 If @code{always} is specified, such constructs are accepted in both
317 ARM and Thumb-2 code, where the IT instruction is added implicitly.
318 If @code{arm} is specified, such constructs are accepted in ARM code
319 and cause an error in Thumb-2 code.
320 If @code{thumb} is specified, such constructs cause a warning in ARM
321 code and are accepted in Thumb-2 code. If you omit this option, the
322 behavior is equivalent to @code{-mimplicit-it=arm}.
324 @cindex @code{-mapcs-26} command line option, ARM
325 @cindex @code{-mapcs-32} command line option, ARM
328 These options specify that the output generated by the assembler should
329 be marked as supporting the indicated version of the Arm Procedure.
332 @cindex @code{-matpcs} command line option, ARM
334 This option specifies that the output generated by the assembler should
335 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
336 enabled this option will cause the assembler to create an empty
337 debugging section in the object file called .arm.atpcs. Debuggers can
338 use this to determine the ABI being used by.
340 @cindex @code{-mapcs-float} command line option, ARM
342 This indicates the floating point variant of the APCS should be
343 used. In this variant floating point arguments are passed in FP
344 registers rather than integer registers.
346 @cindex @code{-mapcs-reentrant} command line option, ARM
347 @item -mapcs-reentrant
348 This indicates that the reentrant variant of the APCS should be used.
349 This variant supports position independent code.
351 @cindex @code{-mfloat-abi=} command line option, ARM
352 @item -mfloat-abi=@var{abi}
353 This option specifies that the output generated by the assembler should be
354 marked as using specified floating point ABI.
355 The following values are recognized:
361 @cindex @code{-eabi=} command line option, ARM
362 @item -meabi=@var{ver}
363 This option specifies which EABI version the produced object files should
365 The following values are recognized:
371 @cindex @code{-EB} command line option, ARM
373 This option specifies that the output generated by the assembler should
374 be marked as being encoded for a big-endian processor.
376 Note: If a program is being built for a system with big-endian data
377 and little-endian instructions then it should be assembled with the
378 @option{-EB} option, (all of it, code and data) and then linked with
379 the @option{--be8} option. This will reverse the endianness of the
380 instructions back to little-endian, but leave the data as big-endian.
382 @cindex @code{-EL} command line option, ARM
384 This option specifies that the output generated by the assembler should
385 be marked as being encoded for a little-endian processor.
387 @cindex @code{-k} command line option, ARM
388 @cindex PIC code generation for ARM
390 This option specifies that the output of the assembler should be marked
391 as position-independent code (PIC).
393 @cindex @code{--fix-v4bx} command line option, ARM
395 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
396 the linker option of the same name.
398 @cindex @code{-mwarn-deprecated} command line option, ARM
399 @item -mwarn-deprecated
400 @itemx -mno-warn-deprecated
401 Enable or disable warnings about using deprecated options or
402 features. The default is to warn.
404 @cindex @code{-mccs} command line option, ARM
406 Turns on CodeComposer Studio assembly syntax compatibility mode.
408 @cindex @code{-mwarn-syms} command line option, ARM
410 @itemx -mno-warn-syms
411 Enable or disable warnings about symbols that match the names of ARM
412 instructions. The default is to warn.
420 * ARM-Instruction-Set:: Instruction Set
421 * ARM-Chars:: Special Characters
422 * ARM-Regs:: Register Names
423 * ARM-Relocations:: Relocations
424 * ARM-Neon-Alignment:: NEON Alignment Specifiers
427 @node ARM-Instruction-Set
428 @subsection Instruction Set Syntax
429 Two slightly different syntaxes are support for ARM and THUMB
430 instructions. The default, @code{divided}, uses the old style where
431 ARM and THUMB instructions had their own, separate syntaxes. The new,
432 @code{unified} syntax, which can be selected via the @code{.syntax}
433 directive, and has the following main features:
437 Immediate operands do not require a @code{#} prefix.
440 The @code{IT} instruction may appear, and if it does it is validated
441 against subsequent conditional affixes. In ARM mode it does not
442 generate machine code, in THUMB mode it does.
445 For ARM instructions the conditional affixes always appear at the end
446 of the instruction. For THUMB instructions conditional affixes can be
447 used, but only inside the scope of an @code{IT} instruction.
450 All of the instructions new to the V6T2 architecture (and later) are
451 available. (Only a few such instructions can be written in the
452 @code{divided} syntax).
455 The @code{.N} and @code{.W} suffixes are recognized and honored.
458 All instructions set the flags if and only if they have an @code{s}
463 @subsection Special Characters
465 @cindex line comment character, ARM
466 @cindex ARM line comment character
467 The presence of a @samp{@@} anywhere on a line indicates the start of
468 a comment that extends to the end of that line.
470 If a @samp{#} appears as the first character of a line then the whole
471 line is treated as a comment, but in this case the line could also be
472 a logical line number directive (@pxref{Comments}) or a preprocessor
473 control command (@pxref{Preprocessing}).
475 @cindex line separator, ARM
476 @cindex statement separator, ARM
477 @cindex ARM line separator
478 The @samp{;} character can be used instead of a newline to separate
481 @cindex immediate character, ARM
482 @cindex ARM immediate character
483 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
485 @cindex identifiers, ARM
486 @cindex ARM identifiers
487 *TODO* Explain about /data modifier on symbols.
490 @subsection Register Names
492 @cindex ARM register names
493 @cindex register names, ARM
494 *TODO* Explain about ARM register naming, and the predefined names.
496 @node ARM-Relocations
497 @subsection ARM relocation generation
499 @cindex data relocations, ARM
500 @cindex ARM data relocations
501 Specific data relocations can be generated by putting the relocation name
502 in parentheses after the symbol name. For example:
508 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
510 The following relocations are supported:
526 For compatibility with older toolchains the assembler also accepts
527 @code{(PLT)} after branch targets. On legacy targets this will
528 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
529 targets it will encode either the @samp{R_ARM_CALL} or
530 @samp{R_ARM_JUMP24} relocation, as appropriate.
532 @cindex MOVW and MOVT relocations, ARM
533 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
534 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
535 respectively. For example to load the 32-bit address of foo into r0:
538 MOVW r0, #:lower16:foo
539 MOVT r0, #:upper16:foo
542 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
543 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
544 generated by prefixing the value with @samp{#:lower0_7:#},
545 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
546 respectively. For example to load the 32-bit address of foo into r0:
549 MOVS r0, #:upper8_15:#foo
551 ADDS r0, #:upper0_7:#foo
553 ADDS r0, #:lower8_15:#foo
555 ADDS r0, #:lower0_7:#foo
558 @node ARM-Neon-Alignment
559 @subsection NEON Alignment Specifiers
561 @cindex alignment for NEON instructions
562 Some NEON load/store instructions allow an optional address
564 The ARM documentation specifies that this is indicated by
565 @samp{@@ @var{align}}. However GAS already interprets
566 the @samp{@@} character as a "line comment" start,
567 so @samp{: @var{align}} is used instead. For example:
570 vld1.8 @{q0@}, [r0, :128]
573 @node ARM Floating Point
574 @section Floating Point
576 @cindex floating point, ARM (@sc{ieee})
577 @cindex ARM floating point (@sc{ieee})
578 The ARM family uses @sc{ieee} floating-point numbers.
581 @section ARM Machine Directives
583 @cindex machine directives, ARM
584 @cindex ARM machine directives
587 @c AAAAAAAAAAAAAAAAAAAAAAAAA
589 @cindex @code{.2byte} directive, ARM
590 @cindex @code{.4byte} directive, ARM
591 @cindex @code{.8byte} directive, ARM
592 @item .2byte @var{expression} [, @var{expression}]*
593 @itemx .4byte @var{expression} [, @var{expression}]*
594 @itemx .8byte @var{expression} [, @var{expression}]*
595 These directives write 2, 4 or 8 byte values to the output section.
597 @cindex @code{.align} directive, ARM
598 @item .align @var{expression} [, @var{expression}]
599 This is the generic @var{.align} directive. For the ARM however if the
600 first argument is zero (ie no alignment is needed) the assembler will
601 behave as if the argument had been 2 (ie pad to the next four byte
602 boundary). This is for compatibility with ARM's own assembler.
604 @cindex @code{.arch} directive, ARM
605 @item .arch @var{name}
606 Select the target architecture. Valid values for @var{name} are the same as
607 for the @option{-march} commandline option.
609 Specifying @code{.arch} clears any previously selected architecture
612 @cindex @code{.arch_extension} directive, ARM
613 @item .arch_extension @var{name}
614 Add or remove an architecture extension to the target architecture. Valid
615 values for @var{name} are the same as those accepted as architectural
616 extensions by the @option{-mcpu} commandline option.
618 @code{.arch_extension} may be used multiple times to add or remove extensions
619 incrementally to the architecture being compiled for.
621 @cindex @code{.arm} directive, ARM
623 This performs the same action as @var{.code 32}.
625 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
627 @cindex @code{.bss} directive, ARM
629 This directive switches to the @code{.bss} section.
631 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
633 @cindex @code{.cantunwind} directive, ARM
635 Prevents unwinding through the current function. No personality routine
636 or exception table data is required or permitted.
638 @cindex @code{.code} directive, ARM
639 @item .code @code{[16|32]}
640 This directive selects the instruction set being generated. The value 16
641 selects Thumb, with the value 32 selecting ARM.
643 @cindex @code{.cpu} directive, ARM
644 @item .cpu @var{name}
645 Select the target processor. Valid values for @var{name} are the same as
646 for the @option{-mcpu} commandline option.
648 Specifying @code{.cpu} clears any previously selected architecture
651 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
653 @cindex @code{.dn} and @code{.qn} directives, ARM
654 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
655 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
657 The @code{dn} and @code{qn} directives are used to create typed
658 and/or indexed register aliases for use in Advanced SIMD Extension
659 (Neon) instructions. The former should be used to create aliases
660 of double-precision registers, and the latter to create aliases of
661 quad-precision registers.
663 If these directives are used to create typed aliases, those aliases can
664 be used in Neon instructions instead of writing types after the mnemonic
665 or after each operand. For example:
674 This is equivalent to writing the following:
680 Aliases created using @code{dn} or @code{qn} can be destroyed using
683 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
685 @cindex @code{.eabi_attribute} directive, ARM
686 @item .eabi_attribute @var{tag}, @var{value}
687 Set the EABI object attribute @var{tag} to @var{value}.
689 The @var{tag} is either an attribute number, or one of the following:
690 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
691 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
692 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
693 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
694 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
695 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
696 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
697 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
698 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
699 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
700 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
701 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
702 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
703 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
704 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
705 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
706 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
707 @code{Tag_conformance}, @code{Tag_T2EE_use},
708 @code{Tag_Virtualization_use}
710 The @var{value} is either a @code{number}, @code{"string"}, or
711 @code{number, "string"} depending on the tag.
713 Note - the following legacy values are also accepted by @var{tag}:
714 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
715 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
717 @cindex @code{.even} directive, ARM
719 This directive aligns to an even-numbered address.
721 @cindex @code{.extend} directive, ARM
722 @cindex @code{.ldouble} directive, ARM
723 @item .extend @var{expression} [, @var{expression}]*
724 @itemx .ldouble @var{expression} [, @var{expression}]*
725 These directives write 12byte long double floating-point values to the
726 output section. These are not compatible with current ARM processors
729 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
732 @cindex @code{.fnend} directive, ARM
734 Marks the end of a function with an unwind table entry. The unwind index
735 table entry is created when this directive is processed.
737 If no personality routine has been specified then standard personality
738 routine 0 or 1 will be used, depending on the number of unwind opcodes
742 @cindex @code{.fnstart} directive, ARM
744 Marks the start of a function with an unwind table entry.
746 @cindex @code{.force_thumb} directive, ARM
748 This directive forces the selection of Thumb instructions, even if the
749 target processor does not support those instructions
751 @cindex @code{.fpu} directive, ARM
752 @item .fpu @var{name}
753 Select the floating-point unit to assemble for. Valid values for @var{name}
754 are the same as for the @option{-mfpu} commandline option.
756 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
757 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
759 @cindex @code{.handlerdata} directive, ARM
761 Marks the end of the current function, and the start of the exception table
762 entry for that function. Anything between this directive and the
763 @code{.fnend} directive will be added to the exception table entry.
765 Must be preceded by a @code{.personality} or @code{.personalityindex}
768 @c IIIIIIIIIIIIIIIIIIIIIIIIII
770 @cindex @code{.inst} directive, ARM
771 @item .inst @var{opcode} [ , @dots{} ]
772 @itemx .inst.n @var{opcode} [ , @dots{} ]
773 @itemx .inst.w @var{opcode} [ , @dots{} ]
774 Generates the instruction corresponding to the numerical value @var{opcode}.
775 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
776 specified explicitly, overriding the normal encoding rules.
778 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
779 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
780 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
782 @item .ldouble @var{expression} [, @var{expression}]*
785 @cindex @code{.ltorg} directive, ARM
787 This directive causes the current contents of the literal pool to be
788 dumped into the current section (which is assumed to be the .text
789 section) at the current location (aligned to a word boundary).
790 @code{GAS} maintains a separate literal pool for each section and each
791 sub-section. The @code{.ltorg} directive will only affect the literal
792 pool of the current section and sub-section. At the end of assembly
793 all remaining, un-empty literal pools will automatically be dumped.
795 Note - older versions of @code{GAS} would dump the current literal
796 pool any time a section change occurred. This is no longer done, since
797 it prevents accurate control of the placement of literal pools.
799 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
801 @cindex @code{.movsp} directive, ARM
802 @item .movsp @var{reg} [, #@var{offset}]
803 Tell the unwinder that @var{reg} contains an offset from the current
804 stack pointer. If @var{offset} is not specified then it is assumed to be
807 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
808 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
810 @cindex @code{.object_arch} directive, ARM
811 @item .object_arch @var{name}
812 Override the architecture recorded in the EABI object attribute section.
813 Valid values for @var{name} are the same as for the @code{.arch} directive.
814 Typically this is useful when code uses runtime detection of CPU features.
816 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
818 @cindex @code{.packed} directive, ARM
819 @item .packed @var{expression} [, @var{expression}]*
820 This directive writes 12-byte packed floating-point values to the
821 output section. These are not compatible with current ARM processors
825 @cindex @code{.pad} directive, ARM
826 @item .pad #@var{count}
827 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
828 A positive value indicates the function prologue allocated stack space by
829 decrementing the stack pointer.
831 @cindex @code{.personality} directive, ARM
832 @item .personality @var{name}
833 Sets the personality routine for the current function to @var{name}.
835 @cindex @code{.personalityindex} directive, ARM
836 @item .personalityindex @var{index}
837 Sets the personality routine for the current function to the EABI standard
838 routine number @var{index}
840 @cindex @code{.pool} directive, ARM
842 This is a synonym for .ltorg.
844 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
845 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
847 @cindex @code{.req} directive, ARM
848 @item @var{name} .req @var{register name}
849 This creates an alias for @var{register name} called @var{name}. For
856 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
859 @cindex @code{.save} directive, ARM
860 @item .save @var{reglist}
861 Generate unwinder annotations to restore the registers in @var{reglist}.
862 The format of @var{reglist} is the same as the corresponding store-multiple
866 @exdent @emph{core registers}
867 .save @{r4, r5, r6, lr@}
868 stmfd sp!, @{r4, r5, r6, lr@}
869 @exdent @emph{FPA registers}
872 @exdent @emph{VFP registers}
873 .save @{d8, d9, d10@}
874 fstmdx sp!, @{d8, d9, d10@}
875 @exdent @emph{iWMMXt registers}
877 wstrd wr11, [sp, #-8]!
878 wstrd wr10, [sp, #-8]!
881 wstrd wr11, [sp, #-8]!
883 wstrd wr10, [sp, #-8]!
887 @cindex @code{.setfp} directive, ARM
888 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
889 Make all unwinder annotations relative to a frame pointer. Without this
890 the unwinder will use offsets from the stack pointer.
892 The syntax of this directive is the same as the @code{add} or @code{mov}
893 instruction used to set the frame pointer. @var{spreg} must be either
894 @code{sp} or mentioned in a previous @code{.movsp} directive.
904 @cindex @code{.secrel32} directive, ARM
905 @item .secrel32 @var{expression} [, @var{expression}]*
906 This directive emits relocations that evaluate to the section-relative
907 offset of each expression's symbol. This directive is only supported
910 @cindex @code{.syntax} directive, ARM
911 @item .syntax [@code{unified} | @code{divided}]
912 This directive sets the Instruction Set Syntax as described in the
913 @ref{ARM-Instruction-Set} section.
915 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
917 @cindex @code{.thumb} directive, ARM
919 This performs the same action as @var{.code 16}.
921 @cindex @code{.thumb_func} directive, ARM
923 This directive specifies that the following symbol is the name of a
924 Thumb encoded function. This information is necessary in order to allow
925 the assembler and linker to generate correct code for interworking
926 between Arm and Thumb instructions and should be used even if
927 interworking is not going to be performed. The presence of this
928 directive also implies @code{.thumb}
930 This directive is not neccessary when generating EABI objects. On these
931 targets the encoding is implicit when generating Thumb code.
933 @cindex @code{.thumb_set} directive, ARM
935 This performs the equivalent of a @code{.set} directive in that it
936 creates a symbol which is an alias for another symbol (possibly not yet
937 defined). This directive also has the added property in that it marks
938 the aliased symbol as being a thumb function entry point, in the same
939 way that the @code{.thumb_func} directive does.
941 @cindex @code{.tlsdescseq} directive, ARM
942 @item .tlsdescseq @var{tls-variable}
943 This directive is used to annotate parts of an inlined TLS descriptor
944 trampoline. Normally the trampoline is provided by the linker, and
945 this directive is not needed.
947 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
949 @cindex @code{.unreq} directive, ARM
950 @item .unreq @var{alias-name}
951 This undefines a register alias which was previously defined using the
952 @code{req}, @code{dn} or @code{qn} directives. For example:
959 An error occurs if the name is undefined. Note - this pseudo op can
960 be used to delete builtin in register name aliases (eg 'r0'). This
961 should only be done if it is really necessary.
963 @cindex @code{.unwind_raw} directive, ARM
964 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
965 Insert one of more arbitary unwind opcode bytes, which are known to adjust
966 the stack pointer by @var{offset} bytes.
968 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
971 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
973 @cindex @code{.vsave} directive, ARM
974 @item .vsave @var{vfp-reglist}
975 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
976 using FLDMD. Also works for VFPv3 registers
977 that are to be restored using VLDM.
978 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
982 @exdent @emph{VFP registers}
983 .vsave @{d8, d9, d10@}
984 fstmdd sp!, @{d8, d9, d10@}
985 @exdent @emph{VFPv3 registers}
986 .vsave @{d15, d16, d17@}
987 vstm sp!, @{d15, d16, d17@}
990 Since FLDMX and FSTMX are now deprecated, this directive should be
991 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
993 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
994 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
995 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
996 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1004 @cindex opcodes for ARM
1005 @code{@value{AS}} implements all the standard ARM opcodes. It also
1006 implements several pseudo opcodes, including several synthetic load
1011 @cindex @code{NOP} pseudo op, ARM
1017 This pseudo op will always evaluate to a legal ARM instruction that does
1018 nothing. Currently it will evaluate to MOV r0, r0.
1020 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1023 ldr <register> , = <expression>
1026 If expression evaluates to a numeric constant then a MOV or MVN
1027 instruction will be used in place of the LDR instruction, if the
1028 constant can be generated by either of these instructions. Otherwise
1029 the constant will be placed into the nearest literal pool (if it not
1030 already there) and a PC relative LDR instruction will be generated.
1032 @cindex @code{ADR reg,<label>} pseudo op, ARM
1035 adr <register> <label>
1038 This instruction will load the address of @var{label} into the indicated
1039 register. The instruction will evaluate to a PC relative ADD or SUB
1040 instruction depending upon where the label is located. If the label is
1041 out of range, or if it is not defined in the same file (and section) as
1042 the ADR instruction, then an error will be generated. This instruction
1043 will not make use of the literal pool.
1045 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1048 adrl <register> <label>
1051 This instruction will load the address of @var{label} into the indicated
1052 register. The instruction will evaluate to one or two PC relative ADD
1053 or SUB instructions depending upon where the label is located. If a
1054 second instruction is not needed a NOP instruction will be generated in
1055 its place, so that this instruction is always 8 bytes long.
1057 If the label is out of range, or if it is not defined in the same file
1058 (and section) as the ADRL instruction, then an error will be generated.
1059 This instruction will not make use of the literal pool.
1063 For information on the ARM or Thumb instruction sets, see @cite{ARM
1064 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1067 @node ARM Mapping Symbols
1068 @section Mapping Symbols
1070 The ARM ELF specification requires that special symbols be inserted
1071 into object files to mark certain features:
1077 At the start of a region of code containing ARM instructions.
1081 At the start of a region of code containing THUMB instructions.
1085 At the start of a region of data.
1089 The assembler will automatically insert these symbols for you - there
1090 is no need to code them yourself. Support for tagging symbols ($b,
1091 $f, $p and $m) which is also mentioned in the current ARM ELF
1092 specification is not implemented. This is because they have been
1093 dropped from the new EABI and so tools cannot rely upon their
1096 @node ARM Unwinding Tutorial
1099 The ABI for the ARM Architecture specifies a standard format for
1100 exception unwind information. This information is used when an
1101 exception is thrown to determine where control should be transferred.
1102 In particular, the unwind information is used to determine which
1103 function called the function that threw the exception, and which
1104 function called that one, and so forth. This information is also used
1105 to restore the values of callee-saved registers in the function
1106 catching the exception.
1108 If you are writing functions in assembly code, and those functions
1109 call other functions that throw exceptions, you must use assembly
1110 pseudo ops to ensure that appropriate exception unwind information is
1111 generated. Otherwise, if one of the functions called by your assembly
1112 code throws an exception, the run-time library will be unable to
1113 unwind the stack through your assembly code and your program will not
1116 To illustrate the use of these pseudo ops, we will examine the code
1117 that G++ generates for the following C++ input:
1120 void callee (int *);
1131 This example does not show how to throw or catch an exception from
1132 assembly code. That is a much more complex operation and should
1133 always be done in a high-level language, such as C++, that directly
1134 supports exceptions.
1136 The code generated by one particular version of G++ when compiling the
1143 @ Function supports interworking.
1144 @ args = 0, pretend = 0, frame = 8
1145 @ frame_needed = 1, uses_anonymous_args = 0
1167 Of course, the sequence of instructions varies based on the options
1168 you pass to GCC and on the version of GCC in use. The exact
1169 instructions are not important since we are focusing on the pseudo ops
1170 that are used to generate unwind information.
1172 An important assumption made by the unwinder is that the stack frame
1173 does not change during the body of the function. In particular, since
1174 we assume that the assembly code does not itself throw an exception,
1175 the only point where an exception can be thrown is from a call, such
1176 as the @code{bl} instruction above. At each call site, the same saved
1177 registers (including @code{lr}, which indicates the return address)
1178 must be located in the same locations relative to the frame pointer.
1180 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1181 op appears immediately before the first instruction of the function
1182 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1183 op appears immediately after the last instruction of the function.
1184 These pseudo ops specify the range of the function.
1186 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1187 @code{.pad}) matters; their exact locations are irrelevant. In the
1188 example above, the compiler emits the pseudo ops with particular
1189 instructions. That makes it easier to understand the code, but it is
1190 not required for correctness. It would work just as well to emit all
1191 of the pseudo ops other than @code{.fnend} in the same order, but
1192 immediately after @code{.fnstart}.
1194 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1195 indicates registers that have been saved to the stack so that they can
1196 be restored before the function returns. The argument to the
1197 @code{.save} pseudo op is a list of registers to save. If a register
1198 is ``callee-saved'' (as specified by the ABI) and is modified by the
1199 function you are writing, then your code must save the value before it
1200 is modified and restore the original value before the function
1201 returns. If an exception is thrown, the run-time library restores the
1202 values of these registers from their locations on the stack before
1203 returning control to the exception handler. (Of course, if an
1204 exception is not thrown, the function that contains the @code{.save}
1205 pseudo op restores these registers in the function epilogue, as is
1206 done with the @code{ldmfd} instruction above.)
1208 You do not have to save callee-saved registers at the very beginning
1209 of the function and you do not need to use the @code{.save} pseudo op
1210 immediately following the point at which the registers are saved.
1211 However, if you modify a callee-saved register, you must save it on
1212 the stack before modifying it and before calling any functions which
1213 might throw an exception. And, you must use the @code{.save} pseudo
1214 op to indicate that you have done so.
1216 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1217 modification of the stack pointer that does not save any registers.
1218 The argument is the number of bytes (in decimal) that are subtracted
1219 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1220 subtracting from the stack pointer increases the size of the stack.)
1222 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1223 indicates the register that contains the frame pointer. The first
1224 argument is the register that is set, which is typically @code{fp}.
1225 The second argument indicates the register from which the frame
1226 pointer takes its value. The third argument, if present, is the value
1227 (in decimal) added to the register specified by the second argument to
1228 compute the value of the frame pointer. You should not modify the
1229 frame pointer in the body of the function.
1231 If you do not use a frame pointer, then you should not use the
1232 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1233 should avoid modifying the stack pointer outside of the function
1234 prologue. Otherwise, the run-time library will be unable to find
1235 saved registers when it is unwinding the stack.
1237 The pseudo ops described above are sufficient for writing assembly
1238 code that calls functions which may throw exceptions. If you need to
1239 know more about the object-file format used to represent unwind
1240 information, you may consult the @cite{Exception Handling ABI for the
1241 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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