1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
125 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
126 @code{i80200} (Intel XScale processor)
127 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
130 The special name @code{all} may be used to allow the
131 assembler to accept instructions valid for any ARM processor.
133 In addition to the basic instruction set, the assembler can be told to
134 accept various extension mnemonics that extend the processor using the
135 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
136 is equivalent to specifying @code{-mcpu=ep9312}.
138 Multiple extensions may be specified, separated by a @code{+}. The
139 extensions should be specified in ascending alphabetical order.
141 Extension mnemonics may also be removed from those the assembler accepts.
142 This is done be prepending @code{no} to the option that adds the extension.
143 Extensions that are removed should be listed after all extensions which have
144 been added, again in ascending alphabetical order. For example,
145 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
148 The following extensions are currently supported:
155 @cindex @code{-march=} command line option, ARM
156 @item -march=@var{architecture}[+@var{extension}@dots{}]
157 This option specifies the target architecture. The assembler will issue
158 an error message if an attempt is made to assemble an instruction which
159 will not execute on the target architecture. The following architecture
160 names are recognized:
189 If both @code{-mcpu} and
190 @code{-march} are specified, the assembler will use
191 the setting for @code{-mcpu}.
193 The architecture option can be extended with the same instruction set
194 extension options as the @code{-mcpu} option.
196 @cindex @code{-mfpu=} command line option, ARM
197 @item -mfpu=@var{floating-point-format}
199 This option specifies the floating point format to assemble for. The
200 assembler will issue an error message if an attempt is made to assemble
201 an instruction which will not execute on the target floating point unit.
202 The following format options are recognized:
222 @code{vfpv3-d16-fp16},
236 In addition to determining which instructions are assembled, this option
237 also affects the way in which the @code{.double} assembler directive behaves
238 when assembling little-endian code.
240 The default is dependent on the processor selected. For Architecture 5 or
241 later, the default is to assembler for VFP instructions; for earlier
242 architectures the default is to assemble for FPA instructions.
244 @cindex @code{-mthumb} command line option, ARM
246 This option specifies that the assembler should start assembling Thumb
247 instructions; that is, it should behave as though the file starts with a
248 @code{.code 16} directive.
250 @cindex @code{-mthumb-interwork} command line option, ARM
251 @item -mthumb-interwork
252 This option specifies that the output generated by the assembler should
253 be marked as supporting interworking.
255 @cindex @code{-mimplicit-it} command line option, ARM
256 @item -mimplicit-it=never
257 @itemx -mimplicit-it=always
258 @itemx -mimplicit-it=arm
259 @itemx -mimplicit-it=thumb
260 The @code{-mimplicit-it} option controls the behavior of the assembler when
261 conditional instructions are not enclosed in IT blocks.
262 There are four possible behaviors.
263 If @code{never} is specified, such constructs cause a warning in ARM
264 code and an error in Thumb-2 code.
265 If @code{always} is specified, such constructs are accepted in both
266 ARM and Thumb-2 code, where the IT instruction is added implicitly.
267 If @code{arm} is specified, such constructs are accepted in ARM code
268 and cause an error in Thumb-2 code.
269 If @code{thumb} is specified, such constructs cause a warning in ARM
270 code and are accepted in Thumb-2 code. If you omit this option, the
271 behavior is equivalent to @code{-mimplicit-it=arm}.
273 @cindex @code{-mapcs-26} command line option, ARM
274 @cindex @code{-mapcs-32} command line option, ARM
277 These options specify that the output generated by the assembler should
278 be marked as supporting the indicated version of the Arm Procedure.
281 @cindex @code{-matpcs} command line option, ARM
283 This option specifies that the output generated by the assembler should
284 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
285 enabled this option will cause the assembler to create an empty
286 debugging section in the object file called .arm.atpcs. Debuggers can
287 use this to determine the ABI being used by.
289 @cindex @code{-mapcs-float} command line option, ARM
291 This indicates the floating point variant of the APCS should be
292 used. In this variant floating point arguments are passed in FP
293 registers rather than integer registers.
295 @cindex @code{-mapcs-reentrant} command line option, ARM
296 @item -mapcs-reentrant
297 This indicates that the reentrant variant of the APCS should be used.
298 This variant supports position independent code.
300 @cindex @code{-mfloat-abi=} command line option, ARM
301 @item -mfloat-abi=@var{abi}
302 This option specifies that the output generated by the assembler should be
303 marked as using specified floating point ABI.
304 The following values are recognized:
310 @cindex @code{-eabi=} command line option, ARM
311 @item -meabi=@var{ver}
312 This option specifies which EABI version the produced object files should
314 The following values are recognized:
320 @cindex @code{-EB} command line option, ARM
322 This option specifies that the output generated by the assembler should
323 be marked as being encoded for a big-endian processor.
325 @cindex @code{-EL} command line option, ARM
327 This option specifies that the output generated by the assembler should
328 be marked as being encoded for a little-endian processor.
330 @cindex @code{-k} command line option, ARM
331 @cindex PIC code generation for ARM
333 This option specifies that the output of the assembler should be marked
334 as position-independent code (PIC).
336 @cindex @code{--fix-v4bx} command line option, ARM
338 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
339 the linker option of the same name.
341 @cindex @code{-mwarn-deprecated} command line option, ARM
342 @item -mwarn-deprecated
343 @itemx -mno-warn-deprecated
344 Enable or disable warnings about using deprecated options or
345 features. The default is to warn.
353 * ARM-Instruction-Set:: Instruction Set
354 * ARM-Chars:: Special Characters
355 * ARM-Regs:: Register Names
356 * ARM-Relocations:: Relocations
357 * ARM-Neon-Alignment:: NEON Alignment Specifiers
360 @node ARM-Instruction-Set
361 @subsection Instruction Set Syntax
362 Two slightly different syntaxes are support for ARM and THUMB
363 instructions. The default, @code{divided}, uses the old style where
364 ARM and THUMB instructions had their own, separate syntaxes. The new,
365 @code{unified} syntax, which can be selected via the @code{.syntax}
366 directive, and has the following main features:
370 Immediate operands do not require a @code{#} prefix.
373 The @code{IT} instruction may appear, and if it does it is validated
374 against subsequent conditional affixes. In ARM mode it does not
375 generate machine code, in THUMB mode it does.
378 For ARM instructions the conditional affixes always appear at the end
379 of the instruction. For THUMB instructions conditional affixes can be
380 used, but only inside the scope of an @code{IT} instruction.
383 All of the instructions new to the V6T2 architecture (and later) are
384 available. (Only a few such instructions can be written in the
385 @code{divided} syntax).
388 The @code{.N} and @code{.W} suffixes are recognized and honored.
391 All instructions set the flags if and only if they have an @code{s}
396 @subsection Special Characters
398 @cindex line comment character, ARM
399 @cindex ARM line comment character
400 The presence of a @samp{@@} on a line indicates the start of a comment
401 that extends to the end of the current line. If a @samp{#} appears as
402 the first character of a line, the whole line is treated as a comment.
404 @cindex line separator, ARM
405 @cindex statement separator, ARM
406 @cindex ARM line separator
407 The @samp{;} character can be used instead of a newline to separate
410 @cindex immediate character, ARM
411 @cindex ARM immediate character
412 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
414 @cindex identifiers, ARM
415 @cindex ARM identifiers
416 *TODO* Explain about /data modifier on symbols.
419 @subsection Register Names
421 @cindex ARM register names
422 @cindex register names, ARM
423 *TODO* Explain about ARM register naming, and the predefined names.
425 @node ARM-Neon-Alignment
426 @subsection NEON Alignment Specifiers
428 @cindex alignment for NEON instructions
429 Some NEON load/store instructions allow an optional address
431 The ARM documentation specifies that this is indicated by
432 @samp{@@ @var{align}}. However GAS already interprets
433 the @samp{@@} character as a "line comment" start,
434 so @samp{: @var{align}} is used instead. For example:
437 vld1.8 @{q0@}, [r0, :128]
440 @node ARM Floating Point
441 @section Floating Point
443 @cindex floating point, ARM (@sc{ieee})
444 @cindex ARM floating point (@sc{ieee})
445 The ARM family uses @sc{ieee} floating-point numbers.
447 @node ARM-Relocations
448 @subsection ARM relocation generation
450 @cindex data relocations, ARM
451 @cindex ARM data relocations
452 Specific data relocations can be generated by putting the relocation name
453 in parentheses after the symbol name. For example:
459 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
461 The following relocations are supported:
475 For compatibility with older toolchains the assembler also accepts
476 @code{(PLT)} after branch targets. This will generate the deprecated
477 @samp{R_ARM_PLT32} relocation.
479 @cindex MOVW and MOVT relocations, ARM
480 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
481 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
482 respectively. For example to load the 32-bit address of foo into r0:
485 MOVW r0, #:lower16:foo
486 MOVT r0, #:upper16:foo
490 @section ARM Machine Directives
492 @cindex machine directives, ARM
493 @cindex ARM machine directives
496 @c AAAAAAAAAAAAAAAAAAAAAAAAA
498 @cindex @code{.2byte} directive, ARM
499 @cindex @code{.4byte} directive, ARM
500 @cindex @code{.8byte} directive, ARM
501 @item .2byte @var{expression} [, @var{expression}]*
502 @itemx .4byte @var{expression} [, @var{expression}]*
503 @itemx .8byte @var{expression} [, @var{expression}]*
504 These directives write 2, 4 or 8 byte values to the output section.
506 @cindex @code{.align} directive, ARM
507 @item .align @var{expression} [, @var{expression}]
508 This is the generic @var{.align} directive. For the ARM however if the
509 first argument is zero (ie no alignment is needed) the assembler will
510 behave as if the argument had been 2 (ie pad to the next four byte
511 boundary). This is for compatibility with ARM's own assembler.
513 @cindex @code{.arch} directive, ARM
514 @item .arch @var{name}
515 Select the target architecture. Valid values for @var{name} are the same as
516 for the @option{-march} commandline option.
518 Specifying @code{.arch} clears any previously selected architecture
521 @cindex @code{.arch_extension} directive, ARM
522 @item .arch_extension @var{name}
523 Add or remove an architecture extension to the target architecture. Valid
524 values for @var{name} are the same as those accepted as architectural
525 extensions by the @option{-mcpu} commandline option.
527 @code{.arch_extension} may be used multiple times to add or remove extensions
528 incrementally to the architecture being compiled for.
530 @cindex @code{.arm} directive, ARM
532 This performs the same action as @var{.code 32}.
535 @cindex @code{.pad} directive, ARM
536 @item .pad #@var{count}
537 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
538 A positive value indicates the function prologue allocated stack space by
539 decrementing the stack pointer.
541 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
543 @cindex @code{.bss} directive, ARM
545 This directive switches to the @code{.bss} section.
547 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
549 @cindex @code{.cantunwind} directive, ARM
551 Prevents unwinding through the current function. No personality routine
552 or exception table data is required or permitted.
554 @cindex @code{.code} directive, ARM
555 @item .code @code{[16|32]}
556 This directive selects the instruction set being generated. The value 16
557 selects Thumb, with the value 32 selecting ARM.
559 @cindex @code{.cpu} directive, ARM
560 @item .cpu @var{name}
561 Select the target processor. Valid values for @var{name} are the same as
562 for the @option{-mcpu} commandline option.
564 Specifying @code{.cpu} clears any previously selected architecture
567 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
569 @cindex @code{.dn} and @code{.qn} directives, ARM
570 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
571 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
573 The @code{dn} and @code{qn} directives are used to create typed
574 and/or indexed register aliases for use in Advanced SIMD Extension
575 (Neon) instructions. The former should be used to create aliases
576 of double-precision registers, and the latter to create aliases of
577 quad-precision registers.
579 If these directives are used to create typed aliases, those aliases can
580 be used in Neon instructions instead of writing types after the mnemonic
581 or after each operand. For example:
590 This is equivalent to writing the following:
596 Aliases created using @code{dn} or @code{qn} can be destroyed using
599 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
601 @cindex @code{.eabi_attribute} directive, ARM
602 @item .eabi_attribute @var{tag}, @var{value}
603 Set the EABI object attribute @var{tag} to @var{value}.
605 The @var{tag} is either an attribute number, or one of the following:
606 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
607 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
608 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
609 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
610 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
611 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
612 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
613 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
614 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
615 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
616 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
617 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
618 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
619 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
620 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
621 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
622 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
623 @code{Tag_conformance}, @code{Tag_T2EE_use},
624 @code{Tag_Virtualization_use}
626 The @var{value} is either a @code{number}, @code{"string"}, or
627 @code{number, "string"} depending on the tag.
629 Note - the following legacy values are also accepted by @var{tag}:
630 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
631 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
633 @cindex @code{.even} directive, ARM
635 This directive aligns to an even-numbered address.
637 @cindex @code{.extend} directive, ARM
638 @cindex @code{.ldouble} directive, ARM
639 @item .extend @var{expression} [, @var{expression}]*
640 @itemx .ldouble @var{expression} [, @var{expression}]*
641 These directives write 12byte long double floating-point values to the
642 output section. These are not compatible with current ARM processors
645 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
648 @cindex @code{.fnend} directive, ARM
650 Marks the end of a function with an unwind table entry. The unwind index
651 table entry is created when this directive is processed.
653 If no personality routine has been specified then standard personality
654 routine 0 or 1 will be used, depending on the number of unwind opcodes
658 @cindex @code{.fnstart} directive, ARM
660 Marks the start of a function with an unwind table entry.
662 @cindex @code{.force_thumb} directive, ARM
664 This directive forces the selection of Thumb instructions, even if the
665 target processor does not support those instructions
667 @cindex @code{.fpu} directive, ARM
668 @item .fpu @var{name}
669 Select the floating-point unit to assemble for. Valid values for @var{name}
670 are the same as for the @option{-mfpu} commandline option.
672 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
673 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
675 @cindex @code{.handlerdata} directive, ARM
677 Marks the end of the current function, and the start of the exception table
678 entry for that function. Anything between this directive and the
679 @code{.fnend} directive will be added to the exception table entry.
681 Must be preceded by a @code{.personality} or @code{.personalityindex}
684 @c IIIIIIIIIIIIIIIIIIIIIIIIII
686 @cindex @code{.inst} directive, ARM
687 @item .inst @var{opcode} [ , @dots{} ]
688 @itemx .inst.n @var{opcode} [ , @dots{} ]
689 @itemx .inst.w @var{opcode} [ , @dots{} ]
690 Generates the instruction corresponding to the numerical value @var{opcode}.
691 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
692 specified explicitly, overriding the normal encoding rules.
694 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
695 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
696 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
698 @item .ldouble @var{expression} [, @var{expression}]*
701 @cindex @code{.ltorg} directive, ARM
703 This directive causes the current contents of the literal pool to be
704 dumped into the current section (which is assumed to be the .text
705 section) at the current location (aligned to a word boundary).
706 @code{GAS} maintains a separate literal pool for each section and each
707 sub-section. The @code{.ltorg} directive will only affect the literal
708 pool of the current section and sub-section. At the end of assembly
709 all remaining, un-empty literal pools will automatically be dumped.
711 Note - older versions of @code{GAS} would dump the current literal
712 pool any time a section change occurred. This is no longer done, since
713 it prevents accurate control of the placement of literal pools.
715 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
717 @cindex @code{.movsp} directive, ARM
718 @item .movsp @var{reg} [, #@var{offset}]
719 Tell the unwinder that @var{reg} contains an offset from the current
720 stack pointer. If @var{offset} is not specified then it is assumed to be
723 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
724 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
726 @cindex @code{.object_arch} directive, ARM
727 @item .object_arch @var{name}
728 Override the architecture recorded in the EABI object attribute section.
729 Valid values for @var{name} are the same as for the @code{.arch} directive.
730 Typically this is useful when code uses runtime detection of CPU features.
732 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
734 @cindex @code{.packed} directive, ARM
735 @item .packed @var{expression} [, @var{expression}]*
736 This directive writes 12-byte packed floating-point values to the
737 output section. These are not compatible with current ARM processors
740 @cindex @code{.pad} directive, ARM
741 @item .pad #@var{count}
742 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
743 A positive value indicates the function prologue allocated stack space by
744 decrementing the stack pointer.
746 @cindex @code{.personality} directive, ARM
747 @item .personality @var{name}
748 Sets the personality routine for the current function to @var{name}.
750 @cindex @code{.personalityindex} directive, ARM
751 @item .personalityindex @var{index}
752 Sets the personality routine for the current function to the EABI standard
753 routine number @var{index}
755 @cindex @code{.pool} directive, ARM
757 This is a synonym for .ltorg.
759 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
760 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
762 @cindex @code{.req} directive, ARM
763 @item @var{name} .req @var{register name}
764 This creates an alias for @var{register name} called @var{name}. For
771 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
774 @cindex @code{.save} directive, ARM
775 @item .save @var{reglist}
776 Generate unwinder annotations to restore the registers in @var{reglist}.
777 The format of @var{reglist} is the same as the corresponding store-multiple
781 @exdent @emph{core registers}
782 .save @{r4, r5, r6, lr@}
783 stmfd sp!, @{r4, r5, r6, lr@}
784 @exdent @emph{FPA registers}
787 @exdent @emph{VFP registers}
788 .save @{d8, d9, d10@}
789 fstmdx sp!, @{d8, d9, d10@}
790 @exdent @emph{iWMMXt registers}
792 wstrd wr11, [sp, #-8]!
793 wstrd wr10, [sp, #-8]!
796 wstrd wr11, [sp, #-8]!
798 wstrd wr10, [sp, #-8]!
802 @cindex @code{.setfp} directive, ARM
803 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
804 Make all unwinder annotations relative to a frame pointer. Without this
805 the unwinder will use offsets from the stack pointer.
807 The syntax of this directive is the same as the @code{add} or @code{mov}
808 instruction used to set the frame pointer. @var{spreg} must be either
809 @code{sp} or mentioned in a previous @code{.movsp} directive.
819 @cindex @code{.secrel32} directive, ARM
820 @item .secrel32 @var{expression} [, @var{expression}]*
821 This directive emits relocations that evaluate to the section-relative
822 offset of each expression's symbol. This directive is only supported
825 @cindex @code{.syntax} directive, ARM
826 @item .syntax [@code{unified} | @code{divided}]
827 This directive sets the Instruction Set Syntax as described in the
828 @ref{ARM-Instruction-Set} section.
830 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
832 @cindex @code{.thumb} directive, ARM
834 This performs the same action as @var{.code 16}.
836 @cindex @code{.thumb_func} directive, ARM
838 This directive specifies that the following symbol is the name of a
839 Thumb encoded function. This information is necessary in order to allow
840 the assembler and linker to generate correct code for interworking
841 between Arm and Thumb instructions and should be used even if
842 interworking is not going to be performed. The presence of this
843 directive also implies @code{.thumb}
845 This directive is not neccessary when generating EABI objects. On these
846 targets the encoding is implicit when generating Thumb code.
848 @cindex @code{.thumb_set} directive, ARM
850 This performs the equivalent of a @code{.set} directive in that it
851 creates a symbol which is an alias for another symbol (possibly not yet
852 defined). This directive also has the added property in that it marks
853 the aliased symbol as being a thumb function entry point, in the same
854 way that the @code{.thumb_func} directive does.
856 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
858 @cindex @code{.unreq} directive, ARM
859 @item .unreq @var{alias-name}
860 This undefines a register alias which was previously defined using the
861 @code{req}, @code{dn} or @code{qn} directives. For example:
868 An error occurs if the name is undefined. Note - this pseudo op can
869 be used to delete builtin in register name aliases (eg 'r0'). This
870 should only be done if it is really necessary.
872 @cindex @code{.unwind_raw} directive, ARM
873 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
874 Insert one of more arbitary unwind opcode bytes, which are known to adjust
875 the stack pointer by @var{offset} bytes.
877 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
880 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
882 @cindex @code{.vsave} directive, ARM
883 @item .vsave @var{vfp-reglist}
884 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
885 using FLDMD. Also works for VFPv3 registers
886 that are to be restored using VLDM.
887 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
891 @exdent @emph{VFP registers}
892 .vsave @{d8, d9, d10@}
893 fstmdd sp!, @{d8, d9, d10@}
894 @exdent @emph{VFPv3 registers}
895 .vsave @{d15, d16, d17@}
896 vstm sp!, @{d15, d16, d17@}
899 Since FLDMX and FSTMX are now deprecated, this directive should be
900 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
902 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
903 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
904 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
905 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
913 @cindex opcodes for ARM
914 @code{@value{AS}} implements all the standard ARM opcodes. It also
915 implements several pseudo opcodes, including several synthetic load
920 @cindex @code{NOP} pseudo op, ARM
926 This pseudo op will always evaluate to a legal ARM instruction that does
927 nothing. Currently it will evaluate to MOV r0, r0.
929 @cindex @code{LDR reg,=<label>} pseudo op, ARM
932 ldr <register> , = <expression>
935 If expression evaluates to a numeric constant then a MOV or MVN
936 instruction will be used in place of the LDR instruction, if the
937 constant can be generated by either of these instructions. Otherwise
938 the constant will be placed into the nearest literal pool (if it not
939 already there) and a PC relative LDR instruction will be generated.
941 @cindex @code{ADR reg,<label>} pseudo op, ARM
944 adr <register> <label>
947 This instruction will load the address of @var{label} into the indicated
948 register. The instruction will evaluate to a PC relative ADD or SUB
949 instruction depending upon where the label is located. If the label is
950 out of range, or if it is not defined in the same file (and section) as
951 the ADR instruction, then an error will be generated. This instruction
952 will not make use of the literal pool.
954 @cindex @code{ADRL reg,<label>} pseudo op, ARM
957 adrl <register> <label>
960 This instruction will load the address of @var{label} into the indicated
961 register. The instruction will evaluate to one or two PC relative ADD
962 or SUB instructions depending upon where the label is located. If a
963 second instruction is not needed a NOP instruction will be generated in
964 its place, so that this instruction is always 8 bytes long.
966 If the label is out of range, or if it is not defined in the same file
967 (and section) as the ADRL instruction, then an error will be generated.
968 This instruction will not make use of the literal pool.
972 For information on the ARM or Thumb instruction sets, see @cite{ARM
973 Software Development Toolkit Reference Manual}, Advanced RISC Machines
976 @node ARM Mapping Symbols
977 @section Mapping Symbols
979 The ARM ELF specification requires that special symbols be inserted
980 into object files to mark certain features:
986 At the start of a region of code containing ARM instructions.
990 At the start of a region of code containing THUMB instructions.
994 At the start of a region of data.
998 The assembler will automatically insert these symbols for you - there
999 is no need to code them yourself. Support for tagging symbols ($b,
1000 $f, $p and $m) which is also mentioned in the current ARM ELF
1001 specification is not implemented. This is because they have been
1002 dropped from the new EABI and so tools cannot rely upon their
1005 @node ARM Unwinding Tutorial
1008 The ABI for the ARM Architecture specifies a standard format for
1009 exception unwind information. This information is used when an
1010 exception is thrown to determine where control should be transferred.
1011 In particular, the unwind information is used to determine which
1012 function called the function that threw the exception, and which
1013 function called that one, and so forth. This information is also used
1014 to restore the values of callee-saved registers in the function
1015 catching the exception.
1017 If you are writing functions in assembly code, and those functions
1018 call other functions that throw exceptions, you must use assembly
1019 pseudo ops to ensure that appropriate exception unwind information is
1020 generated. Otherwise, if one of the functions called by your assembly
1021 code throws an exception, the run-time library will be unable to
1022 unwind the stack through your assembly code and your program will not
1025 To illustrate the use of these pseudo ops, we will examine the code
1026 that G++ generates for the following C++ input:
1029 void callee (int *);
1040 This example does not show how to throw or catch an exception from
1041 assembly code. That is a much more complex operation and should
1042 always be done in a high-level language, such as C++, that directly
1043 supports exceptions.
1045 The code generated by one particular version of G++ when compiling the
1052 @ Function supports interworking.
1053 @ args = 0, pretend = 0, frame = 8
1054 @ frame_needed = 1, uses_anonymous_args = 0
1076 Of course, the sequence of instructions varies based on the options
1077 you pass to GCC and on the version of GCC in use. The exact
1078 instructions are not important since we are focusing on the pseudo ops
1079 that are used to generate unwind information.
1081 An important assumption made by the unwinder is that the stack frame
1082 does not change during the body of the function. In particular, since
1083 we assume that the assembly code does not itself throw an exception,
1084 the only point where an exception can be thrown is from a call, such
1085 as the @code{bl} instruction above. At each call site, the same saved
1086 registers (including @code{lr}, which indicates the return address)
1087 must be located in the same locations relative to the frame pointer.
1089 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1090 op appears immediately before the first instruction of the function
1091 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1092 op appears immediately after the last instruction of the function.
1093 These pseudo ops specify the range of the function.
1095 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1096 @code{.pad}) matters; their exact locations are irrelevant. In the
1097 example above, the compiler emits the pseudo ops with particular
1098 instructions. That makes it easier to understand the code, but it is
1099 not required for correctness. It would work just as well to emit all
1100 of the pseudo ops other than @code{.fnend} in the same order, but
1101 immediately after @code{.fnstart}.
1103 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1104 indicates registers that have been saved to the stack so that they can
1105 be restored before the function returns. The argument to the
1106 @code{.save} pseudo op is a list of registers to save. If a register
1107 is ``callee-saved'' (as specified by the ABI) and is modified by the
1108 function you are writing, then your code must save the value before it
1109 is modified and restore the original value before the function
1110 returns. If an exception is thrown, the run-time library restores the
1111 values of these registers from their locations on the stack before
1112 returning control to the exception handler. (Of course, if an
1113 exception is not thrown, the function that contains the @code{.save}
1114 pseudo op restores these registers in the function epilogue, as is
1115 done with the @code{ldmfd} instruction above.)
1117 You do not have to save callee-saved registers at the very beginning
1118 of the function and you do not need to use the @code{.save} pseudo op
1119 immediately following the point at which the registers are saved.
1120 However, if you modify a callee-saved register, you must save it on
1121 the stack before modifying it and before calling any functions which
1122 might throw an exception. And, you must use the @code{.save} pseudo
1123 op to indicate that you have done so.
1125 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1126 modification of the stack pointer that does not save any registers.
1127 The argument is the number of bytes (in decimal) that are subtracted
1128 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1129 subtracting from the stack pointer increases the size of the stack.)
1131 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1132 indicates the register that contains the frame pointer. The first
1133 argument is the register that is set, which is typically @code{fp}.
1134 The second argument indicates the register from which the frame
1135 pointer takes its value. The third argument, if present, is the value
1136 (in decimal) added to the register specified by the second argument to
1137 compute the value of the frame pointer. You should not modify the
1138 frame pointer in the body of the function.
1140 If you do not use a frame pointer, then you should not use the
1141 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1142 should avoid modifying the stack pointer outside of the function
1143 prologue. Otherwise, the run-time library will be unable to find
1144 saved registers when it is unwinding the stack.
1146 The pseudo ops described above are sufficient for writing assembly
1147 code that calls functions which may throw exceptions. If you need to
1148 know more about the object-file format used to represent unwind
1149 information, you may consult the @cite{Exception Handling ABI for the
1150 ARM Architecture} available from @uref{http://infocenter.arm.com}.