1 @c Copyright (C) 1996-2018 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
145 @code{cortex-m0plus},
148 @code{marvell-whitney},
151 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
152 @code{i80200} (Intel XScale processor)
153 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
156 The special name @code{all} may be used to allow the
157 assembler to accept instructions valid for any ARM processor.
159 In addition to the basic instruction set, the assembler can be told to
160 accept various extension mnemonics that extend the processor using the
161 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
162 is equivalent to specifying @code{-mcpu=ep9312}.
164 Multiple extensions may be specified, separated by a @code{+}. The
165 extensions should be specified in ascending alphabetical order.
167 Some extensions may be restricted to particular architectures; this is
168 documented in the list of extensions below.
170 Extension mnemonics may also be removed from those the assembler accepts.
171 This is done be prepending @code{no} to the option that adds the extension.
172 Extensions that are removed should be listed after all extensions which have
173 been added, again in ascending alphabetical order. For example,
174 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
177 The following extensions are currently supported:
179 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
180 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
181 @code{fp} (Floating Point Extensions for v8-A architecture),
182 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
183 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
184 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
189 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
191 @code{os} (Operating System for v6M architecture),
192 @code{sec} (Security Extensions for v6K and v7-A architectures),
193 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
194 @code{virt} (Virtualization Extensions for v7-A architecture, implies
196 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
197 @code{ras} (Reliability, Availability and Serviceability extensions
198 for v8-A architecture),
199 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
204 @cindex @code{-march=} command line option, ARM
205 @item -march=@var{architecture}[+@var{extension}@dots{}]
206 This option specifies the target architecture. The assembler will issue
207 an error message if an attempt is made to assemble an instruction which
208 will not execute on the target architecture. The following architecture
209 names are recognized:
248 If both @code{-mcpu} and
249 @code{-march} are specified, the assembler will use
250 the setting for @code{-mcpu}.
252 The architecture option can be extended with the same instruction set
253 extension options as the @code{-mcpu} option.
255 @cindex @code{-mfpu=} command line option, ARM
256 @item -mfpu=@var{floating-point-format}
258 This option specifies the floating point format to assemble for. The
259 assembler will issue an error message if an attempt is made to assemble
260 an instruction which will not execute on the target floating point unit.
261 The following format options are recognized:
281 @code{vfpv3-d16-fp16},
298 @code{neon-fp-armv8},
299 @code{crypto-neon-fp-armv8},
300 @code{neon-fp-armv8.1}
302 @code{crypto-neon-fp-armv8.1}.
304 In addition to determining which instructions are assembled, this option
305 also affects the way in which the @code{.double} assembler directive behaves
306 when assembling little-endian code.
308 The default is dependent on the processor selected. For Architecture 5 or
309 later, the default is to assemble for VFP instructions; for earlier
310 architectures the default is to assemble for FPA instructions.
312 @cindex @code{-mthumb} command line option, ARM
314 This option specifies that the assembler should start assembling Thumb
315 instructions; that is, it should behave as though the file starts with a
316 @code{.code 16} directive.
318 @cindex @code{-mthumb-interwork} command line option, ARM
319 @item -mthumb-interwork
320 This option specifies that the output generated by the assembler should
321 be marked as supporting interworking.
323 @cindex @code{-mimplicit-it} command line option, ARM
324 @item -mimplicit-it=never
325 @itemx -mimplicit-it=always
326 @itemx -mimplicit-it=arm
327 @itemx -mimplicit-it=thumb
328 The @code{-mimplicit-it} option controls the behavior of the assembler when
329 conditional instructions are not enclosed in IT blocks.
330 There are four possible behaviors.
331 If @code{never} is specified, such constructs cause a warning in ARM
332 code and an error in Thumb-2 code.
333 If @code{always} is specified, such constructs are accepted in both
334 ARM and Thumb-2 code, where the IT instruction is added implicitly.
335 If @code{arm} is specified, such constructs are accepted in ARM code
336 and cause an error in Thumb-2 code.
337 If @code{thumb} is specified, such constructs cause a warning in ARM
338 code and are accepted in Thumb-2 code. If you omit this option, the
339 behavior is equivalent to @code{-mimplicit-it=arm}.
341 @cindex @code{-mapcs-26} command line option, ARM
342 @cindex @code{-mapcs-32} command line option, ARM
345 These options specify that the output generated by the assembler should
346 be marked as supporting the indicated version of the Arm Procedure.
349 @cindex @code{-matpcs} command line option, ARM
351 This option specifies that the output generated by the assembler should
352 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
353 enabled this option will cause the assembler to create an empty
354 debugging section in the object file called .arm.atpcs. Debuggers can
355 use this to determine the ABI being used by.
357 @cindex @code{-mapcs-float} command line option, ARM
359 This indicates the floating point variant of the APCS should be
360 used. In this variant floating point arguments are passed in FP
361 registers rather than integer registers.
363 @cindex @code{-mapcs-reentrant} command line option, ARM
364 @item -mapcs-reentrant
365 This indicates that the reentrant variant of the APCS should be used.
366 This variant supports position independent code.
368 @cindex @code{-mfloat-abi=} command line option, ARM
369 @item -mfloat-abi=@var{abi}
370 This option specifies that the output generated by the assembler should be
371 marked as using specified floating point ABI.
372 The following values are recognized:
378 @cindex @code{-eabi=} command line option, ARM
379 @item -meabi=@var{ver}
380 This option specifies which EABI version the produced object files should
382 The following values are recognized:
388 @cindex @code{-EB} command line option, ARM
390 This option specifies that the output generated by the assembler should
391 be marked as being encoded for a big-endian processor.
393 Note: If a program is being built for a system with big-endian data
394 and little-endian instructions then it should be assembled with the
395 @option{-EB} option, (all of it, code and data) and then linked with
396 the @option{--be8} option. This will reverse the endianness of the
397 instructions back to little-endian, but leave the data as big-endian.
399 @cindex @code{-EL} command line option, ARM
401 This option specifies that the output generated by the assembler should
402 be marked as being encoded for a little-endian processor.
404 @cindex @code{-k} command line option, ARM
405 @cindex PIC code generation for ARM
407 This option specifies that the output of the assembler should be marked
408 as position-independent code (PIC).
410 @cindex @code{--fix-v4bx} command line option, ARM
412 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
413 the linker option of the same name.
415 @cindex @code{-mwarn-deprecated} command line option, ARM
416 @item -mwarn-deprecated
417 @itemx -mno-warn-deprecated
418 Enable or disable warnings about using deprecated options or
419 features. The default is to warn.
421 @cindex @code{-mccs} command line option, ARM
423 Turns on CodeComposer Studio assembly syntax compatibility mode.
425 @cindex @code{-mwarn-syms} command line option, ARM
427 @itemx -mno-warn-syms
428 Enable or disable warnings about symbols that match the names of ARM
429 instructions. The default is to warn.
437 * ARM-Instruction-Set:: Instruction Set
438 * ARM-Chars:: Special Characters
439 * ARM-Regs:: Register Names
440 * ARM-Relocations:: Relocations
441 * ARM-Neon-Alignment:: NEON Alignment Specifiers
444 @node ARM-Instruction-Set
445 @subsection Instruction Set Syntax
446 Two slightly different syntaxes are support for ARM and THUMB
447 instructions. The default, @code{divided}, uses the old style where
448 ARM and THUMB instructions had their own, separate syntaxes. The new,
449 @code{unified} syntax, which can be selected via the @code{.syntax}
450 directive, and has the following main features:
454 Immediate operands do not require a @code{#} prefix.
457 The @code{IT} instruction may appear, and if it does it is validated
458 against subsequent conditional affixes. In ARM mode it does not
459 generate machine code, in THUMB mode it does.
462 For ARM instructions the conditional affixes always appear at the end
463 of the instruction. For THUMB instructions conditional affixes can be
464 used, but only inside the scope of an @code{IT} instruction.
467 All of the instructions new to the V6T2 architecture (and later) are
468 available. (Only a few such instructions can be written in the
469 @code{divided} syntax).
472 The @code{.N} and @code{.W} suffixes are recognized and honored.
475 All instructions set the flags if and only if they have an @code{s}
480 @subsection Special Characters
482 @cindex line comment character, ARM
483 @cindex ARM line comment character
484 The presence of a @samp{@@} anywhere on a line indicates the start of
485 a comment that extends to the end of that line.
487 If a @samp{#} appears as the first character of a line then the whole
488 line is treated as a comment, but in this case the line could also be
489 a logical line number directive (@pxref{Comments}) or a preprocessor
490 control command (@pxref{Preprocessing}).
492 @cindex line separator, ARM
493 @cindex statement separator, ARM
494 @cindex ARM line separator
495 The @samp{;} character can be used instead of a newline to separate
498 @cindex immediate character, ARM
499 @cindex ARM immediate character
500 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
502 @cindex identifiers, ARM
503 @cindex ARM identifiers
504 *TODO* Explain about /data modifier on symbols.
507 @subsection Register Names
509 @cindex ARM register names
510 @cindex register names, ARM
511 *TODO* Explain about ARM register naming, and the predefined names.
513 @node ARM-Relocations
514 @subsection ARM relocation generation
516 @cindex data relocations, ARM
517 @cindex ARM data relocations
518 Specific data relocations can be generated by putting the relocation name
519 in parentheses after the symbol name. For example:
525 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
527 The following relocations are supported:
543 For compatibility with older toolchains the assembler also accepts
544 @code{(PLT)} after branch targets. On legacy targets this will
545 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
546 targets it will encode either the @samp{R_ARM_CALL} or
547 @samp{R_ARM_JUMP24} relocation, as appropriate.
549 @cindex MOVW and MOVT relocations, ARM
550 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
551 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
552 respectively. For example to load the 32-bit address of foo into r0:
555 MOVW r0, #:lower16:foo
556 MOVT r0, #:upper16:foo
559 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
560 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
561 generated by prefixing the value with @samp{#:lower0_7:#},
562 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
563 respectively. For example to load the 32-bit address of foo into r0:
566 MOVS r0, #:upper8_15:#foo
568 ADDS r0, #:upper0_7:#foo
570 ADDS r0, #:lower8_15:#foo
572 ADDS r0, #:lower0_7:#foo
575 @node ARM-Neon-Alignment
576 @subsection NEON Alignment Specifiers
578 @cindex alignment for NEON instructions
579 Some NEON load/store instructions allow an optional address
581 The ARM documentation specifies that this is indicated by
582 @samp{@@ @var{align}}. However GAS already interprets
583 the @samp{@@} character as a "line comment" start,
584 so @samp{: @var{align}} is used instead. For example:
587 vld1.8 @{q0@}, [r0, :128]
590 @node ARM Floating Point
591 @section Floating Point
593 @cindex floating point, ARM (@sc{ieee})
594 @cindex ARM floating point (@sc{ieee})
595 The ARM family uses @sc{ieee} floating-point numbers.
598 @section ARM Machine Directives
600 @cindex machine directives, ARM
601 @cindex ARM machine directives
604 @c AAAAAAAAAAAAAAAAAAAAAAAAA
607 @cindex @code{.2byte} directive, ARM
608 @cindex @code{.4byte} directive, ARM
609 @cindex @code{.8byte} directive, ARM
610 @item .2byte @var{expression} [, @var{expression}]*
611 @itemx .4byte @var{expression} [, @var{expression}]*
612 @itemx .8byte @var{expression} [, @var{expression}]*
613 These directives write 2, 4 or 8 byte values to the output section.
616 @cindex @code{.align} directive, ARM
617 @item .align @var{expression} [, @var{expression}]
618 This is the generic @var{.align} directive. For the ARM however if the
619 first argument is zero (ie no alignment is needed) the assembler will
620 behave as if the argument had been 2 (ie pad to the next four byte
621 boundary). This is for compatibility with ARM's own assembler.
623 @cindex @code{.arch} directive, ARM
624 @item .arch @var{name}
625 Select the target architecture. Valid values for @var{name} are the same as
626 for the @option{-march} commandline option.
628 Specifying @code{.arch} clears any previously selected architecture
631 @cindex @code{.arch_extension} directive, ARM
632 @item .arch_extension @var{name}
633 Add or remove an architecture extension to the target architecture. Valid
634 values for @var{name} are the same as those accepted as architectural
635 extensions by the @option{-mcpu} and @option{-march} commandline options.
637 @code{.arch_extension} may be used multiple times to add or remove extensions
638 incrementally to the architecture being compiled for.
640 @cindex @code{.arm} directive, ARM
642 This performs the same action as @var{.code 32}.
644 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
646 @cindex @code{.bss} directive, ARM
648 This directive switches to the @code{.bss} section.
650 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
652 @cindex @code{.cantunwind} directive, ARM
654 Prevents unwinding through the current function. No personality routine
655 or exception table data is required or permitted.
657 @cindex @code{.code} directive, ARM
658 @item .code @code{[16|32]}
659 This directive selects the instruction set being generated. The value 16
660 selects Thumb, with the value 32 selecting ARM.
662 @cindex @code{.cpu} directive, ARM
663 @item .cpu @var{name}
664 Select the target processor. Valid values for @var{name} are the same as
665 for the @option{-mcpu} commandline option.
667 Specifying @code{.cpu} clears any previously selected architecture
670 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
672 @cindex @code{.dn} and @code{.qn} directives, ARM
673 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
674 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
676 The @code{dn} and @code{qn} directives are used to create typed
677 and/or indexed register aliases for use in Advanced SIMD Extension
678 (Neon) instructions. The former should be used to create aliases
679 of double-precision registers, and the latter to create aliases of
680 quad-precision registers.
682 If these directives are used to create typed aliases, those aliases can
683 be used in Neon instructions instead of writing types after the mnemonic
684 or after each operand. For example:
693 This is equivalent to writing the following:
699 Aliases created using @code{dn} or @code{qn} can be destroyed using
702 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
704 @cindex @code{.eabi_attribute} directive, ARM
705 @item .eabi_attribute @var{tag}, @var{value}
706 Set the EABI object attribute @var{tag} to @var{value}.
708 The @var{tag} is either an attribute number, or one of the following:
709 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
710 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
711 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
712 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
713 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
714 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
715 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
716 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
717 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
718 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
719 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
720 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
721 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
722 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
723 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
724 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
725 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
726 @code{Tag_conformance}, @code{Tag_T2EE_use},
727 @code{Tag_Virtualization_use}
729 The @var{value} is either a @code{number}, @code{"string"}, or
730 @code{number, "string"} depending on the tag.
732 Note - the following legacy values are also accepted by @var{tag}:
733 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
734 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
736 @cindex @code{.even} directive, ARM
738 This directive aligns to an even-numbered address.
740 @cindex @code{.extend} directive, ARM
741 @cindex @code{.ldouble} directive, ARM
742 @item .extend @var{expression} [, @var{expression}]*
743 @itemx .ldouble @var{expression} [, @var{expression}]*
744 These directives write 12byte long double floating-point values to the
745 output section. These are not compatible with current ARM processors
748 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
751 @cindex @code{.fnend} directive, ARM
753 Marks the end of a function with an unwind table entry. The unwind index
754 table entry is created when this directive is processed.
756 If no personality routine has been specified then standard personality
757 routine 0 or 1 will be used, depending on the number of unwind opcodes
761 @cindex @code{.fnstart} directive, ARM
763 Marks the start of a function with an unwind table entry.
765 @cindex @code{.force_thumb} directive, ARM
767 This directive forces the selection of Thumb instructions, even if the
768 target processor does not support those instructions
770 @cindex @code{.fpu} directive, ARM
771 @item .fpu @var{name}
772 Select the floating-point unit to assemble for. Valid values for @var{name}
773 are the same as for the @option{-mfpu} commandline option.
775 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
776 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
778 @cindex @code{.handlerdata} directive, ARM
780 Marks the end of the current function, and the start of the exception table
781 entry for that function. Anything between this directive and the
782 @code{.fnend} directive will be added to the exception table entry.
784 Must be preceded by a @code{.personality} or @code{.personalityindex}
787 @c IIIIIIIIIIIIIIIIIIIIIIIIII
789 @cindex @code{.inst} directive, ARM
790 @item .inst @var{opcode} [ , @dots{} ]
791 @itemx .inst.n @var{opcode} [ , @dots{} ]
792 @itemx .inst.w @var{opcode} [ , @dots{} ]
793 Generates the instruction corresponding to the numerical value @var{opcode}.
794 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
795 specified explicitly, overriding the normal encoding rules.
797 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
798 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
799 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
801 @item .ldouble @var{expression} [, @var{expression}]*
804 @cindex @code{.ltorg} directive, ARM
806 This directive causes the current contents of the literal pool to be
807 dumped into the current section (which is assumed to be the .text
808 section) at the current location (aligned to a word boundary).
809 @code{GAS} maintains a separate literal pool for each section and each
810 sub-section. The @code{.ltorg} directive will only affect the literal
811 pool of the current section and sub-section. At the end of assembly
812 all remaining, un-empty literal pools will automatically be dumped.
814 Note - older versions of @code{GAS} would dump the current literal
815 pool any time a section change occurred. This is no longer done, since
816 it prevents accurate control of the placement of literal pools.
818 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
820 @cindex @code{.movsp} directive, ARM
821 @item .movsp @var{reg} [, #@var{offset}]
822 Tell the unwinder that @var{reg} contains an offset from the current
823 stack pointer. If @var{offset} is not specified then it is assumed to be
826 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
827 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
829 @cindex @code{.object_arch} directive, ARM
830 @item .object_arch @var{name}
831 Override the architecture recorded in the EABI object attribute section.
832 Valid values for @var{name} are the same as for the @code{.arch} directive.
833 Typically this is useful when code uses runtime detection of CPU features.
835 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
837 @cindex @code{.packed} directive, ARM
838 @item .packed @var{expression} [, @var{expression}]*
839 This directive writes 12-byte packed floating-point values to the
840 output section. These are not compatible with current ARM processors
844 @cindex @code{.pad} directive, ARM
845 @item .pad #@var{count}
846 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
847 A positive value indicates the function prologue allocated stack space by
848 decrementing the stack pointer.
850 @cindex @code{.personality} directive, ARM
851 @item .personality @var{name}
852 Sets the personality routine for the current function to @var{name}.
854 @cindex @code{.personalityindex} directive, ARM
855 @item .personalityindex @var{index}
856 Sets the personality routine for the current function to the EABI standard
857 routine number @var{index}
859 @cindex @code{.pool} directive, ARM
861 This is a synonym for .ltorg.
863 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
864 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
866 @cindex @code{.req} directive, ARM
867 @item @var{name} .req @var{register name}
868 This creates an alias for @var{register name} called @var{name}. For
875 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
878 @cindex @code{.save} directive, ARM
879 @item .save @var{reglist}
880 Generate unwinder annotations to restore the registers in @var{reglist}.
881 The format of @var{reglist} is the same as the corresponding store-multiple
885 @exdent @emph{core registers}
886 .save @{r4, r5, r6, lr@}
887 stmfd sp!, @{r4, r5, r6, lr@}
888 @exdent @emph{FPA registers}
891 @exdent @emph{VFP registers}
892 .save @{d8, d9, d10@}
893 fstmdx sp!, @{d8, d9, d10@}
894 @exdent @emph{iWMMXt registers}
896 wstrd wr11, [sp, #-8]!
897 wstrd wr10, [sp, #-8]!
900 wstrd wr11, [sp, #-8]!
902 wstrd wr10, [sp, #-8]!
906 @cindex @code{.setfp} directive, ARM
907 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
908 Make all unwinder annotations relative to a frame pointer. Without this
909 the unwinder will use offsets from the stack pointer.
911 The syntax of this directive is the same as the @code{add} or @code{mov}
912 instruction used to set the frame pointer. @var{spreg} must be either
913 @code{sp} or mentioned in a previous @code{.movsp} directive.
923 @cindex @code{.secrel32} directive, ARM
924 @item .secrel32 @var{expression} [, @var{expression}]*
925 This directive emits relocations that evaluate to the section-relative
926 offset of each expression's symbol. This directive is only supported
929 @cindex @code{.syntax} directive, ARM
930 @item .syntax [@code{unified} | @code{divided}]
931 This directive sets the Instruction Set Syntax as described in the
932 @ref{ARM-Instruction-Set} section.
934 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
936 @cindex @code{.thumb} directive, ARM
938 This performs the same action as @var{.code 16}.
940 @cindex @code{.thumb_func} directive, ARM
942 This directive specifies that the following symbol is the name of a
943 Thumb encoded function. This information is necessary in order to allow
944 the assembler and linker to generate correct code for interworking
945 between Arm and Thumb instructions and should be used even if
946 interworking is not going to be performed. The presence of this
947 directive also implies @code{.thumb}
949 This directive is not necessary when generating EABI objects. On these
950 targets the encoding is implicit when generating Thumb code.
952 @cindex @code{.thumb_set} directive, ARM
954 This performs the equivalent of a @code{.set} directive in that it
955 creates a symbol which is an alias for another symbol (possibly not yet
956 defined). This directive also has the added property in that it marks
957 the aliased symbol as being a thumb function entry point, in the same
958 way that the @code{.thumb_func} directive does.
960 @cindex @code{.tlsdescseq} directive, ARM
961 @item .tlsdescseq @var{tls-variable}
962 This directive is used to annotate parts of an inlined TLS descriptor
963 trampoline. Normally the trampoline is provided by the linker, and
964 this directive is not needed.
966 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
968 @cindex @code{.unreq} directive, ARM
969 @item .unreq @var{alias-name}
970 This undefines a register alias which was previously defined using the
971 @code{req}, @code{dn} or @code{qn} directives. For example:
978 An error occurs if the name is undefined. Note - this pseudo op can
979 be used to delete builtin in register name aliases (eg 'r0'). This
980 should only be done if it is really necessary.
982 @cindex @code{.unwind_raw} directive, ARM
983 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
984 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
985 the stack pointer by @var{offset} bytes.
987 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
990 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
992 @cindex @code{.vsave} directive, ARM
993 @item .vsave @var{vfp-reglist}
994 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
995 using FLDMD. Also works for VFPv3 registers
996 that are to be restored using VLDM.
997 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1001 @exdent @emph{VFP registers}
1002 .vsave @{d8, d9, d10@}
1003 fstmdd sp!, @{d8, d9, d10@}
1004 @exdent @emph{VFPv3 registers}
1005 .vsave @{d15, d16, d17@}
1006 vstm sp!, @{d15, d16, d17@}
1009 Since FLDMX and FSTMX are now deprecated, this directive should be
1010 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1012 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1013 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1014 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1015 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1023 @cindex opcodes for ARM
1024 @code{@value{AS}} implements all the standard ARM opcodes. It also
1025 implements several pseudo opcodes, including several synthetic load
1030 @cindex @code{NOP} pseudo op, ARM
1036 This pseudo op will always evaluate to a legal ARM instruction that does
1037 nothing. Currently it will evaluate to MOV r0, r0.
1039 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1042 ldr <register> , = <expression>
1045 If expression evaluates to a numeric constant then a MOV or MVN
1046 instruction will be used in place of the LDR instruction, if the
1047 constant can be generated by either of these instructions. Otherwise
1048 the constant will be placed into the nearest literal pool (if it not
1049 already there) and a PC relative LDR instruction will be generated.
1051 @cindex @code{ADR reg,<label>} pseudo op, ARM
1054 adr <register> <label>
1057 This instruction will load the address of @var{label} into the indicated
1058 register. The instruction will evaluate to a PC relative ADD or SUB
1059 instruction depending upon where the label is located. If the label is
1060 out of range, or if it is not defined in the same file (and section) as
1061 the ADR instruction, then an error will be generated. This instruction
1062 will not make use of the literal pool.
1064 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1067 adrl <register> <label>
1070 This instruction will load the address of @var{label} into the indicated
1071 register. The instruction will evaluate to one or two PC relative ADD
1072 or SUB instructions depending upon where the label is located. If a
1073 second instruction is not needed a NOP instruction will be generated in
1074 its place, so that this instruction is always 8 bytes long.
1076 If the label is out of range, or if it is not defined in the same file
1077 (and section) as the ADRL instruction, then an error will be generated.
1078 This instruction will not make use of the literal pool.
1082 For information on the ARM or Thumb instruction sets, see @cite{ARM
1083 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1086 @node ARM Mapping Symbols
1087 @section Mapping Symbols
1089 The ARM ELF specification requires that special symbols be inserted
1090 into object files to mark certain features:
1096 At the start of a region of code containing ARM instructions.
1100 At the start of a region of code containing THUMB instructions.
1104 At the start of a region of data.
1108 The assembler will automatically insert these symbols for you - there
1109 is no need to code them yourself. Support for tagging symbols ($b,
1110 $f, $p and $m) which is also mentioned in the current ARM ELF
1111 specification is not implemented. This is because they have been
1112 dropped from the new EABI and so tools cannot rely upon their
1115 @node ARM Unwinding Tutorial
1118 The ABI for the ARM Architecture specifies a standard format for
1119 exception unwind information. This information is used when an
1120 exception is thrown to determine where control should be transferred.
1121 In particular, the unwind information is used to determine which
1122 function called the function that threw the exception, and which
1123 function called that one, and so forth. This information is also used
1124 to restore the values of callee-saved registers in the function
1125 catching the exception.
1127 If you are writing functions in assembly code, and those functions
1128 call other functions that throw exceptions, you must use assembly
1129 pseudo ops to ensure that appropriate exception unwind information is
1130 generated. Otherwise, if one of the functions called by your assembly
1131 code throws an exception, the run-time library will be unable to
1132 unwind the stack through your assembly code and your program will not
1135 To illustrate the use of these pseudo ops, we will examine the code
1136 that G++ generates for the following C++ input:
1139 void callee (int *);
1150 This example does not show how to throw or catch an exception from
1151 assembly code. That is a much more complex operation and should
1152 always be done in a high-level language, such as C++, that directly
1153 supports exceptions.
1155 The code generated by one particular version of G++ when compiling the
1162 @ Function supports interworking.
1163 @ args = 0, pretend = 0, frame = 8
1164 @ frame_needed = 1, uses_anonymous_args = 0
1186 Of course, the sequence of instructions varies based on the options
1187 you pass to GCC and on the version of GCC in use. The exact
1188 instructions are not important since we are focusing on the pseudo ops
1189 that are used to generate unwind information.
1191 An important assumption made by the unwinder is that the stack frame
1192 does not change during the body of the function. In particular, since
1193 we assume that the assembly code does not itself throw an exception,
1194 the only point where an exception can be thrown is from a call, such
1195 as the @code{bl} instruction above. At each call site, the same saved
1196 registers (including @code{lr}, which indicates the return address)
1197 must be located in the same locations relative to the frame pointer.
1199 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1200 op appears immediately before the first instruction of the function
1201 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1202 op appears immediately after the last instruction of the function.
1203 These pseudo ops specify the range of the function.
1205 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1206 @code{.pad}) matters; their exact locations are irrelevant. In the
1207 example above, the compiler emits the pseudo ops with particular
1208 instructions. That makes it easier to understand the code, but it is
1209 not required for correctness. It would work just as well to emit all
1210 of the pseudo ops other than @code{.fnend} in the same order, but
1211 immediately after @code{.fnstart}.
1213 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1214 indicates registers that have been saved to the stack so that they can
1215 be restored before the function returns. The argument to the
1216 @code{.save} pseudo op is a list of registers to save. If a register
1217 is ``callee-saved'' (as specified by the ABI) and is modified by the
1218 function you are writing, then your code must save the value before it
1219 is modified and restore the original value before the function
1220 returns. If an exception is thrown, the run-time library restores the
1221 values of these registers from their locations on the stack before
1222 returning control to the exception handler. (Of course, if an
1223 exception is not thrown, the function that contains the @code{.save}
1224 pseudo op restores these registers in the function epilogue, as is
1225 done with the @code{ldmfd} instruction above.)
1227 You do not have to save callee-saved registers at the very beginning
1228 of the function and you do not need to use the @code{.save} pseudo op
1229 immediately following the point at which the registers are saved.
1230 However, if you modify a callee-saved register, you must save it on
1231 the stack before modifying it and before calling any functions which
1232 might throw an exception. And, you must use the @code{.save} pseudo
1233 op to indicate that you have done so.
1235 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1236 modification of the stack pointer that does not save any registers.
1237 The argument is the number of bytes (in decimal) that are subtracted
1238 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1239 subtracting from the stack pointer increases the size of the stack.)
1241 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1242 indicates the register that contains the frame pointer. The first
1243 argument is the register that is set, which is typically @code{fp}.
1244 The second argument indicates the register from which the frame
1245 pointer takes its value. The third argument, if present, is the value
1246 (in decimal) added to the register specified by the second argument to
1247 compute the value of the frame pointer. You should not modify the
1248 frame pointer in the body of the function.
1250 If you do not use a frame pointer, then you should not use the
1251 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1252 should avoid modifying the stack pointer outside of the function
1253 prologue. Otherwise, the run-time library will be unable to find
1254 saved registers when it is unwinding the stack.
1256 The pseudo ops described above are sufficient for writing assembly
1257 code that calls functions which may throw exceptions. If you need to
1258 know more about the object-file format used to represent unwind
1259 information, you may consult the @cite{Exception Handling ABI for the
1260 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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