1 @c Copyright (C) 1996-2018 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
145 @code{cortex-m0plus},
148 @code{marvell-whitney},
151 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
152 @code{i80200} (Intel XScale processor)
153 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
156 The special name @code{all} may be used to allow the
157 assembler to accept instructions valid for any ARM processor.
159 In addition to the basic instruction set, the assembler can be told to
160 accept various extension mnemonics that extend the processor using the
161 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
162 is equivalent to specifying @code{-mcpu=ep9312}.
164 Multiple extensions may be specified, separated by a @code{+}. The
165 extensions should be specified in ascending alphabetical order.
167 Some extensions may be restricted to particular architectures; this is
168 documented in the list of extensions below.
170 Extension mnemonics may also be removed from those the assembler accepts.
171 This is done be prepending @code{no} to the option that adds the extension.
172 Extensions that are removed should be listed after all extensions which have
173 been added, again in ascending alphabetical order. For example,
174 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
177 The following extensions are currently supported:
179 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
180 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
181 @code{fp} (Floating Point Extensions for v8-A architecture),
182 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
183 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
184 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
189 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
191 @code{os} (Operating System for v6M architecture),
192 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
193 default from v8.5-A),
194 @code{sec} (Security Extensions for v6K and v7-A architectures),
195 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
196 @code{virt} (Virtualization Extensions for v7-A architecture, implies
198 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
199 @code{ras} (Reliability, Availability and Serviceability extensions
200 for v8-A architecture),
201 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
206 @cindex @code{-march=} command-line option, ARM
207 @item -march=@var{architecture}[+@var{extension}@dots{}]
208 This option specifies the target architecture. The assembler will issue
209 an error message if an attempt is made to assemble an instruction which
210 will not execute on the target architecture. The following architecture
211 names are recognized:
251 If both @code{-mcpu} and
252 @code{-march} are specified, the assembler will use
253 the setting for @code{-mcpu}.
255 The architecture option can be extended with the same instruction set
256 extension options as the @code{-mcpu} option.
258 @cindex @code{-mfpu=} command-line option, ARM
259 @item -mfpu=@var{floating-point-format}
261 This option specifies the floating point format to assemble for. The
262 assembler will issue an error message if an attempt is made to assemble
263 an instruction which will not execute on the target floating point unit.
264 The following format options are recognized:
284 @code{vfpv3-d16-fp16},
301 @code{neon-fp-armv8},
302 @code{crypto-neon-fp-armv8},
303 @code{neon-fp-armv8.1}
305 @code{crypto-neon-fp-armv8.1}.
307 In addition to determining which instructions are assembled, this option
308 also affects the way in which the @code{.double} assembler directive behaves
309 when assembling little-endian code.
311 The default is dependent on the processor selected. For Architecture 5 or
312 later, the default is to assemble for VFP instructions; for earlier
313 architectures the default is to assemble for FPA instructions.
315 @cindex @code{-mthumb} command-line option, ARM
317 This option specifies that the assembler should start assembling Thumb
318 instructions; that is, it should behave as though the file starts with a
319 @code{.code 16} directive.
321 @cindex @code{-mthumb-interwork} command-line option, ARM
322 @item -mthumb-interwork
323 This option specifies that the output generated by the assembler should
324 be marked as supporting interworking. It also affects the behaviour
325 of the @code{ADR} and @code{ADRL} pseudo opcodes.
327 @cindex @code{-mimplicit-it} command-line option, ARM
328 @item -mimplicit-it=never
329 @itemx -mimplicit-it=always
330 @itemx -mimplicit-it=arm
331 @itemx -mimplicit-it=thumb
332 The @code{-mimplicit-it} option controls the behavior of the assembler when
333 conditional instructions are not enclosed in IT blocks.
334 There are four possible behaviors.
335 If @code{never} is specified, such constructs cause a warning in ARM
336 code and an error in Thumb-2 code.
337 If @code{always} is specified, such constructs are accepted in both
338 ARM and Thumb-2 code, where the IT instruction is added implicitly.
339 If @code{arm} is specified, such constructs are accepted in ARM code
340 and cause an error in Thumb-2 code.
341 If @code{thumb} is specified, such constructs cause a warning in ARM
342 code and are accepted in Thumb-2 code. If you omit this option, the
343 behavior is equivalent to @code{-mimplicit-it=arm}.
345 @cindex @code{-mapcs-26} command-line option, ARM
346 @cindex @code{-mapcs-32} command-line option, ARM
349 These options specify that the output generated by the assembler should
350 be marked as supporting the indicated version of the Arm Procedure.
353 @cindex @code{-matpcs} command-line option, ARM
355 This option specifies that the output generated by the assembler should
356 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
357 enabled this option will cause the assembler to create an empty
358 debugging section in the object file called .arm.atpcs. Debuggers can
359 use this to determine the ABI being used by.
361 @cindex @code{-mapcs-float} command-line option, ARM
363 This indicates the floating point variant of the APCS should be
364 used. In this variant floating point arguments are passed in FP
365 registers rather than integer registers.
367 @cindex @code{-mapcs-reentrant} command-line option, ARM
368 @item -mapcs-reentrant
369 This indicates that the reentrant variant of the APCS should be used.
370 This variant supports position independent code.
372 @cindex @code{-mfloat-abi=} command-line option, ARM
373 @item -mfloat-abi=@var{abi}
374 This option specifies that the output generated by the assembler should be
375 marked as using specified floating point ABI.
376 The following values are recognized:
382 @cindex @code{-eabi=} command-line option, ARM
383 @item -meabi=@var{ver}
384 This option specifies which EABI version the produced object files should
386 The following values are recognized:
392 @cindex @code{-EB} command-line option, ARM
394 This option specifies that the output generated by the assembler should
395 be marked as being encoded for a big-endian processor.
397 Note: If a program is being built for a system with big-endian data
398 and little-endian instructions then it should be assembled with the
399 @option{-EB} option, (all of it, code and data) and then linked with
400 the @option{--be8} option. This will reverse the endianness of the
401 instructions back to little-endian, but leave the data as big-endian.
403 @cindex @code{-EL} command-line option, ARM
405 This option specifies that the output generated by the assembler should
406 be marked as being encoded for a little-endian processor.
408 @cindex @code{-k} command-line option, ARM
409 @cindex PIC code generation for ARM
411 This option specifies that the output of the assembler should be marked
412 as position-independent code (PIC).
414 @cindex @code{--fix-v4bx} command-line option, ARM
416 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
417 the linker option of the same name.
419 @cindex @code{-mwarn-deprecated} command-line option, ARM
420 @item -mwarn-deprecated
421 @itemx -mno-warn-deprecated
422 Enable or disable warnings about using deprecated options or
423 features. The default is to warn.
425 @cindex @code{-mccs} command-line option, ARM
427 Turns on CodeComposer Studio assembly syntax compatibility mode.
429 @cindex @code{-mwarn-syms} command-line option, ARM
431 @itemx -mno-warn-syms
432 Enable or disable warnings about symbols that match the names of ARM
433 instructions. The default is to warn.
441 * ARM-Instruction-Set:: Instruction Set
442 * ARM-Chars:: Special Characters
443 * ARM-Regs:: Register Names
444 * ARM-Relocations:: Relocations
445 * ARM-Neon-Alignment:: NEON Alignment Specifiers
448 @node ARM-Instruction-Set
449 @subsection Instruction Set Syntax
450 Two slightly different syntaxes are support for ARM and THUMB
451 instructions. The default, @code{divided}, uses the old style where
452 ARM and THUMB instructions had their own, separate syntaxes. The new,
453 @code{unified} syntax, which can be selected via the @code{.syntax}
454 directive, and has the following main features:
458 Immediate operands do not require a @code{#} prefix.
461 The @code{IT} instruction may appear, and if it does it is validated
462 against subsequent conditional affixes. In ARM mode it does not
463 generate machine code, in THUMB mode it does.
466 For ARM instructions the conditional affixes always appear at the end
467 of the instruction. For THUMB instructions conditional affixes can be
468 used, but only inside the scope of an @code{IT} instruction.
471 All of the instructions new to the V6T2 architecture (and later) are
472 available. (Only a few such instructions can be written in the
473 @code{divided} syntax).
476 The @code{.N} and @code{.W} suffixes are recognized and honored.
479 All instructions set the flags if and only if they have an @code{s}
484 @subsection Special Characters
486 @cindex line comment character, ARM
487 @cindex ARM line comment character
488 The presence of a @samp{@@} anywhere on a line indicates the start of
489 a comment that extends to the end of that line.
491 If a @samp{#} appears as the first character of a line then the whole
492 line is treated as a comment, but in this case the line could also be
493 a logical line number directive (@pxref{Comments}) or a preprocessor
494 control command (@pxref{Preprocessing}).
496 @cindex line separator, ARM
497 @cindex statement separator, ARM
498 @cindex ARM line separator
499 The @samp{;} character can be used instead of a newline to separate
502 @cindex immediate character, ARM
503 @cindex ARM immediate character
504 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
506 @cindex identifiers, ARM
507 @cindex ARM identifiers
508 *TODO* Explain about /data modifier on symbols.
511 @subsection Register Names
513 @cindex ARM register names
514 @cindex register names, ARM
515 *TODO* Explain about ARM register naming, and the predefined names.
517 @node ARM-Relocations
518 @subsection ARM relocation generation
520 @cindex data relocations, ARM
521 @cindex ARM data relocations
522 Specific data relocations can be generated by putting the relocation name
523 in parentheses after the symbol name. For example:
529 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
531 The following relocations are supported:
547 For compatibility with older toolchains the assembler also accepts
548 @code{(PLT)} after branch targets. On legacy targets this will
549 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
550 targets it will encode either the @samp{R_ARM_CALL} or
551 @samp{R_ARM_JUMP24} relocation, as appropriate.
553 @cindex MOVW and MOVT relocations, ARM
554 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
555 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
556 respectively. For example to load the 32-bit address of foo into r0:
559 MOVW r0, #:lower16:foo
560 MOVT r0, #:upper16:foo
563 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
564 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
565 generated by prefixing the value with @samp{#:lower0_7:#},
566 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
567 respectively. For example to load the 32-bit address of foo into r0:
570 MOVS r0, #:upper8_15:#foo
572 ADDS r0, #:upper0_7:#foo
574 ADDS r0, #:lower8_15:#foo
576 ADDS r0, #:lower0_7:#foo
579 @node ARM-Neon-Alignment
580 @subsection NEON Alignment Specifiers
582 @cindex alignment for NEON instructions
583 Some NEON load/store instructions allow an optional address
585 The ARM documentation specifies that this is indicated by
586 @samp{@@ @var{align}}. However GAS already interprets
587 the @samp{@@} character as a "line comment" start,
588 so @samp{: @var{align}} is used instead. For example:
591 vld1.8 @{q0@}, [r0, :128]
594 @node ARM Floating Point
595 @section Floating Point
597 @cindex floating point, ARM (@sc{ieee})
598 @cindex ARM floating point (@sc{ieee})
599 The ARM family uses @sc{ieee} floating-point numbers.
602 @section ARM Machine Directives
604 @cindex machine directives, ARM
605 @cindex ARM machine directives
608 @c AAAAAAAAAAAAAAAAAAAAAAAAA
611 @cindex @code{.2byte} directive, ARM
612 @cindex @code{.4byte} directive, ARM
613 @cindex @code{.8byte} directive, ARM
614 @item .2byte @var{expression} [, @var{expression}]*
615 @itemx .4byte @var{expression} [, @var{expression}]*
616 @itemx .8byte @var{expression} [, @var{expression}]*
617 These directives write 2, 4 or 8 byte values to the output section.
620 @cindex @code{.align} directive, ARM
621 @item .align @var{expression} [, @var{expression}]
622 This is the generic @var{.align} directive. For the ARM however if the
623 first argument is zero (ie no alignment is needed) the assembler will
624 behave as if the argument had been 2 (ie pad to the next four byte
625 boundary). This is for compatibility with ARM's own assembler.
627 @cindex @code{.arch} directive, ARM
628 @item .arch @var{name}
629 Select the target architecture. Valid values for @var{name} are the same as
630 for the @option{-march} command-line option without the instruction set
633 Specifying @code{.arch} clears any previously selected architecture
636 @cindex @code{.arch_extension} directive, ARM
637 @item .arch_extension @var{name}
638 Add or remove an architecture extension to the target architecture. Valid
639 values for @var{name} are the same as those accepted as architectural
640 extensions by the @option{-mcpu} and @option{-march} command-line options.
642 @code{.arch_extension} may be used multiple times to add or remove extensions
643 incrementally to the architecture being compiled for.
645 @cindex @code{.arm} directive, ARM
647 This performs the same action as @var{.code 32}.
649 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
651 @cindex @code{.bss} directive, ARM
653 This directive switches to the @code{.bss} section.
655 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
657 @cindex @code{.cantunwind} directive, ARM
659 Prevents unwinding through the current function. No personality routine
660 or exception table data is required or permitted.
662 @cindex @code{.code} directive, ARM
663 @item .code @code{[16|32]}
664 This directive selects the instruction set being generated. The value 16
665 selects Thumb, with the value 32 selecting ARM.
667 @cindex @code{.cpu} directive, ARM
668 @item .cpu @var{name}
669 Select the target processor. Valid values for @var{name} are the same as
670 for the @option{-mcpu} command-line option without the instruction set
673 Specifying @code{.cpu} clears any previously selected architecture
676 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
678 @cindex @code{.dn} and @code{.qn} directives, ARM
679 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
680 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
682 The @code{dn} and @code{qn} directives are used to create typed
683 and/or indexed register aliases for use in Advanced SIMD Extension
684 (Neon) instructions. The former should be used to create aliases
685 of double-precision registers, and the latter to create aliases of
686 quad-precision registers.
688 If these directives are used to create typed aliases, those aliases can
689 be used in Neon instructions instead of writing types after the mnemonic
690 or after each operand. For example:
699 This is equivalent to writing the following:
705 Aliases created using @code{dn} or @code{qn} can be destroyed using
708 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
710 @cindex @code{.eabi_attribute} directive, ARM
711 @item .eabi_attribute @var{tag}, @var{value}
712 Set the EABI object attribute @var{tag} to @var{value}.
714 The @var{tag} is either an attribute number, or one of the following:
715 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
716 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
717 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
718 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
719 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
720 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
721 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
722 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
723 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
724 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
725 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
726 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
727 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
728 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
729 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
730 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
731 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
732 @code{Tag_conformance}, @code{Tag_T2EE_use},
733 @code{Tag_Virtualization_use}
735 The @var{value} is either a @code{number}, @code{"string"}, or
736 @code{number, "string"} depending on the tag.
738 Note - the following legacy values are also accepted by @var{tag}:
739 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
740 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
742 @cindex @code{.even} directive, ARM
744 This directive aligns to an even-numbered address.
746 @cindex @code{.extend} directive, ARM
747 @cindex @code{.ldouble} directive, ARM
748 @item .extend @var{expression} [, @var{expression}]*
749 @itemx .ldouble @var{expression} [, @var{expression}]*
750 These directives write 12byte long double floating-point values to the
751 output section. These are not compatible with current ARM processors
754 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
757 @cindex @code{.fnend} directive, ARM
759 Marks the end of a function with an unwind table entry. The unwind index
760 table entry is created when this directive is processed.
762 If no personality routine has been specified then standard personality
763 routine 0 or 1 will be used, depending on the number of unwind opcodes
767 @cindex @code{.fnstart} directive, ARM
769 Marks the start of a function with an unwind table entry.
771 @cindex @code{.force_thumb} directive, ARM
773 This directive forces the selection of Thumb instructions, even if the
774 target processor does not support those instructions
776 @cindex @code{.fpu} directive, ARM
777 @item .fpu @var{name}
778 Select the floating-point unit to assemble for. Valid values for @var{name}
779 are the same as for the @option{-mfpu} command-line option.
781 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
782 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
784 @cindex @code{.handlerdata} directive, ARM
786 Marks the end of the current function, and the start of the exception table
787 entry for that function. Anything between this directive and the
788 @code{.fnend} directive will be added to the exception table entry.
790 Must be preceded by a @code{.personality} or @code{.personalityindex}
793 @c IIIIIIIIIIIIIIIIIIIIIIIIII
795 @cindex @code{.inst} directive, ARM
796 @item .inst @var{opcode} [ , @dots{} ]
797 @itemx .inst.n @var{opcode} [ , @dots{} ]
798 @itemx .inst.w @var{opcode} [ , @dots{} ]
799 Generates the instruction corresponding to the numerical value @var{opcode}.
800 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
801 specified explicitly, overriding the normal encoding rules.
803 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
804 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
805 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
807 @item .ldouble @var{expression} [, @var{expression}]*
810 @cindex @code{.ltorg} directive, ARM
812 This directive causes the current contents of the literal pool to be
813 dumped into the current section (which is assumed to be the .text
814 section) at the current location (aligned to a word boundary).
815 @code{GAS} maintains a separate literal pool for each section and each
816 sub-section. The @code{.ltorg} directive will only affect the literal
817 pool of the current section and sub-section. At the end of assembly
818 all remaining, un-empty literal pools will automatically be dumped.
820 Note - older versions of @code{GAS} would dump the current literal
821 pool any time a section change occurred. This is no longer done, since
822 it prevents accurate control of the placement of literal pools.
824 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
826 @cindex @code{.movsp} directive, ARM
827 @item .movsp @var{reg} [, #@var{offset}]
828 Tell the unwinder that @var{reg} contains an offset from the current
829 stack pointer. If @var{offset} is not specified then it is assumed to be
832 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
833 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
835 @cindex @code{.object_arch} directive, ARM
836 @item .object_arch @var{name}
837 Override the architecture recorded in the EABI object attribute section.
838 Valid values for @var{name} are the same as for the @code{.arch} directive.
839 Typically this is useful when code uses runtime detection of CPU features.
841 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
843 @cindex @code{.packed} directive, ARM
844 @item .packed @var{expression} [, @var{expression}]*
845 This directive writes 12-byte packed floating-point values to the
846 output section. These are not compatible with current ARM processors
850 @cindex @code{.pad} directive, ARM
851 @item .pad #@var{count}
852 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
853 A positive value indicates the function prologue allocated stack space by
854 decrementing the stack pointer.
856 @cindex @code{.personality} directive, ARM
857 @item .personality @var{name}
858 Sets the personality routine for the current function to @var{name}.
860 @cindex @code{.personalityindex} directive, ARM
861 @item .personalityindex @var{index}
862 Sets the personality routine for the current function to the EABI standard
863 routine number @var{index}
865 @cindex @code{.pool} directive, ARM
867 This is a synonym for .ltorg.
869 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
870 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
872 @cindex @code{.req} directive, ARM
873 @item @var{name} .req @var{register name}
874 This creates an alias for @var{register name} called @var{name}. For
881 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
884 @cindex @code{.save} directive, ARM
885 @item .save @var{reglist}
886 Generate unwinder annotations to restore the registers in @var{reglist}.
887 The format of @var{reglist} is the same as the corresponding store-multiple
891 @exdent @emph{core registers}
892 .save @{r4, r5, r6, lr@}
893 stmfd sp!, @{r4, r5, r6, lr@}
894 @exdent @emph{FPA registers}
897 @exdent @emph{VFP registers}
898 .save @{d8, d9, d10@}
899 fstmdx sp!, @{d8, d9, d10@}
900 @exdent @emph{iWMMXt registers}
902 wstrd wr11, [sp, #-8]!
903 wstrd wr10, [sp, #-8]!
906 wstrd wr11, [sp, #-8]!
908 wstrd wr10, [sp, #-8]!
912 @cindex @code{.setfp} directive, ARM
913 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
914 Make all unwinder annotations relative to a frame pointer. Without this
915 the unwinder will use offsets from the stack pointer.
917 The syntax of this directive is the same as the @code{add} or @code{mov}
918 instruction used to set the frame pointer. @var{spreg} must be either
919 @code{sp} or mentioned in a previous @code{.movsp} directive.
929 @cindex @code{.secrel32} directive, ARM
930 @item .secrel32 @var{expression} [, @var{expression}]*
931 This directive emits relocations that evaluate to the section-relative
932 offset of each expression's symbol. This directive is only supported
935 @cindex @code{.syntax} directive, ARM
936 @item .syntax [@code{unified} | @code{divided}]
937 This directive sets the Instruction Set Syntax as described in the
938 @ref{ARM-Instruction-Set} section.
940 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
942 @cindex @code{.thumb} directive, ARM
944 This performs the same action as @var{.code 16}.
946 @cindex @code{.thumb_func} directive, ARM
948 This directive specifies that the following symbol is the name of a
949 Thumb encoded function. This information is necessary in order to allow
950 the assembler and linker to generate correct code for interworking
951 between Arm and Thumb instructions and should be used even if
952 interworking is not going to be performed. The presence of this
953 directive also implies @code{.thumb}
955 This directive is not necessary when generating EABI objects. On these
956 targets the encoding is implicit when generating Thumb code.
958 @cindex @code{.thumb_set} directive, ARM
960 This performs the equivalent of a @code{.set} directive in that it
961 creates a symbol which is an alias for another symbol (possibly not yet
962 defined). This directive also has the added property in that it marks
963 the aliased symbol as being a thumb function entry point, in the same
964 way that the @code{.thumb_func} directive does.
966 @cindex @code{.tlsdescseq} directive, ARM
967 @item .tlsdescseq @var{tls-variable}
968 This directive is used to annotate parts of an inlined TLS descriptor
969 trampoline. Normally the trampoline is provided by the linker, and
970 this directive is not needed.
972 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
974 @cindex @code{.unreq} directive, ARM
975 @item .unreq @var{alias-name}
976 This undefines a register alias which was previously defined using the
977 @code{req}, @code{dn} or @code{qn} directives. For example:
984 An error occurs if the name is undefined. Note - this pseudo op can
985 be used to delete builtin in register name aliases (eg 'r0'). This
986 should only be done if it is really necessary.
988 @cindex @code{.unwind_raw} directive, ARM
989 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
990 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
991 the stack pointer by @var{offset} bytes.
993 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
996 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
998 @cindex @code{.vsave} directive, ARM
999 @item .vsave @var{vfp-reglist}
1000 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1001 using FLDMD. Also works for VFPv3 registers
1002 that are to be restored using VLDM.
1003 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1007 @exdent @emph{VFP registers}
1008 .vsave @{d8, d9, d10@}
1009 fstmdd sp!, @{d8, d9, d10@}
1010 @exdent @emph{VFPv3 registers}
1011 .vsave @{d15, d16, d17@}
1012 vstm sp!, @{d15, d16, d17@}
1015 Since FLDMX and FSTMX are now deprecated, this directive should be
1016 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1018 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1019 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1020 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1021 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1029 @cindex opcodes for ARM
1030 @code{@value{AS}} implements all the standard ARM opcodes. It also
1031 implements several pseudo opcodes, including several synthetic load
1036 @cindex @code{NOP} pseudo op, ARM
1042 This pseudo op will always evaluate to a legal ARM instruction that does
1043 nothing. Currently it will evaluate to MOV r0, r0.
1045 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1048 ldr <register> , = <expression>
1051 If expression evaluates to a numeric constant then a MOV or MVN
1052 instruction will be used in place of the LDR instruction, if the
1053 constant can be generated by either of these instructions. Otherwise
1054 the constant will be placed into the nearest literal pool (if it not
1055 already there) and a PC relative LDR instruction will be generated.
1057 @cindex @code{ADR reg,<label>} pseudo op, ARM
1060 adr <register> <label>
1063 This instruction will load the address of @var{label} into the indicated
1064 register. The instruction will evaluate to a PC relative ADD or SUB
1065 instruction depending upon where the label is located. If the label is
1066 out of range, or if it is not defined in the same file (and section) as
1067 the ADR instruction, then an error will be generated. This instruction
1068 will not make use of the literal pool.
1070 If @var{label} is a thumb function symbol, and thumb interworking has
1071 been enabled via the @option{-mthumb-interwork} option then the bottom
1072 bit of the value stored into @var{register} will be set. This allows
1073 the following sequence to work as expected:
1076 adr r0, thumb_function
1080 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1083 adrl <register> <label>
1086 This instruction will load the address of @var{label} into the indicated
1087 register. The instruction will evaluate to one or two PC relative ADD
1088 or SUB instructions depending upon where the label is located. If a
1089 second instruction is not needed a NOP instruction will be generated in
1090 its place, so that this instruction is always 8 bytes long.
1092 If the label is out of range, or if it is not defined in the same file
1093 (and section) as the ADRL instruction, then an error will be generated.
1094 This instruction will not make use of the literal pool.
1096 If @var{label} is a thumb function symbol, and thumb interworking has
1097 been enabled via the @option{-mthumb-interwork} option then the bottom
1098 bit of the value stored into @var{register} will be set.
1102 For information on the ARM or Thumb instruction sets, see @cite{ARM
1103 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1106 @node ARM Mapping Symbols
1107 @section Mapping Symbols
1109 The ARM ELF specification requires that special symbols be inserted
1110 into object files to mark certain features:
1116 At the start of a region of code containing ARM instructions.
1120 At the start of a region of code containing THUMB instructions.
1124 At the start of a region of data.
1128 The assembler will automatically insert these symbols for you - there
1129 is no need to code them yourself. Support for tagging symbols ($b,
1130 $f, $p and $m) which is also mentioned in the current ARM ELF
1131 specification is not implemented. This is because they have been
1132 dropped from the new EABI and so tools cannot rely upon their
1135 @node ARM Unwinding Tutorial
1138 The ABI for the ARM Architecture specifies a standard format for
1139 exception unwind information. This information is used when an
1140 exception is thrown to determine where control should be transferred.
1141 In particular, the unwind information is used to determine which
1142 function called the function that threw the exception, and which
1143 function called that one, and so forth. This information is also used
1144 to restore the values of callee-saved registers in the function
1145 catching the exception.
1147 If you are writing functions in assembly code, and those functions
1148 call other functions that throw exceptions, you must use assembly
1149 pseudo ops to ensure that appropriate exception unwind information is
1150 generated. Otherwise, if one of the functions called by your assembly
1151 code throws an exception, the run-time library will be unable to
1152 unwind the stack through your assembly code and your program will not
1155 To illustrate the use of these pseudo ops, we will examine the code
1156 that G++ generates for the following C++ input:
1159 void callee (int *);
1170 This example does not show how to throw or catch an exception from
1171 assembly code. That is a much more complex operation and should
1172 always be done in a high-level language, such as C++, that directly
1173 supports exceptions.
1175 The code generated by one particular version of G++ when compiling the
1182 @ Function supports interworking.
1183 @ args = 0, pretend = 0, frame = 8
1184 @ frame_needed = 1, uses_anonymous_args = 0
1206 Of course, the sequence of instructions varies based on the options
1207 you pass to GCC and on the version of GCC in use. The exact
1208 instructions are not important since we are focusing on the pseudo ops
1209 that are used to generate unwind information.
1211 An important assumption made by the unwinder is that the stack frame
1212 does not change during the body of the function. In particular, since
1213 we assume that the assembly code does not itself throw an exception,
1214 the only point where an exception can be thrown is from a call, such
1215 as the @code{bl} instruction above. At each call site, the same saved
1216 registers (including @code{lr}, which indicates the return address)
1217 must be located in the same locations relative to the frame pointer.
1219 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1220 op appears immediately before the first instruction of the function
1221 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1222 op appears immediately after the last instruction of the function.
1223 These pseudo ops specify the range of the function.
1225 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1226 @code{.pad}) matters; their exact locations are irrelevant. In the
1227 example above, the compiler emits the pseudo ops with particular
1228 instructions. That makes it easier to understand the code, but it is
1229 not required for correctness. It would work just as well to emit all
1230 of the pseudo ops other than @code{.fnend} in the same order, but
1231 immediately after @code{.fnstart}.
1233 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1234 indicates registers that have been saved to the stack so that they can
1235 be restored before the function returns. The argument to the
1236 @code{.save} pseudo op is a list of registers to save. If a register
1237 is ``callee-saved'' (as specified by the ABI) and is modified by the
1238 function you are writing, then your code must save the value before it
1239 is modified and restore the original value before the function
1240 returns. If an exception is thrown, the run-time library restores the
1241 values of these registers from their locations on the stack before
1242 returning control to the exception handler. (Of course, if an
1243 exception is not thrown, the function that contains the @code{.save}
1244 pseudo op restores these registers in the function epilogue, as is
1245 done with the @code{ldmfd} instruction above.)
1247 You do not have to save callee-saved registers at the very beginning
1248 of the function and you do not need to use the @code{.save} pseudo op
1249 immediately following the point at which the registers are saved.
1250 However, if you modify a callee-saved register, you must save it on
1251 the stack before modifying it and before calling any functions which
1252 might throw an exception. And, you must use the @code{.save} pseudo
1253 op to indicate that you have done so.
1255 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1256 modification of the stack pointer that does not save any registers.
1257 The argument is the number of bytes (in decimal) that are subtracted
1258 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1259 subtracting from the stack pointer increases the size of the stack.)
1261 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1262 indicates the register that contains the frame pointer. The first
1263 argument is the register that is set, which is typically @code{fp}.
1264 The second argument indicates the register from which the frame
1265 pointer takes its value. The third argument, if present, is the value
1266 (in decimal) added to the register specified by the second argument to
1267 compute the value of the frame pointer. You should not modify the
1268 frame pointer in the body of the function.
1270 If you do not use a frame pointer, then you should not use the
1271 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1272 should avoid modifying the stack pointer outside of the function
1273 prologue. Otherwise, the run-time library will be unable to find
1274 saved registers when it is unwinding the stack.
1276 The pseudo ops described above are sufficient for writing assembly
1277 code that calls functions which may throw exceptions. If you need to
1278 know more about the object-file format used to represent unwind
1279 information, you may consult the @cite{Exception Handling ABI for the
1280 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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