1 @c Copyright (C) 1996-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
146 @code{cortex-m0plus},
149 @code{marvell-whitney},
153 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
154 @code{i80200} (Intel XScale processor)
155 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
158 The special name @code{all} may be used to allow the
159 assembler to accept instructions valid for any ARM processor.
161 In addition to the basic instruction set, the assembler can be told to
162 accept various extension mnemonics that extend the processor using the
163 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
164 is equivalent to specifying @code{-mcpu=ep9312}.
166 Multiple extensions may be specified, separated by a @code{+}. The
167 extensions should be specified in ascending alphabetical order.
169 Some extensions may be restricted to particular architectures; this is
170 documented in the list of extensions below.
172 Extension mnemonics may also be removed from those the assembler accepts.
173 This is done be prepending @code{no} to the option that adds the extension.
174 Extensions that are removed should be listed after all extensions which have
175 been added, again in ascending alphabetical order. For example,
176 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
179 The following extensions are currently supported:
181 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
182 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
183 @code{fp} (Floating Point Extensions for v8-A architecture),
184 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
185 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
186 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
191 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
193 @code{os} (Operating System for v6M architecture),
194 @code{predres} (Execution and Data Prediction Restriction Instruction for
195 v8-A architectures, added by default from v8.5-A),
196 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
197 default from v8.5-A),
198 @code{sec} (Security Extensions for v6K and v7-A architectures),
199 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
200 @code{virt} (Virtualization Extensions for v7-A architecture, implies
202 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
203 @code{ras} (Reliability, Availability and Serviceability extensions
204 for v8-A architecture),
205 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
210 @cindex @code{-march=} command-line option, ARM
211 @item -march=@var{architecture}[+@var{extension}@dots{}]
212 This option specifies the target architecture. The assembler will issue
213 an error message if an attempt is made to assemble an instruction which
214 will not execute on the target architecture. The following architecture
215 names are recognized:
255 If both @code{-mcpu} and
256 @code{-march} are specified, the assembler will use
257 the setting for @code{-mcpu}.
259 The architecture option can be extended with the same instruction set
260 extension options as the @code{-mcpu} option.
262 @cindex @code{-mfpu=} command-line option, ARM
263 @item -mfpu=@var{floating-point-format}
265 This option specifies the floating point format to assemble for. The
266 assembler will issue an error message if an attempt is made to assemble
267 an instruction which will not execute on the target floating point unit.
268 The following format options are recognized:
288 @code{vfpv3-d16-fp16},
305 @code{neon-fp-armv8},
306 @code{crypto-neon-fp-armv8},
307 @code{neon-fp-armv8.1}
309 @code{crypto-neon-fp-armv8.1}.
311 In addition to determining which instructions are assembled, this option
312 also affects the way in which the @code{.double} assembler directive behaves
313 when assembling little-endian code.
315 The default is dependent on the processor selected. For Architecture 5 or
316 later, the default is to assemble for VFP instructions; for earlier
317 architectures the default is to assemble for FPA instructions.
319 @cindex @code{-mthumb} command-line option, ARM
321 This option specifies that the assembler should start assembling Thumb
322 instructions; that is, it should behave as though the file starts with a
323 @code{.code 16} directive.
325 @cindex @code{-mthumb-interwork} command-line option, ARM
326 @item -mthumb-interwork
327 This option specifies that the output generated by the assembler should
328 be marked as supporting interworking. It also affects the behaviour
329 of the @code{ADR} and @code{ADRL} pseudo opcodes.
331 @cindex @code{-mimplicit-it} command-line option, ARM
332 @item -mimplicit-it=never
333 @itemx -mimplicit-it=always
334 @itemx -mimplicit-it=arm
335 @itemx -mimplicit-it=thumb
336 The @code{-mimplicit-it} option controls the behavior of the assembler when
337 conditional instructions are not enclosed in IT blocks.
338 There are four possible behaviors.
339 If @code{never} is specified, such constructs cause a warning in ARM
340 code and an error in Thumb-2 code.
341 If @code{always} is specified, such constructs are accepted in both
342 ARM and Thumb-2 code, where the IT instruction is added implicitly.
343 If @code{arm} is specified, such constructs are accepted in ARM code
344 and cause an error in Thumb-2 code.
345 If @code{thumb} is specified, such constructs cause a warning in ARM
346 code and are accepted in Thumb-2 code. If you omit this option, the
347 behavior is equivalent to @code{-mimplicit-it=arm}.
349 @cindex @code{-mapcs-26} command-line option, ARM
350 @cindex @code{-mapcs-32} command-line option, ARM
353 These options specify that the output generated by the assembler should
354 be marked as supporting the indicated version of the Arm Procedure.
357 @cindex @code{-matpcs} command-line option, ARM
359 This option specifies that the output generated by the assembler should
360 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
361 enabled this option will cause the assembler to create an empty
362 debugging section in the object file called .arm.atpcs. Debuggers can
363 use this to determine the ABI being used by.
365 @cindex @code{-mapcs-float} command-line option, ARM
367 This indicates the floating point variant of the APCS should be
368 used. In this variant floating point arguments are passed in FP
369 registers rather than integer registers.
371 @cindex @code{-mapcs-reentrant} command-line option, ARM
372 @item -mapcs-reentrant
373 This indicates that the reentrant variant of the APCS should be used.
374 This variant supports position independent code.
376 @cindex @code{-mfloat-abi=} command-line option, ARM
377 @item -mfloat-abi=@var{abi}
378 This option specifies that the output generated by the assembler should be
379 marked as using specified floating point ABI.
380 The following values are recognized:
386 @cindex @code{-eabi=} command-line option, ARM
387 @item -meabi=@var{ver}
388 This option specifies which EABI version the produced object files should
390 The following values are recognized:
396 @cindex @code{-EB} command-line option, ARM
398 This option specifies that the output generated by the assembler should
399 be marked as being encoded for a big-endian processor.
401 Note: If a program is being built for a system with big-endian data
402 and little-endian instructions then it should be assembled with the
403 @option{-EB} option, (all of it, code and data) and then linked with
404 the @option{--be8} option. This will reverse the endianness of the
405 instructions back to little-endian, but leave the data as big-endian.
407 @cindex @code{-EL} command-line option, ARM
409 This option specifies that the output generated by the assembler should
410 be marked as being encoded for a little-endian processor.
412 @cindex @code{-k} command-line option, ARM
413 @cindex PIC code generation for ARM
415 This option specifies that the output of the assembler should be marked
416 as position-independent code (PIC).
418 @cindex @code{--fix-v4bx} command-line option, ARM
420 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
421 the linker option of the same name.
423 @cindex @code{-mwarn-deprecated} command-line option, ARM
424 @item -mwarn-deprecated
425 @itemx -mno-warn-deprecated
426 Enable or disable warnings about using deprecated options or
427 features. The default is to warn.
429 @cindex @code{-mccs} command-line option, ARM
431 Turns on CodeComposer Studio assembly syntax compatibility mode.
433 @cindex @code{-mwarn-syms} command-line option, ARM
435 @itemx -mno-warn-syms
436 Enable or disable warnings about symbols that match the names of ARM
437 instructions. The default is to warn.
445 * ARM-Instruction-Set:: Instruction Set
446 * ARM-Chars:: Special Characters
447 * ARM-Regs:: Register Names
448 * ARM-Relocations:: Relocations
449 * ARM-Neon-Alignment:: NEON Alignment Specifiers
452 @node ARM-Instruction-Set
453 @subsection Instruction Set Syntax
454 Two slightly different syntaxes are support for ARM and THUMB
455 instructions. The default, @code{divided}, uses the old style where
456 ARM and THUMB instructions had their own, separate syntaxes. The new,
457 @code{unified} syntax, which can be selected via the @code{.syntax}
458 directive, and has the following main features:
462 Immediate operands do not require a @code{#} prefix.
465 The @code{IT} instruction may appear, and if it does it is validated
466 against subsequent conditional affixes. In ARM mode it does not
467 generate machine code, in THUMB mode it does.
470 For ARM instructions the conditional affixes always appear at the end
471 of the instruction. For THUMB instructions conditional affixes can be
472 used, but only inside the scope of an @code{IT} instruction.
475 All of the instructions new to the V6T2 architecture (and later) are
476 available. (Only a few such instructions can be written in the
477 @code{divided} syntax).
480 The @code{.N} and @code{.W} suffixes are recognized and honored.
483 All instructions set the flags if and only if they have an @code{s}
488 @subsection Special Characters
490 @cindex line comment character, ARM
491 @cindex ARM line comment character
492 The presence of a @samp{@@} anywhere on a line indicates the start of
493 a comment that extends to the end of that line.
495 If a @samp{#} appears as the first character of a line then the whole
496 line is treated as a comment, but in this case the line could also be
497 a logical line number directive (@pxref{Comments}) or a preprocessor
498 control command (@pxref{Preprocessing}).
500 @cindex line separator, ARM
501 @cindex statement separator, ARM
502 @cindex ARM line separator
503 The @samp{;} character can be used instead of a newline to separate
506 @cindex immediate character, ARM
507 @cindex ARM immediate character
508 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
510 @cindex identifiers, ARM
511 @cindex ARM identifiers
512 *TODO* Explain about /data modifier on symbols.
515 @subsection Register Names
517 @cindex ARM register names
518 @cindex register names, ARM
519 *TODO* Explain about ARM register naming, and the predefined names.
521 @node ARM-Relocations
522 @subsection ARM relocation generation
524 @cindex data relocations, ARM
525 @cindex ARM data relocations
526 Specific data relocations can be generated by putting the relocation name
527 in parentheses after the symbol name. For example:
533 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
535 The following relocations are supported:
551 For compatibility with older toolchains the assembler also accepts
552 @code{(PLT)} after branch targets. On legacy targets this will
553 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
554 targets it will encode either the @samp{R_ARM_CALL} or
555 @samp{R_ARM_JUMP24} relocation, as appropriate.
557 @cindex MOVW and MOVT relocations, ARM
558 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
559 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
560 respectively. For example to load the 32-bit address of foo into r0:
563 MOVW r0, #:lower16:foo
564 MOVT r0, #:upper16:foo
567 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
568 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
569 generated by prefixing the value with @samp{#:lower0_7:#},
570 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
571 respectively. For example to load the 32-bit address of foo into r0:
574 MOVS r0, #:upper8_15:#foo
576 ADDS r0, #:upper0_7:#foo
578 ADDS r0, #:lower8_15:#foo
580 ADDS r0, #:lower0_7:#foo
583 @node ARM-Neon-Alignment
584 @subsection NEON Alignment Specifiers
586 @cindex alignment for NEON instructions
587 Some NEON load/store instructions allow an optional address
589 The ARM documentation specifies that this is indicated by
590 @samp{@@ @var{align}}. However GAS already interprets
591 the @samp{@@} character as a "line comment" start,
592 so @samp{: @var{align}} is used instead. For example:
595 vld1.8 @{q0@}, [r0, :128]
598 @node ARM Floating Point
599 @section Floating Point
601 @cindex floating point, ARM (@sc{ieee})
602 @cindex ARM floating point (@sc{ieee})
603 The ARM family uses @sc{ieee} floating-point numbers.
606 @section ARM Machine Directives
608 @cindex machine directives, ARM
609 @cindex ARM machine directives
612 @c AAAAAAAAAAAAAAAAAAAAAAAAA
615 @cindex @code{.2byte} directive, ARM
616 @cindex @code{.4byte} directive, ARM
617 @cindex @code{.8byte} directive, ARM
618 @item .2byte @var{expression} [, @var{expression}]*
619 @itemx .4byte @var{expression} [, @var{expression}]*
620 @itemx .8byte @var{expression} [, @var{expression}]*
621 These directives write 2, 4 or 8 byte values to the output section.
624 @cindex @code{.align} directive, ARM
625 @item .align @var{expression} [, @var{expression}]
626 This is the generic @var{.align} directive. For the ARM however if the
627 first argument is zero (ie no alignment is needed) the assembler will
628 behave as if the argument had been 2 (ie pad to the next four byte
629 boundary). This is for compatibility with ARM's own assembler.
631 @cindex @code{.arch} directive, ARM
632 @item .arch @var{name}
633 Select the target architecture. Valid values for @var{name} are the same as
634 for the @option{-march} command-line option without the instruction set
637 Specifying @code{.arch} clears any previously selected architecture
640 @cindex @code{.arch_extension} directive, ARM
641 @item .arch_extension @var{name}
642 Add or remove an architecture extension to the target architecture. Valid
643 values for @var{name} are the same as those accepted as architectural
644 extensions by the @option{-mcpu} and @option{-march} command-line options.
646 @code{.arch_extension} may be used multiple times to add or remove extensions
647 incrementally to the architecture being compiled for.
649 @cindex @code{.arm} directive, ARM
651 This performs the same action as @var{.code 32}.
653 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
655 @cindex @code{.bss} directive, ARM
657 This directive switches to the @code{.bss} section.
659 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
661 @cindex @code{.cantunwind} directive, ARM
663 Prevents unwinding through the current function. No personality routine
664 or exception table data is required or permitted.
666 @cindex @code{.code} directive, ARM
667 @item .code @code{[16|32]}
668 This directive selects the instruction set being generated. The value 16
669 selects Thumb, with the value 32 selecting ARM.
671 @cindex @code{.cpu} directive, ARM
672 @item .cpu @var{name}
673 Select the target processor. Valid values for @var{name} are the same as
674 for the @option{-mcpu} command-line option without the instruction set
677 Specifying @code{.cpu} clears any previously selected architecture
680 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
682 @cindex @code{.dn} and @code{.qn} directives, ARM
683 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
684 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
686 The @code{dn} and @code{qn} directives are used to create typed
687 and/or indexed register aliases for use in Advanced SIMD Extension
688 (Neon) instructions. The former should be used to create aliases
689 of double-precision registers, and the latter to create aliases of
690 quad-precision registers.
692 If these directives are used to create typed aliases, those aliases can
693 be used in Neon instructions instead of writing types after the mnemonic
694 or after each operand. For example:
703 This is equivalent to writing the following:
709 Aliases created using @code{dn} or @code{qn} can be destroyed using
712 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
714 @cindex @code{.eabi_attribute} directive, ARM
715 @item .eabi_attribute @var{tag}, @var{value}
716 Set the EABI object attribute @var{tag} to @var{value}.
718 The @var{tag} is either an attribute number, or one of the following:
719 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
720 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
721 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
722 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
723 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
724 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
725 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
726 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
727 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
728 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
729 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
730 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
731 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
732 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
733 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
734 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
735 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
736 @code{Tag_conformance}, @code{Tag_T2EE_use},
737 @code{Tag_Virtualization_use}
739 The @var{value} is either a @code{number}, @code{"string"}, or
740 @code{number, "string"} depending on the tag.
742 Note - the following legacy values are also accepted by @var{tag}:
743 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
744 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
746 @cindex @code{.even} directive, ARM
748 This directive aligns to an even-numbered address.
750 @cindex @code{.extend} directive, ARM
751 @cindex @code{.ldouble} directive, ARM
752 @item .extend @var{expression} [, @var{expression}]*
753 @itemx .ldouble @var{expression} [, @var{expression}]*
754 These directives write 12byte long double floating-point values to the
755 output section. These are not compatible with current ARM processors
758 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
761 @cindex @code{.fnend} directive, ARM
763 Marks the end of a function with an unwind table entry. The unwind index
764 table entry is created when this directive is processed.
766 If no personality routine has been specified then standard personality
767 routine 0 or 1 will be used, depending on the number of unwind opcodes
771 @cindex @code{.fnstart} directive, ARM
773 Marks the start of a function with an unwind table entry.
775 @cindex @code{.force_thumb} directive, ARM
777 This directive forces the selection of Thumb instructions, even if the
778 target processor does not support those instructions
780 @cindex @code{.fpu} directive, ARM
781 @item .fpu @var{name}
782 Select the floating-point unit to assemble for. Valid values for @var{name}
783 are the same as for the @option{-mfpu} command-line option.
785 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
786 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
788 @cindex @code{.handlerdata} directive, ARM
790 Marks the end of the current function, and the start of the exception table
791 entry for that function. Anything between this directive and the
792 @code{.fnend} directive will be added to the exception table entry.
794 Must be preceded by a @code{.personality} or @code{.personalityindex}
797 @c IIIIIIIIIIIIIIIIIIIIIIIIII
799 @cindex @code{.inst} directive, ARM
800 @item .inst @var{opcode} [ , @dots{} ]
801 @itemx .inst.n @var{opcode} [ , @dots{} ]
802 @itemx .inst.w @var{opcode} [ , @dots{} ]
803 Generates the instruction corresponding to the numerical value @var{opcode}.
804 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
805 specified explicitly, overriding the normal encoding rules.
807 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
808 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
809 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
811 @item .ldouble @var{expression} [, @var{expression}]*
814 @cindex @code{.ltorg} directive, ARM
816 This directive causes the current contents of the literal pool to be
817 dumped into the current section (which is assumed to be the .text
818 section) at the current location (aligned to a word boundary).
819 @code{GAS} maintains a separate literal pool for each section and each
820 sub-section. The @code{.ltorg} directive will only affect the literal
821 pool of the current section and sub-section. At the end of assembly
822 all remaining, un-empty literal pools will automatically be dumped.
824 Note - older versions of @code{GAS} would dump the current literal
825 pool any time a section change occurred. This is no longer done, since
826 it prevents accurate control of the placement of literal pools.
828 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
830 @cindex @code{.movsp} directive, ARM
831 @item .movsp @var{reg} [, #@var{offset}]
832 Tell the unwinder that @var{reg} contains an offset from the current
833 stack pointer. If @var{offset} is not specified then it is assumed to be
836 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
837 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
839 @cindex @code{.object_arch} directive, ARM
840 @item .object_arch @var{name}
841 Override the architecture recorded in the EABI object attribute section.
842 Valid values for @var{name} are the same as for the @code{.arch} directive.
843 Typically this is useful when code uses runtime detection of CPU features.
845 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
847 @cindex @code{.packed} directive, ARM
848 @item .packed @var{expression} [, @var{expression}]*
849 This directive writes 12-byte packed floating-point values to the
850 output section. These are not compatible with current ARM processors
854 @cindex @code{.pad} directive, ARM
855 @item .pad #@var{count}
856 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
857 A positive value indicates the function prologue allocated stack space by
858 decrementing the stack pointer.
860 @cindex @code{.personality} directive, ARM
861 @item .personality @var{name}
862 Sets the personality routine for the current function to @var{name}.
864 @cindex @code{.personalityindex} directive, ARM
865 @item .personalityindex @var{index}
866 Sets the personality routine for the current function to the EABI standard
867 routine number @var{index}
869 @cindex @code{.pool} directive, ARM
871 This is a synonym for .ltorg.
873 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
874 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
876 @cindex @code{.req} directive, ARM
877 @item @var{name} .req @var{register name}
878 This creates an alias for @var{register name} called @var{name}. For
885 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
888 @cindex @code{.save} directive, ARM
889 @item .save @var{reglist}
890 Generate unwinder annotations to restore the registers in @var{reglist}.
891 The format of @var{reglist} is the same as the corresponding store-multiple
895 @exdent @emph{core registers}
896 .save @{r4, r5, r6, lr@}
897 stmfd sp!, @{r4, r5, r6, lr@}
898 @exdent @emph{FPA registers}
901 @exdent @emph{VFP registers}
902 .save @{d8, d9, d10@}
903 fstmdx sp!, @{d8, d9, d10@}
904 @exdent @emph{iWMMXt registers}
906 wstrd wr11, [sp, #-8]!
907 wstrd wr10, [sp, #-8]!
910 wstrd wr11, [sp, #-8]!
912 wstrd wr10, [sp, #-8]!
916 @cindex @code{.setfp} directive, ARM
917 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
918 Make all unwinder annotations relative to a frame pointer. Without this
919 the unwinder will use offsets from the stack pointer.
921 The syntax of this directive is the same as the @code{add} or @code{mov}
922 instruction used to set the frame pointer. @var{spreg} must be either
923 @code{sp} or mentioned in a previous @code{.movsp} directive.
933 @cindex @code{.secrel32} directive, ARM
934 @item .secrel32 @var{expression} [, @var{expression}]*
935 This directive emits relocations that evaluate to the section-relative
936 offset of each expression's symbol. This directive is only supported
939 @cindex @code{.syntax} directive, ARM
940 @item .syntax [@code{unified} | @code{divided}]
941 This directive sets the Instruction Set Syntax as described in the
942 @ref{ARM-Instruction-Set} section.
944 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
946 @cindex @code{.thumb} directive, ARM
948 This performs the same action as @var{.code 16}.
950 @cindex @code{.thumb_func} directive, ARM
952 This directive specifies that the following symbol is the name of a
953 Thumb encoded function. This information is necessary in order to allow
954 the assembler and linker to generate correct code for interworking
955 between Arm and Thumb instructions and should be used even if
956 interworking is not going to be performed. The presence of this
957 directive also implies @code{.thumb}
959 This directive is not necessary when generating EABI objects. On these
960 targets the encoding is implicit when generating Thumb code.
962 @cindex @code{.thumb_set} directive, ARM
964 This performs the equivalent of a @code{.set} directive in that it
965 creates a symbol which is an alias for another symbol (possibly not yet
966 defined). This directive also has the added property in that it marks
967 the aliased symbol as being a thumb function entry point, in the same
968 way that the @code{.thumb_func} directive does.
970 @cindex @code{.tlsdescseq} directive, ARM
971 @item .tlsdescseq @var{tls-variable}
972 This directive is used to annotate parts of an inlined TLS descriptor
973 trampoline. Normally the trampoline is provided by the linker, and
974 this directive is not needed.
976 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
978 @cindex @code{.unreq} directive, ARM
979 @item .unreq @var{alias-name}
980 This undefines a register alias which was previously defined using the
981 @code{req}, @code{dn} or @code{qn} directives. For example:
988 An error occurs if the name is undefined. Note - this pseudo op can
989 be used to delete builtin in register name aliases (eg 'r0'). This
990 should only be done if it is really necessary.
992 @cindex @code{.unwind_raw} directive, ARM
993 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
994 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
995 the stack pointer by @var{offset} bytes.
997 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1000 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1002 @cindex @code{.vsave} directive, ARM
1003 @item .vsave @var{vfp-reglist}
1004 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1005 using FLDMD. Also works for VFPv3 registers
1006 that are to be restored using VLDM.
1007 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1011 @exdent @emph{VFP registers}
1012 .vsave @{d8, d9, d10@}
1013 fstmdd sp!, @{d8, d9, d10@}
1014 @exdent @emph{VFPv3 registers}
1015 .vsave @{d15, d16, d17@}
1016 vstm sp!, @{d15, d16, d17@}
1019 Since FLDMX and FSTMX are now deprecated, this directive should be
1020 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1022 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1023 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1024 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1025 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1033 @cindex opcodes for ARM
1034 @code{@value{AS}} implements all the standard ARM opcodes. It also
1035 implements several pseudo opcodes, including several synthetic load
1040 @cindex @code{NOP} pseudo op, ARM
1046 This pseudo op will always evaluate to a legal ARM instruction that does
1047 nothing. Currently it will evaluate to MOV r0, r0.
1049 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1052 ldr <register> , = <expression>
1055 If expression evaluates to a numeric constant then a MOV or MVN
1056 instruction will be used in place of the LDR instruction, if the
1057 constant can be generated by either of these instructions. Otherwise
1058 the constant will be placed into the nearest literal pool (if it not
1059 already there) and a PC relative LDR instruction will be generated.
1061 @cindex @code{ADR reg,<label>} pseudo op, ARM
1064 adr <register> <label>
1067 This instruction will load the address of @var{label} into the indicated
1068 register. The instruction will evaluate to a PC relative ADD or SUB
1069 instruction depending upon where the label is located. If the label is
1070 out of range, or if it is not defined in the same file (and section) as
1071 the ADR instruction, then an error will be generated. This instruction
1072 will not make use of the literal pool.
1074 If @var{label} is a thumb function symbol, and thumb interworking has
1075 been enabled via the @option{-mthumb-interwork} option then the bottom
1076 bit of the value stored into @var{register} will be set. This allows
1077 the following sequence to work as expected:
1080 adr r0, thumb_function
1084 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1087 adrl <register> <label>
1090 This instruction will load the address of @var{label} into the indicated
1091 register. The instruction will evaluate to one or two PC relative ADD
1092 or SUB instructions depending upon where the label is located. If a
1093 second instruction is not needed a NOP instruction will be generated in
1094 its place, so that this instruction is always 8 bytes long.
1096 If the label is out of range, or if it is not defined in the same file
1097 (and section) as the ADRL instruction, then an error will be generated.
1098 This instruction will not make use of the literal pool.
1100 If @var{label} is a thumb function symbol, and thumb interworking has
1101 been enabled via the @option{-mthumb-interwork} option then the bottom
1102 bit of the value stored into @var{register} will be set.
1106 For information on the ARM or Thumb instruction sets, see @cite{ARM
1107 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1110 @node ARM Mapping Symbols
1111 @section Mapping Symbols
1113 The ARM ELF specification requires that special symbols be inserted
1114 into object files to mark certain features:
1120 At the start of a region of code containing ARM instructions.
1124 At the start of a region of code containing THUMB instructions.
1128 At the start of a region of data.
1132 The assembler will automatically insert these symbols for you - there
1133 is no need to code them yourself. Support for tagging symbols ($b,
1134 $f, $p and $m) which is also mentioned in the current ARM ELF
1135 specification is not implemented. This is because they have been
1136 dropped from the new EABI and so tools cannot rely upon their
1139 @node ARM Unwinding Tutorial
1142 The ABI for the ARM Architecture specifies a standard format for
1143 exception unwind information. This information is used when an
1144 exception is thrown to determine where control should be transferred.
1145 In particular, the unwind information is used to determine which
1146 function called the function that threw the exception, and which
1147 function called that one, and so forth. This information is also used
1148 to restore the values of callee-saved registers in the function
1149 catching the exception.
1151 If you are writing functions in assembly code, and those functions
1152 call other functions that throw exceptions, you must use assembly
1153 pseudo ops to ensure that appropriate exception unwind information is
1154 generated. Otherwise, if one of the functions called by your assembly
1155 code throws an exception, the run-time library will be unable to
1156 unwind the stack through your assembly code and your program will not
1159 To illustrate the use of these pseudo ops, we will examine the code
1160 that G++ generates for the following C++ input:
1163 void callee (int *);
1174 This example does not show how to throw or catch an exception from
1175 assembly code. That is a much more complex operation and should
1176 always be done in a high-level language, such as C++, that directly
1177 supports exceptions.
1179 The code generated by one particular version of G++ when compiling the
1186 @ Function supports interworking.
1187 @ args = 0, pretend = 0, frame = 8
1188 @ frame_needed = 1, uses_anonymous_args = 0
1210 Of course, the sequence of instructions varies based on the options
1211 you pass to GCC and on the version of GCC in use. The exact
1212 instructions are not important since we are focusing on the pseudo ops
1213 that are used to generate unwind information.
1215 An important assumption made by the unwinder is that the stack frame
1216 does not change during the body of the function. In particular, since
1217 we assume that the assembly code does not itself throw an exception,
1218 the only point where an exception can be thrown is from a call, such
1219 as the @code{bl} instruction above. At each call site, the same saved
1220 registers (including @code{lr}, which indicates the return address)
1221 must be located in the same locations relative to the frame pointer.
1223 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1224 op appears immediately before the first instruction of the function
1225 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1226 op appears immediately after the last instruction of the function.
1227 These pseudo ops specify the range of the function.
1229 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1230 @code{.pad}) matters; their exact locations are irrelevant. In the
1231 example above, the compiler emits the pseudo ops with particular
1232 instructions. That makes it easier to understand the code, but it is
1233 not required for correctness. It would work just as well to emit all
1234 of the pseudo ops other than @code{.fnend} in the same order, but
1235 immediately after @code{.fnstart}.
1237 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1238 indicates registers that have been saved to the stack so that they can
1239 be restored before the function returns. The argument to the
1240 @code{.save} pseudo op is a list of registers to save. If a register
1241 is ``callee-saved'' (as specified by the ABI) and is modified by the
1242 function you are writing, then your code must save the value before it
1243 is modified and restore the original value before the function
1244 returns. If an exception is thrown, the run-time library restores the
1245 values of these registers from their locations on the stack before
1246 returning control to the exception handler. (Of course, if an
1247 exception is not thrown, the function that contains the @code{.save}
1248 pseudo op restores these registers in the function epilogue, as is
1249 done with the @code{ldmfd} instruction above.)
1251 You do not have to save callee-saved registers at the very beginning
1252 of the function and you do not need to use the @code{.save} pseudo op
1253 immediately following the point at which the registers are saved.
1254 However, if you modify a callee-saved register, you must save it on
1255 the stack before modifying it and before calling any functions which
1256 might throw an exception. And, you must use the @code{.save} pseudo
1257 op to indicate that you have done so.
1259 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1260 modification of the stack pointer that does not save any registers.
1261 The argument is the number of bytes (in decimal) that are subtracted
1262 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1263 subtracting from the stack pointer increases the size of the stack.)
1265 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1266 indicates the register that contains the frame pointer. The first
1267 argument is the register that is set, which is typically @code{fp}.
1268 The second argument indicates the register from which the frame
1269 pointer takes its value. The third argument, if present, is the value
1270 (in decimal) added to the register specified by the second argument to
1271 compute the value of the frame pointer. You should not modify the
1272 frame pointer in the body of the function.
1274 If you do not use a frame pointer, then you should not use the
1275 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1276 should avoid modifying the stack pointer outside of the function
1277 prologue. Otherwise, the run-time library will be unable to find
1278 saved registers when it is unwinding the stack.
1280 The pseudo ops described above are sufficient for writing assembly
1281 code that calls functions which may throw exceptions. If you need to
1282 know more about the object-file format used to represent unwind
1283 information, you may consult the @cite{Exception Handling ABI for the
1284 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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