1 @c Copyright (C) 1996-2018 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
145 @code{cortex-m0plus},
148 @code{marvell-whitney},
151 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
152 @code{i80200} (Intel XScale processor)
153 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
156 The special name @code{all} may be used to allow the
157 assembler to accept instructions valid for any ARM processor.
159 In addition to the basic instruction set, the assembler can be told to
160 accept various extension mnemonics that extend the processor using the
161 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
162 is equivalent to specifying @code{-mcpu=ep9312}.
164 Multiple extensions may be specified, separated by a @code{+}. The
165 extensions should be specified in ascending alphabetical order.
167 Some extensions may be restricted to particular architectures; this is
168 documented in the list of extensions below.
170 Extension mnemonics may also be removed from those the assembler accepts.
171 This is done be prepending @code{no} to the option that adds the extension.
172 Extensions that are removed should be listed after all extensions which have
173 been added, again in ascending alphabetical order. For example,
174 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
177 The following extensions are currently supported:
179 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
180 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
181 @code{fp} (Floating Point Extensions for v8-A architecture),
182 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
183 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
184 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
189 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
191 @code{os} (Operating System for v6M architecture),
192 @code{sec} (Security Extensions for v6K and v7-A architectures),
193 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
194 @code{virt} (Virtualization Extensions for v7-A architecture, implies
196 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
197 @code{ras} (Reliability, Availability and Serviceability extensions
198 for v8-A architecture),
199 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
204 @cindex @code{-march=} command-line option, ARM
205 @item -march=@var{architecture}[+@var{extension}@dots{}]
206 This option specifies the target architecture. The assembler will issue
207 an error message if an attempt is made to assemble an instruction which
208 will not execute on the target architecture. The following architecture
209 names are recognized:
248 If both @code{-mcpu} and
249 @code{-march} are specified, the assembler will use
250 the setting for @code{-mcpu}.
252 The architecture option can be extended with the same instruction set
253 extension options as the @code{-mcpu} option.
255 @cindex @code{-mfpu=} command-line option, ARM
256 @item -mfpu=@var{floating-point-format}
258 This option specifies the floating point format to assemble for. The
259 assembler will issue an error message if an attempt is made to assemble
260 an instruction which will not execute on the target floating point unit.
261 The following format options are recognized:
281 @code{vfpv3-d16-fp16},
298 @code{neon-fp-armv8},
299 @code{crypto-neon-fp-armv8},
300 @code{neon-fp-armv8.1}
302 @code{crypto-neon-fp-armv8.1}.
304 In addition to determining which instructions are assembled, this option
305 also affects the way in which the @code{.double} assembler directive behaves
306 when assembling little-endian code.
308 The default is dependent on the processor selected. For Architecture 5 or
309 later, the default is to assemble for VFP instructions; for earlier
310 architectures the default is to assemble for FPA instructions.
312 @cindex @code{-mthumb} command-line option, ARM
314 This option specifies that the assembler should start assembling Thumb
315 instructions; that is, it should behave as though the file starts with a
316 @code{.code 16} directive.
318 @cindex @code{-mthumb-interwork} command-line option, ARM
319 @item -mthumb-interwork
320 This option specifies that the output generated by the assembler should
321 be marked as supporting interworking. It also affects the behaviour
322 of the @code{ADR} and @code{ADRL} pseudo opcodes.
324 @cindex @code{-mimplicit-it} command-line option, ARM
325 @item -mimplicit-it=never
326 @itemx -mimplicit-it=always
327 @itemx -mimplicit-it=arm
328 @itemx -mimplicit-it=thumb
329 The @code{-mimplicit-it} option controls the behavior of the assembler when
330 conditional instructions are not enclosed in IT blocks.
331 There are four possible behaviors.
332 If @code{never} is specified, such constructs cause a warning in ARM
333 code and an error in Thumb-2 code.
334 If @code{always} is specified, such constructs are accepted in both
335 ARM and Thumb-2 code, where the IT instruction is added implicitly.
336 If @code{arm} is specified, such constructs are accepted in ARM code
337 and cause an error in Thumb-2 code.
338 If @code{thumb} is specified, such constructs cause a warning in ARM
339 code and are accepted in Thumb-2 code. If you omit this option, the
340 behavior is equivalent to @code{-mimplicit-it=arm}.
342 @cindex @code{-mapcs-26} command-line option, ARM
343 @cindex @code{-mapcs-32} command-line option, ARM
346 These options specify that the output generated by the assembler should
347 be marked as supporting the indicated version of the Arm Procedure.
350 @cindex @code{-matpcs} command-line option, ARM
352 This option specifies that the output generated by the assembler should
353 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
354 enabled this option will cause the assembler to create an empty
355 debugging section in the object file called .arm.atpcs. Debuggers can
356 use this to determine the ABI being used by.
358 @cindex @code{-mapcs-float} command-line option, ARM
360 This indicates the floating point variant of the APCS should be
361 used. In this variant floating point arguments are passed in FP
362 registers rather than integer registers.
364 @cindex @code{-mapcs-reentrant} command-line option, ARM
365 @item -mapcs-reentrant
366 This indicates that the reentrant variant of the APCS should be used.
367 This variant supports position independent code.
369 @cindex @code{-mfloat-abi=} command-line option, ARM
370 @item -mfloat-abi=@var{abi}
371 This option specifies that the output generated by the assembler should be
372 marked as using specified floating point ABI.
373 The following values are recognized:
379 @cindex @code{-eabi=} command-line option, ARM
380 @item -meabi=@var{ver}
381 This option specifies which EABI version the produced object files should
383 The following values are recognized:
389 @cindex @code{-EB} command-line option, ARM
391 This option specifies that the output generated by the assembler should
392 be marked as being encoded for a big-endian processor.
394 Note: If a program is being built for a system with big-endian data
395 and little-endian instructions then it should be assembled with the
396 @option{-EB} option, (all of it, code and data) and then linked with
397 the @option{--be8} option. This will reverse the endianness of the
398 instructions back to little-endian, but leave the data as big-endian.
400 @cindex @code{-EL} command-line option, ARM
402 This option specifies that the output generated by the assembler should
403 be marked as being encoded for a little-endian processor.
405 @cindex @code{-k} command-line option, ARM
406 @cindex PIC code generation for ARM
408 This option specifies that the output of the assembler should be marked
409 as position-independent code (PIC).
411 @cindex @code{--fix-v4bx} command-line option, ARM
413 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
414 the linker option of the same name.
416 @cindex @code{-mwarn-deprecated} command-line option, ARM
417 @item -mwarn-deprecated
418 @itemx -mno-warn-deprecated
419 Enable or disable warnings about using deprecated options or
420 features. The default is to warn.
422 @cindex @code{-mccs} command-line option, ARM
424 Turns on CodeComposer Studio assembly syntax compatibility mode.
426 @cindex @code{-mwarn-syms} command-line option, ARM
428 @itemx -mno-warn-syms
429 Enable or disable warnings about symbols that match the names of ARM
430 instructions. The default is to warn.
438 * ARM-Instruction-Set:: Instruction Set
439 * ARM-Chars:: Special Characters
440 * ARM-Regs:: Register Names
441 * ARM-Relocations:: Relocations
442 * ARM-Neon-Alignment:: NEON Alignment Specifiers
445 @node ARM-Instruction-Set
446 @subsection Instruction Set Syntax
447 Two slightly different syntaxes are support for ARM and THUMB
448 instructions. The default, @code{divided}, uses the old style where
449 ARM and THUMB instructions had their own, separate syntaxes. The new,
450 @code{unified} syntax, which can be selected via the @code{.syntax}
451 directive, and has the following main features:
455 Immediate operands do not require a @code{#} prefix.
458 The @code{IT} instruction may appear, and if it does it is validated
459 against subsequent conditional affixes. In ARM mode it does not
460 generate machine code, in THUMB mode it does.
463 For ARM instructions the conditional affixes always appear at the end
464 of the instruction. For THUMB instructions conditional affixes can be
465 used, but only inside the scope of an @code{IT} instruction.
468 All of the instructions new to the V6T2 architecture (and later) are
469 available. (Only a few such instructions can be written in the
470 @code{divided} syntax).
473 The @code{.N} and @code{.W} suffixes are recognized and honored.
476 All instructions set the flags if and only if they have an @code{s}
481 @subsection Special Characters
483 @cindex line comment character, ARM
484 @cindex ARM line comment character
485 The presence of a @samp{@@} anywhere on a line indicates the start of
486 a comment that extends to the end of that line.
488 If a @samp{#} appears as the first character of a line then the whole
489 line is treated as a comment, but in this case the line could also be
490 a logical line number directive (@pxref{Comments}) or a preprocessor
491 control command (@pxref{Preprocessing}).
493 @cindex line separator, ARM
494 @cindex statement separator, ARM
495 @cindex ARM line separator
496 The @samp{;} character can be used instead of a newline to separate
499 @cindex immediate character, ARM
500 @cindex ARM immediate character
501 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
503 @cindex identifiers, ARM
504 @cindex ARM identifiers
505 *TODO* Explain about /data modifier on symbols.
508 @subsection Register Names
510 @cindex ARM register names
511 @cindex register names, ARM
512 *TODO* Explain about ARM register naming, and the predefined names.
514 @node ARM-Relocations
515 @subsection ARM relocation generation
517 @cindex data relocations, ARM
518 @cindex ARM data relocations
519 Specific data relocations can be generated by putting the relocation name
520 in parentheses after the symbol name. For example:
526 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
528 The following relocations are supported:
544 For compatibility with older toolchains the assembler also accepts
545 @code{(PLT)} after branch targets. On legacy targets this will
546 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
547 targets it will encode either the @samp{R_ARM_CALL} or
548 @samp{R_ARM_JUMP24} relocation, as appropriate.
550 @cindex MOVW and MOVT relocations, ARM
551 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
552 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
553 respectively. For example to load the 32-bit address of foo into r0:
556 MOVW r0, #:lower16:foo
557 MOVT r0, #:upper16:foo
560 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
561 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
562 generated by prefixing the value with @samp{#:lower0_7:#},
563 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
564 respectively. For example to load the 32-bit address of foo into r0:
567 MOVS r0, #:upper8_15:#foo
569 ADDS r0, #:upper0_7:#foo
571 ADDS r0, #:lower8_15:#foo
573 ADDS r0, #:lower0_7:#foo
576 @node ARM-Neon-Alignment
577 @subsection NEON Alignment Specifiers
579 @cindex alignment for NEON instructions
580 Some NEON load/store instructions allow an optional address
582 The ARM documentation specifies that this is indicated by
583 @samp{@@ @var{align}}. However GAS already interprets
584 the @samp{@@} character as a "line comment" start,
585 so @samp{: @var{align}} is used instead. For example:
588 vld1.8 @{q0@}, [r0, :128]
591 @node ARM Floating Point
592 @section Floating Point
594 @cindex floating point, ARM (@sc{ieee})
595 @cindex ARM floating point (@sc{ieee})
596 The ARM family uses @sc{ieee} floating-point numbers.
599 @section ARM Machine Directives
601 @cindex machine directives, ARM
602 @cindex ARM machine directives
605 @c AAAAAAAAAAAAAAAAAAAAAAAAA
608 @cindex @code{.2byte} directive, ARM
609 @cindex @code{.4byte} directive, ARM
610 @cindex @code{.8byte} directive, ARM
611 @item .2byte @var{expression} [, @var{expression}]*
612 @itemx .4byte @var{expression} [, @var{expression}]*
613 @itemx .8byte @var{expression} [, @var{expression}]*
614 These directives write 2, 4 or 8 byte values to the output section.
617 @cindex @code{.align} directive, ARM
618 @item .align @var{expression} [, @var{expression}]
619 This is the generic @var{.align} directive. For the ARM however if the
620 first argument is zero (ie no alignment is needed) the assembler will
621 behave as if the argument had been 2 (ie pad to the next four byte
622 boundary). This is for compatibility with ARM's own assembler.
624 @cindex @code{.arch} directive, ARM
625 @item .arch @var{name}
626 Select the target architecture. Valid values for @var{name} are the same as
627 for the @option{-march} command-line option.
629 Specifying @code{.arch} clears any previously selected architecture
632 @cindex @code{.arch_extension} directive, ARM
633 @item .arch_extension @var{name}
634 Add or remove an architecture extension to the target architecture. Valid
635 values for @var{name} are the same as those accepted as architectural
636 extensions by the @option{-mcpu} and @option{-march} command-line options.
638 @code{.arch_extension} may be used multiple times to add or remove extensions
639 incrementally to the architecture being compiled for.
641 @cindex @code{.arm} directive, ARM
643 This performs the same action as @var{.code 32}.
645 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
647 @cindex @code{.bss} directive, ARM
649 This directive switches to the @code{.bss} section.
651 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
653 @cindex @code{.cantunwind} directive, ARM
655 Prevents unwinding through the current function. No personality routine
656 or exception table data is required or permitted.
658 @cindex @code{.code} directive, ARM
659 @item .code @code{[16|32]}
660 This directive selects the instruction set being generated. The value 16
661 selects Thumb, with the value 32 selecting ARM.
663 @cindex @code{.cpu} directive, ARM
664 @item .cpu @var{name}
665 Select the target processor. Valid values for @var{name} are the same as
666 for the @option{-mcpu} command-line option.
668 Specifying @code{.cpu} clears any previously selected architecture
671 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
673 @cindex @code{.dn} and @code{.qn} directives, ARM
674 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
675 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
677 The @code{dn} and @code{qn} directives are used to create typed
678 and/or indexed register aliases for use in Advanced SIMD Extension
679 (Neon) instructions. The former should be used to create aliases
680 of double-precision registers, and the latter to create aliases of
681 quad-precision registers.
683 If these directives are used to create typed aliases, those aliases can
684 be used in Neon instructions instead of writing types after the mnemonic
685 or after each operand. For example:
694 This is equivalent to writing the following:
700 Aliases created using @code{dn} or @code{qn} can be destroyed using
703 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
705 @cindex @code{.eabi_attribute} directive, ARM
706 @item .eabi_attribute @var{tag}, @var{value}
707 Set the EABI object attribute @var{tag} to @var{value}.
709 The @var{tag} is either an attribute number, or one of the following:
710 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
711 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
712 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
713 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
714 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
715 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
716 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
717 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
718 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
719 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
720 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
721 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
722 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
723 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
724 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
725 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
726 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
727 @code{Tag_conformance}, @code{Tag_T2EE_use},
728 @code{Tag_Virtualization_use}
730 The @var{value} is either a @code{number}, @code{"string"}, or
731 @code{number, "string"} depending on the tag.
733 Note - the following legacy values are also accepted by @var{tag}:
734 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
735 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
737 @cindex @code{.even} directive, ARM
739 This directive aligns to an even-numbered address.
741 @cindex @code{.extend} directive, ARM
742 @cindex @code{.ldouble} directive, ARM
743 @item .extend @var{expression} [, @var{expression}]*
744 @itemx .ldouble @var{expression} [, @var{expression}]*
745 These directives write 12byte long double floating-point values to the
746 output section. These are not compatible with current ARM processors
749 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
752 @cindex @code{.fnend} directive, ARM
754 Marks the end of a function with an unwind table entry. The unwind index
755 table entry is created when this directive is processed.
757 If no personality routine has been specified then standard personality
758 routine 0 or 1 will be used, depending on the number of unwind opcodes
762 @cindex @code{.fnstart} directive, ARM
764 Marks the start of a function with an unwind table entry.
766 @cindex @code{.force_thumb} directive, ARM
768 This directive forces the selection of Thumb instructions, even if the
769 target processor does not support those instructions
771 @cindex @code{.fpu} directive, ARM
772 @item .fpu @var{name}
773 Select the floating-point unit to assemble for. Valid values for @var{name}
774 are the same as for the @option{-mfpu} command-line option.
776 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
777 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
779 @cindex @code{.handlerdata} directive, ARM
781 Marks the end of the current function, and the start of the exception table
782 entry for that function. Anything between this directive and the
783 @code{.fnend} directive will be added to the exception table entry.
785 Must be preceded by a @code{.personality} or @code{.personalityindex}
788 @c IIIIIIIIIIIIIIIIIIIIIIIIII
790 @cindex @code{.inst} directive, ARM
791 @item .inst @var{opcode} [ , @dots{} ]
792 @itemx .inst.n @var{opcode} [ , @dots{} ]
793 @itemx .inst.w @var{opcode} [ , @dots{} ]
794 Generates the instruction corresponding to the numerical value @var{opcode}.
795 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
796 specified explicitly, overriding the normal encoding rules.
798 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
799 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
800 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
802 @item .ldouble @var{expression} [, @var{expression}]*
805 @cindex @code{.ltorg} directive, ARM
807 This directive causes the current contents of the literal pool to be
808 dumped into the current section (which is assumed to be the .text
809 section) at the current location (aligned to a word boundary).
810 @code{GAS} maintains a separate literal pool for each section and each
811 sub-section. The @code{.ltorg} directive will only affect the literal
812 pool of the current section and sub-section. At the end of assembly
813 all remaining, un-empty literal pools will automatically be dumped.
815 Note - older versions of @code{GAS} would dump the current literal
816 pool any time a section change occurred. This is no longer done, since
817 it prevents accurate control of the placement of literal pools.
819 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
821 @cindex @code{.movsp} directive, ARM
822 @item .movsp @var{reg} [, #@var{offset}]
823 Tell the unwinder that @var{reg} contains an offset from the current
824 stack pointer. If @var{offset} is not specified then it is assumed to be
827 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
828 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
830 @cindex @code{.object_arch} directive, ARM
831 @item .object_arch @var{name}
832 Override the architecture recorded in the EABI object attribute section.
833 Valid values for @var{name} are the same as for the @code{.arch} directive.
834 Typically this is useful when code uses runtime detection of CPU features.
836 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
838 @cindex @code{.packed} directive, ARM
839 @item .packed @var{expression} [, @var{expression}]*
840 This directive writes 12-byte packed floating-point values to the
841 output section. These are not compatible with current ARM processors
845 @cindex @code{.pad} directive, ARM
846 @item .pad #@var{count}
847 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
848 A positive value indicates the function prologue allocated stack space by
849 decrementing the stack pointer.
851 @cindex @code{.personality} directive, ARM
852 @item .personality @var{name}
853 Sets the personality routine for the current function to @var{name}.
855 @cindex @code{.personalityindex} directive, ARM
856 @item .personalityindex @var{index}
857 Sets the personality routine for the current function to the EABI standard
858 routine number @var{index}
860 @cindex @code{.pool} directive, ARM
862 This is a synonym for .ltorg.
864 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
865 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
867 @cindex @code{.req} directive, ARM
868 @item @var{name} .req @var{register name}
869 This creates an alias for @var{register name} called @var{name}. For
876 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
879 @cindex @code{.save} directive, ARM
880 @item .save @var{reglist}
881 Generate unwinder annotations to restore the registers in @var{reglist}.
882 The format of @var{reglist} is the same as the corresponding store-multiple
886 @exdent @emph{core registers}
887 .save @{r4, r5, r6, lr@}
888 stmfd sp!, @{r4, r5, r6, lr@}
889 @exdent @emph{FPA registers}
892 @exdent @emph{VFP registers}
893 .save @{d8, d9, d10@}
894 fstmdx sp!, @{d8, d9, d10@}
895 @exdent @emph{iWMMXt registers}
897 wstrd wr11, [sp, #-8]!
898 wstrd wr10, [sp, #-8]!
901 wstrd wr11, [sp, #-8]!
903 wstrd wr10, [sp, #-8]!
907 @cindex @code{.setfp} directive, ARM
908 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
909 Make all unwinder annotations relative to a frame pointer. Without this
910 the unwinder will use offsets from the stack pointer.
912 The syntax of this directive is the same as the @code{add} or @code{mov}
913 instruction used to set the frame pointer. @var{spreg} must be either
914 @code{sp} or mentioned in a previous @code{.movsp} directive.
924 @cindex @code{.secrel32} directive, ARM
925 @item .secrel32 @var{expression} [, @var{expression}]*
926 This directive emits relocations that evaluate to the section-relative
927 offset of each expression's symbol. This directive is only supported
930 @cindex @code{.syntax} directive, ARM
931 @item .syntax [@code{unified} | @code{divided}]
932 This directive sets the Instruction Set Syntax as described in the
933 @ref{ARM-Instruction-Set} section.
935 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
937 @cindex @code{.thumb} directive, ARM
939 This performs the same action as @var{.code 16}.
941 @cindex @code{.thumb_func} directive, ARM
943 This directive specifies that the following symbol is the name of a
944 Thumb encoded function. This information is necessary in order to allow
945 the assembler and linker to generate correct code for interworking
946 between Arm and Thumb instructions and should be used even if
947 interworking is not going to be performed. The presence of this
948 directive also implies @code{.thumb}
950 This directive is not necessary when generating EABI objects. On these
951 targets the encoding is implicit when generating Thumb code.
953 @cindex @code{.thumb_set} directive, ARM
955 This performs the equivalent of a @code{.set} directive in that it
956 creates a symbol which is an alias for another symbol (possibly not yet
957 defined). This directive also has the added property in that it marks
958 the aliased symbol as being a thumb function entry point, in the same
959 way that the @code{.thumb_func} directive does.
961 @cindex @code{.tlsdescseq} directive, ARM
962 @item .tlsdescseq @var{tls-variable}
963 This directive is used to annotate parts of an inlined TLS descriptor
964 trampoline. Normally the trampoline is provided by the linker, and
965 this directive is not needed.
967 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
969 @cindex @code{.unreq} directive, ARM
970 @item .unreq @var{alias-name}
971 This undefines a register alias which was previously defined using the
972 @code{req}, @code{dn} or @code{qn} directives. For example:
979 An error occurs if the name is undefined. Note - this pseudo op can
980 be used to delete builtin in register name aliases (eg 'r0'). This
981 should only be done if it is really necessary.
983 @cindex @code{.unwind_raw} directive, ARM
984 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
985 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
986 the stack pointer by @var{offset} bytes.
988 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
991 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
993 @cindex @code{.vsave} directive, ARM
994 @item .vsave @var{vfp-reglist}
995 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
996 using FLDMD. Also works for VFPv3 registers
997 that are to be restored using VLDM.
998 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1002 @exdent @emph{VFP registers}
1003 .vsave @{d8, d9, d10@}
1004 fstmdd sp!, @{d8, d9, d10@}
1005 @exdent @emph{VFPv3 registers}
1006 .vsave @{d15, d16, d17@}
1007 vstm sp!, @{d15, d16, d17@}
1010 Since FLDMX and FSTMX are now deprecated, this directive should be
1011 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1013 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1014 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1015 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1016 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1024 @cindex opcodes for ARM
1025 @code{@value{AS}} implements all the standard ARM opcodes. It also
1026 implements several pseudo opcodes, including several synthetic load
1031 @cindex @code{NOP} pseudo op, ARM
1037 This pseudo op will always evaluate to a legal ARM instruction that does
1038 nothing. Currently it will evaluate to MOV r0, r0.
1040 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1043 ldr <register> , = <expression>
1046 If expression evaluates to a numeric constant then a MOV or MVN
1047 instruction will be used in place of the LDR instruction, if the
1048 constant can be generated by either of these instructions. Otherwise
1049 the constant will be placed into the nearest literal pool (if it not
1050 already there) and a PC relative LDR instruction will be generated.
1052 @cindex @code{ADR reg,<label>} pseudo op, ARM
1055 adr <register> <label>
1058 This instruction will load the address of @var{label} into the indicated
1059 register. The instruction will evaluate to a PC relative ADD or SUB
1060 instruction depending upon where the label is located. If the label is
1061 out of range, or if it is not defined in the same file (and section) as
1062 the ADR instruction, then an error will be generated. This instruction
1063 will not make use of the literal pool.
1065 If @var{label} is a thumb function symbol, and thumb interworking has
1066 been enabled via the @option{-mthumb-interwork} option then the bottom
1067 bit of the value stored into @var{register} will be set. This allows
1068 the following sequence to work as expected:
1071 adr r0, thumb_function
1075 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1078 adrl <register> <label>
1081 This instruction will load the address of @var{label} into the indicated
1082 register. The instruction will evaluate to one or two PC relative ADD
1083 or SUB instructions depending upon where the label is located. If a
1084 second instruction is not needed a NOP instruction will be generated in
1085 its place, so that this instruction is always 8 bytes long.
1087 If the label is out of range, or if it is not defined in the same file
1088 (and section) as the ADRL instruction, then an error will be generated.
1089 This instruction will not make use of the literal pool.
1091 If @var{label} is a thumb function symbol, and thumb interworking has
1092 been enabled via the @option{-mthumb-interwork} option then the bottom
1093 bit of the value stored into @var{register} will be set.
1097 For information on the ARM or Thumb instruction sets, see @cite{ARM
1098 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1101 @node ARM Mapping Symbols
1102 @section Mapping Symbols
1104 The ARM ELF specification requires that special symbols be inserted
1105 into object files to mark certain features:
1111 At the start of a region of code containing ARM instructions.
1115 At the start of a region of code containing THUMB instructions.
1119 At the start of a region of data.
1123 The assembler will automatically insert these symbols for you - there
1124 is no need to code them yourself. Support for tagging symbols ($b,
1125 $f, $p and $m) which is also mentioned in the current ARM ELF
1126 specification is not implemented. This is because they have been
1127 dropped from the new EABI and so tools cannot rely upon their
1130 @node ARM Unwinding Tutorial
1133 The ABI for the ARM Architecture specifies a standard format for
1134 exception unwind information. This information is used when an
1135 exception is thrown to determine where control should be transferred.
1136 In particular, the unwind information is used to determine which
1137 function called the function that threw the exception, and which
1138 function called that one, and so forth. This information is also used
1139 to restore the values of callee-saved registers in the function
1140 catching the exception.
1142 If you are writing functions in assembly code, and those functions
1143 call other functions that throw exceptions, you must use assembly
1144 pseudo ops to ensure that appropriate exception unwind information is
1145 generated. Otherwise, if one of the functions called by your assembly
1146 code throws an exception, the run-time library will be unable to
1147 unwind the stack through your assembly code and your program will not
1150 To illustrate the use of these pseudo ops, we will examine the code
1151 that G++ generates for the following C++ input:
1154 void callee (int *);
1165 This example does not show how to throw or catch an exception from
1166 assembly code. That is a much more complex operation and should
1167 always be done in a high-level language, such as C++, that directly
1168 supports exceptions.
1170 The code generated by one particular version of G++ when compiling the
1177 @ Function supports interworking.
1178 @ args = 0, pretend = 0, frame = 8
1179 @ frame_needed = 1, uses_anonymous_args = 0
1201 Of course, the sequence of instructions varies based on the options
1202 you pass to GCC and on the version of GCC in use. The exact
1203 instructions are not important since we are focusing on the pseudo ops
1204 that are used to generate unwind information.
1206 An important assumption made by the unwinder is that the stack frame
1207 does not change during the body of the function. In particular, since
1208 we assume that the assembly code does not itself throw an exception,
1209 the only point where an exception can be thrown is from a call, such
1210 as the @code{bl} instruction above. At each call site, the same saved
1211 registers (including @code{lr}, which indicates the return address)
1212 must be located in the same locations relative to the frame pointer.
1214 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1215 op appears immediately before the first instruction of the function
1216 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1217 op appears immediately after the last instruction of the function.
1218 These pseudo ops specify the range of the function.
1220 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1221 @code{.pad}) matters; their exact locations are irrelevant. In the
1222 example above, the compiler emits the pseudo ops with particular
1223 instructions. That makes it easier to understand the code, but it is
1224 not required for correctness. It would work just as well to emit all
1225 of the pseudo ops other than @code{.fnend} in the same order, but
1226 immediately after @code{.fnstart}.
1228 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1229 indicates registers that have been saved to the stack so that they can
1230 be restored before the function returns. The argument to the
1231 @code{.save} pseudo op is a list of registers to save. If a register
1232 is ``callee-saved'' (as specified by the ABI) and is modified by the
1233 function you are writing, then your code must save the value before it
1234 is modified and restore the original value before the function
1235 returns. If an exception is thrown, the run-time library restores the
1236 values of these registers from their locations on the stack before
1237 returning control to the exception handler. (Of course, if an
1238 exception is not thrown, the function that contains the @code{.save}
1239 pseudo op restores these registers in the function epilogue, as is
1240 done with the @code{ldmfd} instruction above.)
1242 You do not have to save callee-saved registers at the very beginning
1243 of the function and you do not need to use the @code{.save} pseudo op
1244 immediately following the point at which the registers are saved.
1245 However, if you modify a callee-saved register, you must save it on
1246 the stack before modifying it and before calling any functions which
1247 might throw an exception. And, you must use the @code{.save} pseudo
1248 op to indicate that you have done so.
1250 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1251 modification of the stack pointer that does not save any registers.
1252 The argument is the number of bytes (in decimal) that are subtracted
1253 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1254 subtracting from the stack pointer increases the size of the stack.)
1256 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1257 indicates the register that contains the frame pointer. The first
1258 argument is the register that is set, which is typically @code{fp}.
1259 The second argument indicates the register from which the frame
1260 pointer takes its value. The third argument, if present, is the value
1261 (in decimal) added to the register specified by the second argument to
1262 compute the value of the frame pointer. You should not modify the
1263 frame pointer in the body of the function.
1265 If you do not use a frame pointer, then you should not use the
1266 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1267 should avoid modifying the stack pointer outside of the function
1268 prologue. Otherwise, the run-time library will be unable to find
1269 saved registers when it is unwinding the stack.
1271 The pseudo ops described above are sufficient for writing assembly
1272 code that calls functions which may throw exceptions. If you need to
1273 know more about the object-file format used to represent unwind
1274 information, you may consult the @cite{Exception Handling ABI for the
1275 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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