1 @c Copyright (C) 1996-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
134 @code{cortex-m0plus},
137 @code{marvell-whitney},
140 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
141 @code{i80200} (Intel XScale processor)
142 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
145 The special name @code{all} may be used to allow the
146 assembler to accept instructions valid for any ARM processor.
148 In addition to the basic instruction set, the assembler can be told to
149 accept various extension mnemonics that extend the processor using the
150 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
151 is equivalent to specifying @code{-mcpu=ep9312}.
153 Multiple extensions may be specified, separated by a @code{+}. The
154 extensions should be specified in ascending alphabetical order.
156 Some extensions may be restricted to particular architectures; this is
157 documented in the list of extensions below.
159 Extension mnemonics may also be removed from those the assembler accepts.
160 This is done be prepending @code{no} to the option that adds the extension.
161 Extensions that are removed should be listed after all extensions which have
162 been added, again in ascending alphabetical order. For example,
163 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
166 The following extensions are currently supported:
168 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
169 @code{fp} (Floating Point Extensions for v8-A architecture),
170 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
175 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
177 @code{os} (Operating System for v6M architecture),
178 @code{sec} (Security Extensions for v6K and v7-A architectures),
179 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
180 @code{virt} (Virtualization Extensions for v7-A architecture, implies
182 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
183 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
188 @cindex @code{-march=} command line option, ARM
189 @item -march=@var{architecture}[+@var{extension}@dots{}]
190 This option specifies the target architecture. The assembler will issue
191 an error message if an attempt is made to assemble an instruction which
192 will not execute on the target architecture. The following architecture
193 names are recognized:
228 If both @code{-mcpu} and
229 @code{-march} are specified, the assembler will use
230 the setting for @code{-mcpu}.
232 The architecture option can be extended with the same instruction set
233 extension options as the @code{-mcpu} option.
235 @cindex @code{-mfpu=} command line option, ARM
236 @item -mfpu=@var{floating-point-format}
238 This option specifies the floating point format to assemble for. The
239 assembler will issue an error message if an attempt is made to assemble
240 an instruction which will not execute on the target floating point unit.
241 The following format options are recognized:
261 @code{vfpv3-d16-fp16},
276 @code{neon-fp-armv8},
277 @code{crypto-neon-fp-armv8}.
279 @code{neon-fp-armv8-1},
281 In addition to determining which instructions are assembled, this option
282 also affects the way in which the @code{.double} assembler directive behaves
283 when assembling little-endian code.
285 The default is dependent on the processor selected. For Architecture 5 or
286 later, the default is to assembler for VFP instructions; for earlier
287 architectures the default is to assemble for FPA instructions.
289 @cindex @code{-mthumb} command line option, ARM
291 This option specifies that the assembler should start assembling Thumb
292 instructions; that is, it should behave as though the file starts with a
293 @code{.code 16} directive.
295 @cindex @code{-mthumb-interwork} command line option, ARM
296 @item -mthumb-interwork
297 This option specifies that the output generated by the assembler should
298 be marked as supporting interworking.
300 @cindex @code{-mimplicit-it} command line option, ARM
301 @item -mimplicit-it=never
302 @itemx -mimplicit-it=always
303 @itemx -mimplicit-it=arm
304 @itemx -mimplicit-it=thumb
305 The @code{-mimplicit-it} option controls the behavior of the assembler when
306 conditional instructions are not enclosed in IT blocks.
307 There are four possible behaviors.
308 If @code{never} is specified, such constructs cause a warning in ARM
309 code and an error in Thumb-2 code.
310 If @code{always} is specified, such constructs are accepted in both
311 ARM and Thumb-2 code, where the IT instruction is added implicitly.
312 If @code{arm} is specified, such constructs are accepted in ARM code
313 and cause an error in Thumb-2 code.
314 If @code{thumb} is specified, such constructs cause a warning in ARM
315 code and are accepted in Thumb-2 code. If you omit this option, the
316 behavior is equivalent to @code{-mimplicit-it=arm}.
318 @cindex @code{-mapcs-26} command line option, ARM
319 @cindex @code{-mapcs-32} command line option, ARM
322 These options specify that the output generated by the assembler should
323 be marked as supporting the indicated version of the Arm Procedure.
326 @cindex @code{-matpcs} command line option, ARM
328 This option specifies that the output generated by the assembler should
329 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
330 enabled this option will cause the assembler to create an empty
331 debugging section in the object file called .arm.atpcs. Debuggers can
332 use this to determine the ABI being used by.
334 @cindex @code{-mapcs-float} command line option, ARM
336 This indicates the floating point variant of the APCS should be
337 used. In this variant floating point arguments are passed in FP
338 registers rather than integer registers.
340 @cindex @code{-mapcs-reentrant} command line option, ARM
341 @item -mapcs-reentrant
342 This indicates that the reentrant variant of the APCS should be used.
343 This variant supports position independent code.
345 @cindex @code{-mfloat-abi=} command line option, ARM
346 @item -mfloat-abi=@var{abi}
347 This option specifies that the output generated by the assembler should be
348 marked as using specified floating point ABI.
349 The following values are recognized:
355 @cindex @code{-eabi=} command line option, ARM
356 @item -meabi=@var{ver}
357 This option specifies which EABI version the produced object files should
359 The following values are recognized:
365 @cindex @code{-EB} command line option, ARM
367 This option specifies that the output generated by the assembler should
368 be marked as being encoded for a big-endian processor.
370 Note: If a program is being built for a system with big-endian data
371 and little-endian instructions then it should be assembled with the
372 @option{-EB} option, (all of it, code and data) and then linked with
373 the @option{--be8} option. This will reverse the endianness of the
374 instructions back to little-endian, but leave the data as big-endian.
376 @cindex @code{-EL} command line option, ARM
378 This option specifies that the output generated by the assembler should
379 be marked as being encoded for a little-endian processor.
381 @cindex @code{-k} command line option, ARM
382 @cindex PIC code generation for ARM
384 This option specifies that the output of the assembler should be marked
385 as position-independent code (PIC).
387 @cindex @code{--fix-v4bx} command line option, ARM
389 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
390 the linker option of the same name.
392 @cindex @code{-mwarn-deprecated} command line option, ARM
393 @item -mwarn-deprecated
394 @itemx -mno-warn-deprecated
395 Enable or disable warnings about using deprecated options or
396 features. The default is to warn.
398 @cindex @code{-mccs} command line option, ARM
400 Turns on CodeComposer Studio assembly syntax compatibility mode.
402 @cindex @code{-mwarn-syms} command line option, ARM
404 @itemx -mno-warn-syms
405 Enable or disable warnings about symbols that match the names of ARM
406 instructions. The default is to warn.
414 * ARM-Instruction-Set:: Instruction Set
415 * ARM-Chars:: Special Characters
416 * ARM-Regs:: Register Names
417 * ARM-Relocations:: Relocations
418 * ARM-Neon-Alignment:: NEON Alignment Specifiers
421 @node ARM-Instruction-Set
422 @subsection Instruction Set Syntax
423 Two slightly different syntaxes are support for ARM and THUMB
424 instructions. The default, @code{divided}, uses the old style where
425 ARM and THUMB instructions had their own, separate syntaxes. The new,
426 @code{unified} syntax, which can be selected via the @code{.syntax}
427 directive, and has the following main features:
431 Immediate operands do not require a @code{#} prefix.
434 The @code{IT} instruction may appear, and if it does it is validated
435 against subsequent conditional affixes. In ARM mode it does not
436 generate machine code, in THUMB mode it does.
439 For ARM instructions the conditional affixes always appear at the end
440 of the instruction. For THUMB instructions conditional affixes can be
441 used, but only inside the scope of an @code{IT} instruction.
444 All of the instructions new to the V6T2 architecture (and later) are
445 available. (Only a few such instructions can be written in the
446 @code{divided} syntax).
449 The @code{.N} and @code{.W} suffixes are recognized and honored.
452 All instructions set the flags if and only if they have an @code{s}
457 @subsection Special Characters
459 @cindex line comment character, ARM
460 @cindex ARM line comment character
461 The presence of a @samp{@@} anywhere on a line indicates the start of
462 a comment that extends to the end of that line.
464 If a @samp{#} appears as the first character of a line then the whole
465 line is treated as a comment, but in this case the line could also be
466 a logical line number directive (@pxref{Comments}) or a preprocessor
467 control command (@pxref{Preprocessing}).
469 @cindex line separator, ARM
470 @cindex statement separator, ARM
471 @cindex ARM line separator
472 The @samp{;} character can be used instead of a newline to separate
475 @cindex immediate character, ARM
476 @cindex ARM immediate character
477 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
479 @cindex identifiers, ARM
480 @cindex ARM identifiers
481 *TODO* Explain about /data modifier on symbols.
484 @subsection Register Names
486 @cindex ARM register names
487 @cindex register names, ARM
488 *TODO* Explain about ARM register naming, and the predefined names.
490 @node ARM-Relocations
491 @subsection ARM relocation generation
493 @cindex data relocations, ARM
494 @cindex ARM data relocations
495 Specific data relocations can be generated by putting the relocation name
496 in parentheses after the symbol name. For example:
502 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
504 The following relocations are supported:
520 For compatibility with older toolchains the assembler also accepts
521 @code{(PLT)} after branch targets. On legacy targets this will
522 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
523 targets it will encode either the @samp{R_ARM_CALL} or
524 @samp{R_ARM_JUMP24} relocation, as appropriate.
526 @cindex MOVW and MOVT relocations, ARM
527 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
528 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
529 respectively. For example to load the 32-bit address of foo into r0:
532 MOVW r0, #:lower16:foo
533 MOVT r0, #:upper16:foo
536 @node ARM-Neon-Alignment
537 @subsection NEON Alignment Specifiers
539 @cindex alignment for NEON instructions
540 Some NEON load/store instructions allow an optional address
542 The ARM documentation specifies that this is indicated by
543 @samp{@@ @var{align}}. However GAS already interprets
544 the @samp{@@} character as a "line comment" start,
545 so @samp{: @var{align}} is used instead. For example:
548 vld1.8 @{q0@}, [r0, :128]
551 @node ARM Floating Point
552 @section Floating Point
554 @cindex floating point, ARM (@sc{ieee})
555 @cindex ARM floating point (@sc{ieee})
556 The ARM family uses @sc{ieee} floating-point numbers.
559 @section ARM Machine Directives
561 @cindex machine directives, ARM
562 @cindex ARM machine directives
565 @c AAAAAAAAAAAAAAAAAAAAAAAAA
567 @cindex @code{.2byte} directive, ARM
568 @cindex @code{.4byte} directive, ARM
569 @cindex @code{.8byte} directive, ARM
570 @item .2byte @var{expression} [, @var{expression}]*
571 @itemx .4byte @var{expression} [, @var{expression}]*
572 @itemx .8byte @var{expression} [, @var{expression}]*
573 These directives write 2, 4 or 8 byte values to the output section.
575 @cindex @code{.align} directive, ARM
576 @item .align @var{expression} [, @var{expression}]
577 This is the generic @var{.align} directive. For the ARM however if the
578 first argument is zero (ie no alignment is needed) the assembler will
579 behave as if the argument had been 2 (ie pad to the next four byte
580 boundary). This is for compatibility with ARM's own assembler.
582 @cindex @code{.arch} directive, ARM
583 @item .arch @var{name}
584 Select the target architecture. Valid values for @var{name} are the same as
585 for the @option{-march} commandline option.
587 Specifying @code{.arch} clears any previously selected architecture
590 @cindex @code{.arch_extension} directive, ARM
591 @item .arch_extension @var{name}
592 Add or remove an architecture extension to the target architecture. Valid
593 values for @var{name} are the same as those accepted as architectural
594 extensions by the @option{-mcpu} commandline option.
596 @code{.arch_extension} may be used multiple times to add or remove extensions
597 incrementally to the architecture being compiled for.
599 @cindex @code{.arm} directive, ARM
601 This performs the same action as @var{.code 32}.
603 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
605 @cindex @code{.bss} directive, ARM
607 This directive switches to the @code{.bss} section.
609 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
611 @cindex @code{.cantunwind} directive, ARM
613 Prevents unwinding through the current function. No personality routine
614 or exception table data is required or permitted.
616 @cindex @code{.code} directive, ARM
617 @item .code @code{[16|32]}
618 This directive selects the instruction set being generated. The value 16
619 selects Thumb, with the value 32 selecting ARM.
621 @cindex @code{.cpu} directive, ARM
622 @item .cpu @var{name}
623 Select the target processor. Valid values for @var{name} are the same as
624 for the @option{-mcpu} commandline option.
626 Specifying @code{.cpu} clears any previously selected architecture
629 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
631 @cindex @code{.dn} and @code{.qn} directives, ARM
632 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
633 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
635 The @code{dn} and @code{qn} directives are used to create typed
636 and/or indexed register aliases for use in Advanced SIMD Extension
637 (Neon) instructions. The former should be used to create aliases
638 of double-precision registers, and the latter to create aliases of
639 quad-precision registers.
641 If these directives are used to create typed aliases, those aliases can
642 be used in Neon instructions instead of writing types after the mnemonic
643 or after each operand. For example:
652 This is equivalent to writing the following:
658 Aliases created using @code{dn} or @code{qn} can be destroyed using
661 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
663 @cindex @code{.eabi_attribute} directive, ARM
664 @item .eabi_attribute @var{tag}, @var{value}
665 Set the EABI object attribute @var{tag} to @var{value}.
667 The @var{tag} is either an attribute number, or one of the following:
668 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
669 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
670 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
671 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
672 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
673 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
674 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
675 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
676 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
677 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
678 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
679 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
680 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
681 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
682 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
683 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
684 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
685 @code{Tag_conformance}, @code{Tag_T2EE_use},
686 @code{Tag_Virtualization_use}
688 The @var{value} is either a @code{number}, @code{"string"}, or
689 @code{number, "string"} depending on the tag.
691 Note - the following legacy values are also accepted by @var{tag}:
692 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
693 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
695 @cindex @code{.even} directive, ARM
697 This directive aligns to an even-numbered address.
699 @cindex @code{.extend} directive, ARM
700 @cindex @code{.ldouble} directive, ARM
701 @item .extend @var{expression} [, @var{expression}]*
702 @itemx .ldouble @var{expression} [, @var{expression}]*
703 These directives write 12byte long double floating-point values to the
704 output section. These are not compatible with current ARM processors
707 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
710 @cindex @code{.fnend} directive, ARM
712 Marks the end of a function with an unwind table entry. The unwind index
713 table entry is created when this directive is processed.
715 If no personality routine has been specified then standard personality
716 routine 0 or 1 will be used, depending on the number of unwind opcodes
720 @cindex @code{.fnstart} directive, ARM
722 Marks the start of a function with an unwind table entry.
724 @cindex @code{.force_thumb} directive, ARM
726 This directive forces the selection of Thumb instructions, even if the
727 target processor does not support those instructions
729 @cindex @code{.fpu} directive, ARM
730 @item .fpu @var{name}
731 Select the floating-point unit to assemble for. Valid values for @var{name}
732 are the same as for the @option{-mfpu} commandline option.
734 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
735 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
737 @cindex @code{.handlerdata} directive, ARM
739 Marks the end of the current function, and the start of the exception table
740 entry for that function. Anything between this directive and the
741 @code{.fnend} directive will be added to the exception table entry.
743 Must be preceded by a @code{.personality} or @code{.personalityindex}
746 @c IIIIIIIIIIIIIIIIIIIIIIIIII
748 @cindex @code{.inst} directive, ARM
749 @item .inst @var{opcode} [ , @dots{} ]
750 @itemx .inst.n @var{opcode} [ , @dots{} ]
751 @itemx .inst.w @var{opcode} [ , @dots{} ]
752 Generates the instruction corresponding to the numerical value @var{opcode}.
753 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
754 specified explicitly, overriding the normal encoding rules.
756 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
757 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
758 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
760 @item .ldouble @var{expression} [, @var{expression}]*
763 @cindex @code{.ltorg} directive, ARM
765 This directive causes the current contents of the literal pool to be
766 dumped into the current section (which is assumed to be the .text
767 section) at the current location (aligned to a word boundary).
768 @code{GAS} maintains a separate literal pool for each section and each
769 sub-section. The @code{.ltorg} directive will only affect the literal
770 pool of the current section and sub-section. At the end of assembly
771 all remaining, un-empty literal pools will automatically be dumped.
773 Note - older versions of @code{GAS} would dump the current literal
774 pool any time a section change occurred. This is no longer done, since
775 it prevents accurate control of the placement of literal pools.
777 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
779 @cindex @code{.movsp} directive, ARM
780 @item .movsp @var{reg} [, #@var{offset}]
781 Tell the unwinder that @var{reg} contains an offset from the current
782 stack pointer. If @var{offset} is not specified then it is assumed to be
785 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
786 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
788 @cindex @code{.object_arch} directive, ARM
789 @item .object_arch @var{name}
790 Override the architecture recorded in the EABI object attribute section.
791 Valid values for @var{name} are the same as for the @code{.arch} directive.
792 Typically this is useful when code uses runtime detection of CPU features.
794 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
796 @cindex @code{.packed} directive, ARM
797 @item .packed @var{expression} [, @var{expression}]*
798 This directive writes 12-byte packed floating-point values to the
799 output section. These are not compatible with current ARM processors
803 @cindex @code{.pad} directive, ARM
804 @item .pad #@var{count}
805 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
806 A positive value indicates the function prologue allocated stack space by
807 decrementing the stack pointer.
809 @cindex @code{.personality} directive, ARM
810 @item .personality @var{name}
811 Sets the personality routine for the current function to @var{name}.
813 @cindex @code{.personalityindex} directive, ARM
814 @item .personalityindex @var{index}
815 Sets the personality routine for the current function to the EABI standard
816 routine number @var{index}
818 @cindex @code{.pool} directive, ARM
820 This is a synonym for .ltorg.
822 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
823 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
825 @cindex @code{.req} directive, ARM
826 @item @var{name} .req @var{register name}
827 This creates an alias for @var{register name} called @var{name}. For
834 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
837 @cindex @code{.save} directive, ARM
838 @item .save @var{reglist}
839 Generate unwinder annotations to restore the registers in @var{reglist}.
840 The format of @var{reglist} is the same as the corresponding store-multiple
844 @exdent @emph{core registers}
845 .save @{r4, r5, r6, lr@}
846 stmfd sp!, @{r4, r5, r6, lr@}
847 @exdent @emph{FPA registers}
850 @exdent @emph{VFP registers}
851 .save @{d8, d9, d10@}
852 fstmdx sp!, @{d8, d9, d10@}
853 @exdent @emph{iWMMXt registers}
855 wstrd wr11, [sp, #-8]!
856 wstrd wr10, [sp, #-8]!
859 wstrd wr11, [sp, #-8]!
861 wstrd wr10, [sp, #-8]!
865 @cindex @code{.setfp} directive, ARM
866 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
867 Make all unwinder annotations relative to a frame pointer. Without this
868 the unwinder will use offsets from the stack pointer.
870 The syntax of this directive is the same as the @code{add} or @code{mov}
871 instruction used to set the frame pointer. @var{spreg} must be either
872 @code{sp} or mentioned in a previous @code{.movsp} directive.
882 @cindex @code{.secrel32} directive, ARM
883 @item .secrel32 @var{expression} [, @var{expression}]*
884 This directive emits relocations that evaluate to the section-relative
885 offset of each expression's symbol. This directive is only supported
888 @cindex @code{.syntax} directive, ARM
889 @item .syntax [@code{unified} | @code{divided}]
890 This directive sets the Instruction Set Syntax as described in the
891 @ref{ARM-Instruction-Set} section.
893 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
895 @cindex @code{.thumb} directive, ARM
897 This performs the same action as @var{.code 16}.
899 @cindex @code{.thumb_func} directive, ARM
901 This directive specifies that the following symbol is the name of a
902 Thumb encoded function. This information is necessary in order to allow
903 the assembler and linker to generate correct code for interworking
904 between Arm and Thumb instructions and should be used even if
905 interworking is not going to be performed. The presence of this
906 directive also implies @code{.thumb}
908 This directive is not neccessary when generating EABI objects. On these
909 targets the encoding is implicit when generating Thumb code.
911 @cindex @code{.thumb_set} directive, ARM
913 This performs the equivalent of a @code{.set} directive in that it
914 creates a symbol which is an alias for another symbol (possibly not yet
915 defined). This directive also has the added property in that it marks
916 the aliased symbol as being a thumb function entry point, in the same
917 way that the @code{.thumb_func} directive does.
919 @cindex @code{.tlsdescseq} directive, ARM
920 @item .tlsdescseq @var{tls-variable}
921 This directive is used to annotate parts of an inlined TLS descriptor
922 trampoline. Normally the trampoline is provided by the linker, and
923 this directive is not needed.
925 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
927 @cindex @code{.unreq} directive, ARM
928 @item .unreq @var{alias-name}
929 This undefines a register alias which was previously defined using the
930 @code{req}, @code{dn} or @code{qn} directives. For example:
937 An error occurs if the name is undefined. Note - this pseudo op can
938 be used to delete builtin in register name aliases (eg 'r0'). This
939 should only be done if it is really necessary.
941 @cindex @code{.unwind_raw} directive, ARM
942 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
943 Insert one of more arbitary unwind opcode bytes, which are known to adjust
944 the stack pointer by @var{offset} bytes.
946 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
949 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
951 @cindex @code{.vsave} directive, ARM
952 @item .vsave @var{vfp-reglist}
953 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
954 using FLDMD. Also works for VFPv3 registers
955 that are to be restored using VLDM.
956 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
960 @exdent @emph{VFP registers}
961 .vsave @{d8, d9, d10@}
962 fstmdd sp!, @{d8, d9, d10@}
963 @exdent @emph{VFPv3 registers}
964 .vsave @{d15, d16, d17@}
965 vstm sp!, @{d15, d16, d17@}
968 Since FLDMX and FSTMX are now deprecated, this directive should be
969 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
971 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
972 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
973 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
974 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
982 @cindex opcodes for ARM
983 @code{@value{AS}} implements all the standard ARM opcodes. It also
984 implements several pseudo opcodes, including several synthetic load
989 @cindex @code{NOP} pseudo op, ARM
995 This pseudo op will always evaluate to a legal ARM instruction that does
996 nothing. Currently it will evaluate to MOV r0, r0.
998 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1001 ldr <register> , = <expression>
1004 If expression evaluates to a numeric constant then a MOV or MVN
1005 instruction will be used in place of the LDR instruction, if the
1006 constant can be generated by either of these instructions. Otherwise
1007 the constant will be placed into the nearest literal pool (if it not
1008 already there) and a PC relative LDR instruction will be generated.
1010 @cindex @code{ADR reg,<label>} pseudo op, ARM
1013 adr <register> <label>
1016 This instruction will load the address of @var{label} into the indicated
1017 register. The instruction will evaluate to a PC relative ADD or SUB
1018 instruction depending upon where the label is located. If the label is
1019 out of range, or if it is not defined in the same file (and section) as
1020 the ADR instruction, then an error will be generated. This instruction
1021 will not make use of the literal pool.
1023 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1026 adrl <register> <label>
1029 This instruction will load the address of @var{label} into the indicated
1030 register. The instruction will evaluate to one or two PC relative ADD
1031 or SUB instructions depending upon where the label is located. If a
1032 second instruction is not needed a NOP instruction will be generated in
1033 its place, so that this instruction is always 8 bytes long.
1035 If the label is out of range, or if it is not defined in the same file
1036 (and section) as the ADRL instruction, then an error will be generated.
1037 This instruction will not make use of the literal pool.
1041 For information on the ARM or Thumb instruction sets, see @cite{ARM
1042 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1045 @node ARM Mapping Symbols
1046 @section Mapping Symbols
1048 The ARM ELF specification requires that special symbols be inserted
1049 into object files to mark certain features:
1055 At the start of a region of code containing ARM instructions.
1059 At the start of a region of code containing THUMB instructions.
1063 At the start of a region of data.
1067 The assembler will automatically insert these symbols for you - there
1068 is no need to code them yourself. Support for tagging symbols ($b,
1069 $f, $p and $m) which is also mentioned in the current ARM ELF
1070 specification is not implemented. This is because they have been
1071 dropped from the new EABI and so tools cannot rely upon their
1074 @node ARM Unwinding Tutorial
1077 The ABI for the ARM Architecture specifies a standard format for
1078 exception unwind information. This information is used when an
1079 exception is thrown to determine where control should be transferred.
1080 In particular, the unwind information is used to determine which
1081 function called the function that threw the exception, and which
1082 function called that one, and so forth. This information is also used
1083 to restore the values of callee-saved registers in the function
1084 catching the exception.
1086 If you are writing functions in assembly code, and those functions
1087 call other functions that throw exceptions, you must use assembly
1088 pseudo ops to ensure that appropriate exception unwind information is
1089 generated. Otherwise, if one of the functions called by your assembly
1090 code throws an exception, the run-time library will be unable to
1091 unwind the stack through your assembly code and your program will not
1094 To illustrate the use of these pseudo ops, we will examine the code
1095 that G++ generates for the following C++ input:
1098 void callee (int *);
1109 This example does not show how to throw or catch an exception from
1110 assembly code. That is a much more complex operation and should
1111 always be done in a high-level language, such as C++, that directly
1112 supports exceptions.
1114 The code generated by one particular version of G++ when compiling the
1121 @ Function supports interworking.
1122 @ args = 0, pretend = 0, frame = 8
1123 @ frame_needed = 1, uses_anonymous_args = 0
1145 Of course, the sequence of instructions varies based on the options
1146 you pass to GCC and on the version of GCC in use. The exact
1147 instructions are not important since we are focusing on the pseudo ops
1148 that are used to generate unwind information.
1150 An important assumption made by the unwinder is that the stack frame
1151 does not change during the body of the function. In particular, since
1152 we assume that the assembly code does not itself throw an exception,
1153 the only point where an exception can be thrown is from a call, such
1154 as the @code{bl} instruction above. At each call site, the same saved
1155 registers (including @code{lr}, which indicates the return address)
1156 must be located in the same locations relative to the frame pointer.
1158 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1159 op appears immediately before the first instruction of the function
1160 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1161 op appears immediately after the last instruction of the function.
1162 These pseudo ops specify the range of the function.
1164 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1165 @code{.pad}) matters; their exact locations are irrelevant. In the
1166 example above, the compiler emits the pseudo ops with particular
1167 instructions. That makes it easier to understand the code, but it is
1168 not required for correctness. It would work just as well to emit all
1169 of the pseudo ops other than @code{.fnend} in the same order, but
1170 immediately after @code{.fnstart}.
1172 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1173 indicates registers that have been saved to the stack so that they can
1174 be restored before the function returns. The argument to the
1175 @code{.save} pseudo op is a list of registers to save. If a register
1176 is ``callee-saved'' (as specified by the ABI) and is modified by the
1177 function you are writing, then your code must save the value before it
1178 is modified and restore the original value before the function
1179 returns. If an exception is thrown, the run-time library restores the
1180 values of these registers from their locations on the stack before
1181 returning control to the exception handler. (Of course, if an
1182 exception is not thrown, the function that contains the @code{.save}
1183 pseudo op restores these registers in the function epilogue, as is
1184 done with the @code{ldmfd} instruction above.)
1186 You do not have to save callee-saved registers at the very beginning
1187 of the function and you do not need to use the @code{.save} pseudo op
1188 immediately following the point at which the registers are saved.
1189 However, if you modify a callee-saved register, you must save it on
1190 the stack before modifying it and before calling any functions which
1191 might throw an exception. And, you must use the @code{.save} pseudo
1192 op to indicate that you have done so.
1194 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1195 modification of the stack pointer that does not save any registers.
1196 The argument is the number of bytes (in decimal) that are subtracted
1197 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1198 subtracting from the stack pointer increases the size of the stack.)
1200 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1201 indicates the register that contains the frame pointer. The first
1202 argument is the register that is set, which is typically @code{fp}.
1203 The second argument indicates the register from which the frame
1204 pointer takes its value. The third argument, if present, is the value
1205 (in decimal) added to the register specified by the second argument to
1206 compute the value of the frame pointer. You should not modify the
1207 frame pointer in the body of the function.
1209 If you do not use a frame pointer, then you should not use the
1210 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1211 should avoid modifying the stack pointer outside of the function
1212 prologue. Otherwise, the run-time library will be unable to find
1213 saved registers when it is unwinding the stack.
1215 The pseudo ops described above are sufficient for writing assembly
1216 code that calls functions which may throw exceptions. If you need to
1217 know more about the object-file format used to represent unwind
1218 information, you may consult the @cite{Exception Handling ABI for the
1219 ARM Architecture} available from @uref{http://infocenter.arm.com}.