1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
113 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
114 @code{i80200} (Intel XScale processor)
115 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
118 The special name @code{all} may be used to allow the
119 assembler to accept instructions valid for any ARM processor.
121 In addition to the basic instruction set, the assembler can be told to
122 accept various extension mnemonics that extend the processor using the
123 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
124 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
125 are currently supported:
131 @cindex @code{-march=} command line option, ARM
132 @item -march=@var{architecture}[+@var{extension}@dots{}]
133 This option specifies the target architecture. The assembler will issue
134 an error message if an attempt is made to assemble an instruction which
135 will not execute on the target architecture. The following architecture
136 names are recognized:
164 If both @code{-mcpu} and
165 @code{-march} are specified, the assembler will use
166 the setting for @code{-mcpu}.
168 The architecture option can be extended with the same instruction set
169 extension options as the @code{-mcpu} option.
171 @cindex @code{-mfpu=} command line option, ARM
172 @item -mfpu=@var{floating-point-format}
174 This option specifies the floating point format to assemble for. The
175 assembler will issue an error message if an attempt is made to assemble
176 an instruction which will not execute on the target floating point unit.
177 The following format options are recognized:
199 In addition to determining which instructions are assembled, this option
200 also affects the way in which the @code{.double} assembler directive behaves
201 when assembling little-endian code.
203 The default is dependent on the processor selected. For Architecture 5 or
204 later, the default is to assembler for VFP instructions; for earlier
205 architectures the default is to assemble for FPA instructions.
207 @cindex @code{-mthumb} command line option, ARM
209 This option specifies that the assembler should start assembling Thumb
210 instructions; that is, it should behave as though the file starts with a
211 @code{.code 16} directive.
213 @cindex @code{-mthumb-interwork} command line option, ARM
214 @item -mthumb-interwork
215 This option specifies that the output generated by the assembler should
216 be marked as supporting interworking.
218 @cindex @code{-mapcs} command line option, ARM
219 @item -mapcs @code{[26|32]}
220 This option specifies that the output generated by the assembler should
221 be marked as supporting the indicated version of the Arm Procedure.
224 @cindex @code{-matpcs} command line option, ARM
226 This option specifies that the output generated by the assembler should
227 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
228 enabled this option will cause the assembler to create an empty
229 debugging section in the object file called .arm.atpcs. Debuggers can
230 use this to determine the ABI being used by.
232 @cindex @code{-mapcs-float} command line option, ARM
234 This indicates the floating point variant of the APCS should be
235 used. In this variant floating point arguments are passed in FP
236 registers rather than integer registers.
238 @cindex @code{-mapcs-reentrant} command line option, ARM
239 @item -mapcs-reentrant
240 This indicates that the reentrant variant of the APCS should be used.
241 This variant supports position independent code.
243 @cindex @code{-mfloat-abi=} command line option, ARM
244 @item -mfloat-abi=@var{abi}
245 This option specifies that the output generated by the assembler should be
246 marked as using specified floating point ABI.
247 The following values are recognized:
253 @cindex @code{-eabi=} command line option, ARM
254 @item -meabi=@var{ver}
255 This option specifies which EABI version the produced object files should
257 The following values are recognised:
263 @cindex @code{-EB} command line option, ARM
265 This option specifies that the output generated by the assembler should
266 be marked as being encoded for a big-endian processor.
268 @cindex @code{-EL} command line option, ARM
270 This option specifies that the output generated by the assembler should
271 be marked as being encoded for a little-endian processor.
273 @cindex @code{-k} command line option, ARM
274 @cindex PIC code generation for ARM
276 This option specifies that the output of the assembler should be marked
277 as position-independent code (PIC).
285 * ARM-Chars:: Special Characters
286 * ARM-Regs:: Register Names
287 * ARM-Relocations:: Relocations
291 @subsection Special Characters
293 @cindex line comment character, ARM
294 @cindex ARM line comment character
295 The presence of a @samp{@@} on a line indicates the start of a comment
296 that extends to the end of the current line. If a @samp{#} appears as
297 the first character of a line, the whole line is treated as a comment.
299 @cindex line separator, ARM
300 @cindex statement separator, ARM
301 @cindex ARM line separator
302 The @samp{;} character can be used instead of a newline to separate
305 @cindex immediate character, ARM
306 @cindex ARM immediate character
307 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
309 @cindex identifiers, ARM
310 @cindex ARM identifiers
311 *TODO* Explain about /data modifier on symbols.
314 @subsection Register Names
316 @cindex ARM register names
317 @cindex register names, ARM
318 *TODO* Explain about ARM register naming, and the predefined names.
320 @node ARM Floating Point
321 @section Floating Point
323 @cindex floating point, ARM (@sc{ieee})
324 @cindex ARM floating point (@sc{ieee})
325 The ARM family uses @sc{ieee} floating-point numbers.
327 @node ARM-Relocations
328 @subsection ARM relocation generation
330 @cindex data relocations, ARM
331 @cindex ARM data relocations
332 Specific data relocations can be generated by putting the relocation name
333 in parentheses after the symbol name. For example:
339 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
341 The following relocations are supported:
354 For compatibility with older toolchains the assembler also accepts
355 @code{(PLT)} after branch targets. This will generate the deprecated
356 @samp{R_ARM_PLT32} relocation.
358 @cindex MOVW and MOVT relocations, ARM
359 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
360 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
361 respectively. For example to load the 32-bit addresss of foo into r0:
364 MOVW r0, #:lower16:foo
365 MOVT r0, #:upper16:foo
369 @section ARM Machine Directives
371 @cindex machine directives, ARM
372 @cindex ARM machine directives
375 @cindex @code{align} directive, ARM
376 @item .align @var{expression} [, @var{expression}]
377 This is the generic @var{.align} directive. For the ARM however if the
378 first argument is zero (ie no alignment is needed) the assembler will
379 behave as if the argument had been 2 (ie pad to the next four byte
380 boundary). This is for compatibility with ARM's own assembler.
382 @cindex @code{req} directive, ARM
383 @item @var{name} .req @var{register name}
384 This creates an alias for @var{register name} called @var{name}. For
391 @cindex @code{unreq} directive, ARM
392 @item .unreq @var{alias-name}
393 This undefines a register alias which was previously defined using the
394 @code{req} directive. For example:
401 An error occurs if the name is undefined. Note - this pseudo op can
402 be used to delete builtin in register name aliases (eg 'r0'). This
403 should only be done if it is really necessary.
405 @cindex @code{code} directive, ARM
406 @item .code @code{[16|32]}
407 This directive selects the instruction set being generated. The value 16
408 selects Thumb, with the value 32 selecting ARM.
410 @cindex @code{thumb} directive, ARM
412 This performs the same action as @var{.code 16}.
414 @cindex @code{arm} directive, ARM
416 This performs the same action as @var{.code 32}.
418 @cindex @code{force_thumb} directive, ARM
420 This directive forces the selection of Thumb instructions, even if the
421 target processor does not support those instructions
423 @cindex @code{thumb_func} directive, ARM
425 This directive specifies that the following symbol is the name of a
426 Thumb encoded function. This information is necessary in order to allow
427 the assembler and linker to generate correct code for interworking
428 between Arm and Thumb instructions and should be used even if
429 interworking is not going to be performed. The presence of this
430 directive also implies @code{.thumb}
432 @cindex @code{thumb_set} directive, ARM
434 This performs the equivalent of a @code{.set} directive in that it
435 creates a symbol which is an alias for another symbol (possibly not yet
436 defined). This directive also has the added property in that it marks
437 the aliased symbol as being a thumb function entry point, in the same
438 way that the @code{.thumb_func} directive does.
440 @cindex @code{.ltorg} directive, ARM
442 This directive causes the current contents of the literal pool to be
443 dumped into the current section (which is assumed to be the .text
444 section) at the current location (aligned to a word boundary).
445 @code{GAS} maintains a separate literal pool for each section and each
446 sub-section. The @code{.ltorg} directive will only affect the literal
447 pool of the current section and sub-section. At the end of assembly
448 all remaining, un-empty literal pools will automatically be dumped.
450 Note - older versions of @code{GAS} would dump the current literal
451 pool any time a section change occurred. This is no longer done, since
452 it prevents accurate control of the placement of literal pools.
454 @cindex @code{.pool} directive, ARM
456 This is a synonym for .ltorg.
458 @cindex @code{.fnstart} directive, ARM
459 @item .unwind_fnstart
460 Marks the start of a function with an unwind table entry.
462 @cindex @code{.fnend} directive, ARM
464 Marks the end of a function with an unwind table entry. The unwind index
465 table entry is created when this directive is processed.
467 If no personality routine has been specified then standard personality
468 routine 0 or 1 will be used, depending on the number of unwind opcodes
471 @cindex @code{.cantunwind} directive, ARM
473 Prevents unwinding through the current function. No personality routine
474 or exception table data is required or permitted.
476 @cindex @code{.personality} directive, ARM
477 @item .personality @var{name}
478 Sets the personality routine for the current function to @var{name}.
480 @cindex @code{.personalityindex} directive, ARM
481 @item .personalityindex @var{index}
482 Sets the personality routine for the current function to the EABI standard
483 routine number @var{index}
485 @cindex @code{.handlerdata} directive, ARM
487 Marks the end of the current function, and the start of the exception table
488 entry for that function. Anything between this directive and the
489 @code{.fnend} directive will be added to the exception table entry.
491 Must be preceded by a @code{.personality} or @code{.personalityindex}
494 @cindex @code{.save} directive, ARM
495 @item .save @var{reglist}
496 Generate unwinder annotations to restore the registers in @var{reglist}.
497 The format of @var{reglist} is the same as the corresponding store-multiple
501 @exdent @emph{core registers}
502 .save @{r4, r5, r6, lr@}
503 stmfd sp!, @{r4, r5, r6, lr@}
504 @exdent @emph{FPA registers}
507 @exdent @emph{VFP registers}
508 .save @{d8, d9, d10@}
509 fstmdf sp!, @{d8, d9, d10@}
510 @exdent @emph{iWMMXt registers}
512 wstrd wr11, [sp, #-8]!
513 wstrd wr10, [sp, #-8]!
516 wstrd wr11, [sp, #-8]!
518 wstrd wr10, [sp, #-8]!
521 @cindex @code{.pad} directive, ARM
522 @item .pad #@var{count}
523 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
524 A positive value indicates the function prologue allocated stack space by
525 decrementing the stack pointer.
527 @cindex @code{.movsp} directive, ARM
528 @item .movsp @var{reg}
529 Tell the unwinder that @var{reg} contains the current stack pointer.
531 @cindex @code{.setfp} directive, ARM
532 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
533 Make all unwinder annotations relaive to a frame pointer. Without this
534 the unwinder will use offsets from the stack pointer.
536 The syntax of this directive is the same as the @code{sub} or @code{mov}
537 instruction used to set the frame pointer. @var{spreg} must be either
538 @code{sp} or mentioned in a previous @code{.movsp} directive.
548 @cindex @code{.unwind_raw} directive, ARM
549 @item .raw @var{offset}, @var{byte1}, @dots{}
550 Insert one of more arbitary unwind opcode bytes, which are known to adjust
551 the stack pointer by @var{offset} bytes.
553 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
556 @cindex @code{.cpu} directive, ARM
557 @item .cpu @var{name}
558 Select the target processor. Valid values for @var{name} are the same as
559 for the @option{-mcpu} commandline option.
561 @cindex @code{.arch} directive, ARM
562 @item .arch @var{name}
563 Select the target architecture. Valid values for @var{name} are the same as
564 for the @option{-march} commandline option.
566 @cindex @code{.fpu} directive, ARM
567 @item .fpu @var{name}
568 Select the floating point unit to assemble for. Valid values for @var{name}
569 are the same as for the @option{-mfpu} commandline option.
571 @cindex @code{.eabi_attribute} directive, ARM
572 @item .eabi_attribute @var{tag}, @var{value}
573 Set the EABI object attribute number @var{tag} to @var{value}. The value
574 is either a @code{number}, @code{"string"}, or @code{number, "string"}
575 depending on the tag.
583 @cindex opcodes for ARM
584 @code{@value{AS}} implements all the standard ARM opcodes. It also
585 implements several pseudo opcodes, including several synthetic load
590 @cindex @code{NOP} pseudo op, ARM
596 This pseudo op will always evaluate to a legal ARM instruction that does
597 nothing. Currently it will evaluate to MOV r0, r0.
599 @cindex @code{LDR reg,=<label>} pseudo op, ARM
602 ldr <register> , = <expression>
605 If expression evaluates to a numeric constant then a MOV or MVN
606 instruction will be used in place of the LDR instruction, if the
607 constant can be generated by either of these instructions. Otherwise
608 the constant will be placed into the nearest literal pool (if it not
609 already there) and a PC relative LDR instruction will be generated.
611 @cindex @code{ADR reg,<label>} pseudo op, ARM
614 adr <register> <label>
617 This instruction will load the address of @var{label} into the indicated
618 register. The instruction will evaluate to a PC relative ADD or SUB
619 instruction depending upon where the label is located. If the label is
620 out of range, or if it is not defined in the same file (and section) as
621 the ADR instruction, then an error will be generated. This instruction
622 will not make use of the literal pool.
624 @cindex @code{ADRL reg,<label>} pseudo op, ARM
627 adrl <register> <label>
630 This instruction will load the address of @var{label} into the indicated
631 register. The instruction will evaluate to one or two PC relative ADD
632 or SUB instructions depending upon where the label is located. If a
633 second instruction is not needed a NOP instruction will be generated in
634 its place, so that this instruction is always 8 bytes long.
636 If the label is out of range, or if it is not defined in the same file
637 (and section) as the ADRL instruction, then an error will be generated.
638 This instruction will not make use of the literal pool.
642 For information on the ARM or Thumb instruction sets, see @cite{ARM
643 Software Development Toolkit Reference Manual}, Advanced RISC Machines
646 @node ARM Mapping Symbols
647 @section Mapping Symbols
649 The ARM ELF specification requires that special symbols be inserted
650 into object files to mark certain features:
656 At the start of a region of code containing ARM instructions.
660 At the start of a region of code containing THUMB instructions.
664 At the start of a region of data.
668 The assembler will automatically insert these symbols for you - there
669 is no need to code them yourself. Support for tagging symbols ($b,
670 $f, $p and $m) which is also mentioned in the current ARM ELF
671 specification is not implemented. This is because they have been
672 dropped from the new EABI and so tools cannot rely upon their