1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
2 @c 2008, 2009 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
121 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
122 @code{i80200} (Intel XScale processor)
123 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
126 The special name @code{all} may be used to allow the
127 assembler to accept instructions valid for any ARM processor.
129 In addition to the basic instruction set, the assembler can be told to
130 accept various extension mnemonics that extend the processor using the
131 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
132 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
133 are currently supported:
139 @cindex @code{-march=} command line option, ARM
140 @item -march=@var{architecture}[+@var{extension}@dots{}]
141 This option specifies the target architecture. The assembler will issue
142 an error message if an attempt is made to assemble an instruction which
143 will not execute on the target architecture. The following architecture
144 names are recognized:
172 If both @code{-mcpu} and
173 @code{-march} are specified, the assembler will use
174 the setting for @code{-mcpu}.
176 The architecture option can be extended with the same instruction set
177 extension options as the @code{-mcpu} option.
179 @cindex @code{-mfpu=} command line option, ARM
180 @item -mfpu=@var{floating-point-format}
182 This option specifies the floating point format to assemble for. The
183 assembler will issue an error message if an attempt is made to assemble
184 an instruction which will not execute on the target floating point unit.
185 The following format options are recognized:
211 In addition to determining which instructions are assembled, this option
212 also affects the way in which the @code{.double} assembler directive behaves
213 when assembling little-endian code.
215 The default is dependent on the processor selected. For Architecture 5 or
216 later, the default is to assembler for VFP instructions; for earlier
217 architectures the default is to assemble for FPA instructions.
219 @cindex @code{-mthumb} command line option, ARM
221 This option specifies that the assembler should start assembling Thumb
222 instructions; that is, it should behave as though the file starts with a
223 @code{.code 16} directive.
225 @cindex @code{-mthumb-interwork} command line option, ARM
226 @item -mthumb-interwork
227 This option specifies that the output generated by the assembler should
228 be marked as supporting interworking.
230 @cindex @code{-mauto-it} command line option, ARM
232 This option enables the automatic generation of IT instructions for
233 conditional instructions not covered by an IT block.
235 @cindex @code{-mapcs} command line option, ARM
236 @item -mapcs @code{[26|32]}
237 This option specifies that the output generated by the assembler should
238 be marked as supporting the indicated version of the Arm Procedure.
241 @cindex @code{-matpcs} command line option, ARM
243 This option specifies that the output generated by the assembler should
244 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
245 enabled this option will cause the assembler to create an empty
246 debugging section in the object file called .arm.atpcs. Debuggers can
247 use this to determine the ABI being used by.
249 @cindex @code{-mapcs-float} command line option, ARM
251 This indicates the floating point variant of the APCS should be
252 used. In this variant floating point arguments are passed in FP
253 registers rather than integer registers.
255 @cindex @code{-mapcs-reentrant} command line option, ARM
256 @item -mapcs-reentrant
257 This indicates that the reentrant variant of the APCS should be used.
258 This variant supports position independent code.
260 @cindex @code{-mfloat-abi=} command line option, ARM
261 @item -mfloat-abi=@var{abi}
262 This option specifies that the output generated by the assembler should be
263 marked as using specified floating point ABI.
264 The following values are recognized:
270 @cindex @code{-eabi=} command line option, ARM
271 @item -meabi=@var{ver}
272 This option specifies which EABI version the produced object files should
274 The following values are recognized:
280 @cindex @code{-EB} command line option, ARM
282 This option specifies that the output generated by the assembler should
283 be marked as being encoded for a big-endian processor.
285 @cindex @code{-EL} command line option, ARM
287 This option specifies that the output generated by the assembler should
288 be marked as being encoded for a little-endian processor.
290 @cindex @code{-k} command line option, ARM
291 @cindex PIC code generation for ARM
293 This option specifies that the output of the assembler should be marked
294 as position-independent code (PIC).
296 @cindex @code{--fix-v4bx} command line option, ARM
298 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
299 the linker option of the same name.
301 @cindex @code{-mwarn-deprecated} command line option, ARM
302 @item -mwarn-deprecated
303 @itemx -mno-warn-deprecated
304 Enable or disable warnings about using deprecated options or
305 features. The default is to warn.
313 * ARM-Chars:: Special Characters
314 * ARM-Regs:: Register Names
315 * ARM-Relocations:: Relocations
319 @subsection Special Characters
321 @cindex line comment character, ARM
322 @cindex ARM line comment character
323 The presence of a @samp{@@} on a line indicates the start of a comment
324 that extends to the end of the current line. If a @samp{#} appears as
325 the first character of a line, the whole line is treated as a comment.
327 @cindex line separator, ARM
328 @cindex statement separator, ARM
329 @cindex ARM line separator
330 The @samp{;} character can be used instead of a newline to separate
333 @cindex immediate character, ARM
334 @cindex ARM immediate character
335 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
337 @cindex identifiers, ARM
338 @cindex ARM identifiers
339 *TODO* Explain about /data modifier on symbols.
342 @subsection Register Names
344 @cindex ARM register names
345 @cindex register names, ARM
346 *TODO* Explain about ARM register naming, and the predefined names.
348 @node ARM Floating Point
349 @section Floating Point
351 @cindex floating point, ARM (@sc{ieee})
352 @cindex ARM floating point (@sc{ieee})
353 The ARM family uses @sc{ieee} floating-point numbers.
355 @node ARM-Relocations
356 @subsection ARM relocation generation
358 @cindex data relocations, ARM
359 @cindex ARM data relocations
360 Specific data relocations can be generated by putting the relocation name
361 in parentheses after the symbol name. For example:
367 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
369 The following relocations are supported:
382 For compatibility with older toolchains the assembler also accepts
383 @code{(PLT)} after branch targets. This will generate the deprecated
384 @samp{R_ARM_PLT32} relocation.
386 @cindex MOVW and MOVT relocations, ARM
387 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
388 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
389 respectively. For example to load the 32-bit address of foo into r0:
392 MOVW r0, #:lower16:foo
393 MOVT r0, #:upper16:foo
397 @section ARM Machine Directives
399 @cindex machine directives, ARM
400 @cindex ARM machine directives
403 @c AAAAAAAAAAAAAAAAAAAAAAAAA
405 @cindex @code{.2byte} directive, ARM
406 @cindex @code{.4byte} directive, ARM
407 @cindex @code{.8byte} directive, ARM
408 @item .2byte @var{expression} [, @var{expression}]*
409 @itemx .4byte @var{expression} [, @var{expression}]*
410 @itemx .8byte @var{expression} [, @var{expression}]*
411 These directives write 2, 4 or 8 byte values to the output section.
413 @cindex @code{.align} directive, ARM
414 @item .align @var{expression} [, @var{expression}]
415 This is the generic @var{.align} directive. For the ARM however if the
416 first argument is zero (ie no alignment is needed) the assembler will
417 behave as if the argument had been 2 (ie pad to the next four byte
418 boundary). This is for compatibility with ARM's own assembler.
420 @cindex @code{.arch} directive, ARM
421 @item .arch @var{name}
422 Select the target architecture. Valid values for @var{name} are the same as
423 for the @option{-march} commandline option.
425 @cindex @code{.arm} directive, ARM
427 This performs the same action as @var{.code 32}.
430 @cindex @code{.pad} directive, ARM
431 @item .pad #@var{count}
432 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
433 A positive value indicates the function prologue allocated stack space by
434 decrementing the stack pointer.
436 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
438 @cindex @code{.bss} directive, ARM
440 This directive switches to the @code{.bss} section.
442 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
444 @cindex @code{.cantunwind} directive, ARM
446 Prevents unwinding through the current function. No personality routine
447 or exception table data is required or permitted.
449 @cindex @code{.code} directive, ARM
450 @item .code @code{[16|32]}
451 This directive selects the instruction set being generated. The value 16
452 selects Thumb, with the value 32 selecting ARM.
454 @cindex @code{.cpu} directive, ARM
455 @item .cpu @var{name}
456 Select the target processor. Valid values for @var{name} are the same as
457 for the @option{-mcpu} commandline option.
459 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
461 @cindex @code{.dn} and @code{.qn} directives, ARM
462 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
463 @item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
465 The @code{dn} and @code{qn} directives are used to create typed
466 and/or indexed register aliases for use in Advanced SIMD Extension
467 (Neon) instructions. The former should be used to create aliases
468 of double-precision registers, and the latter to create aliases of
469 quad-precision registers.
471 If these directives are used to create typed aliases, those aliases can
472 be used in Neon instructions instead of writing types after the mnemonic
473 or after each operand. For example:
482 This is equivalent to writing the following:
488 Aliases created using @code{dn} or @code{qn} can be destroyed using
491 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
493 @cindex @code{.eabi_attribute} directive, ARM
494 @item .eabi_attribute @var{tag}, @var{value}
495 Set the EABI object attribute @var{tag} to @var{value}.
497 The @var{tag} is either an attribute number, or one of the following:
498 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
499 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
500 @code{Tag_THUMB_ISA_use}, @code{Tag_VFP_arch}, @code{Tag_WMMX_arch},
501 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
502 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
503 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
504 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
505 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
506 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
507 @code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved},
508 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
509 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
510 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
511 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
512 @code{Tag_VFP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
513 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
514 @code{Tag_conformance}, @code{Tag_T2EE_use},
515 @code{Tag_Virtualization_use}, @code{Tag_MPextension_use}
517 The @var{value} is either a @code{number}, @code{"string"}, or
518 @code{number, "string"} depending on the tag.
520 @cindex @code{.even} directive, ARM
522 This directive aligns to an even-numbered address.
524 @cindex @code{.extend} directive, ARM
525 @cindex @code{.ldouble} directive, ARM
526 @item .extend @var{expression} [, @var{expression}]*
527 @itemx .ldouble @var{expression} [, @var{expression}]*
528 These directives write 12byte long double floating-point values to the
529 output section. These are not compatible with current ARM processors
532 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
535 @cindex @code{.fnend} directive, ARM
537 Marks the end of a function with an unwind table entry. The unwind index
538 table entry is created when this directive is processed.
540 If no personality routine has been specified then standard personality
541 routine 0 or 1 will be used, depending on the number of unwind opcodes
545 @cindex @code{.fnstart} directive, ARM
547 Marks the start of a function with an unwind table entry.
549 @cindex @code{.force_thumb} directive, ARM
551 This directive forces the selection of Thumb instructions, even if the
552 target processor does not support those instructions
554 @cindex @code{.fpu} directive, ARM
555 @item .fpu @var{name}
556 Select the floating-point unit to assemble for. Valid values for @var{name}
557 are the same as for the @option{-mfpu} commandline option.
559 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
560 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
562 @cindex @code{.handlerdata} directive, ARM
564 Marks the end of the current function, and the start of the exception table
565 entry for that function. Anything between this directive and the
566 @code{.fnend} directive will be added to the exception table entry.
568 Must be preceded by a @code{.personality} or @code{.personalityindex}
571 @c IIIIIIIIIIIIIIIIIIIIIIIIII
573 @cindex @code{.inst} directive, ARM
574 @item .inst @var{opcode} [ , @dots{} ]
575 @item .inst.n @var{opcode} [ , @dots{} ]
576 @item .inst.w @var{opcode} [ , @dots{} ]
577 Generates the instruction corresponding to the numerical value @var{opcode}.
578 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
579 specified explicitly, overriding the normal encoding rules.
581 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
582 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
583 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
585 @item .ldouble @var{expression} [, @var{expression}]*
588 @cindex @code{.ltorg} directive, ARM
590 This directive causes the current contents of the literal pool to be
591 dumped into the current section (which is assumed to be the .text
592 section) at the current location (aligned to a word boundary).
593 @code{GAS} maintains a separate literal pool for each section and each
594 sub-section. The @code{.ltorg} directive will only affect the literal
595 pool of the current section and sub-section. At the end of assembly
596 all remaining, un-empty literal pools will automatically be dumped.
598 Note - older versions of @code{GAS} would dump the current literal
599 pool any time a section change occurred. This is no longer done, since
600 it prevents accurate control of the placement of literal pools.
602 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
604 @cindex @code{.movsp} directive, ARM
605 @item .movsp @var{reg} [, #@var{offset}]
606 Tell the unwinder that @var{reg} contains an offset from the current
607 stack pointer. If @var{offset} is not specified then it is assumed to be
610 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
611 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
613 @cindex @code{.object_arch} directive, ARM
614 @item .object_arch @var{name}
615 Override the architecture recorded in the EABI object attribute section.
616 Valid values for @var{name} are the same as for the @code{.arch} directive.
617 Typically this is useful when code uses runtime detection of CPU features.
619 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
621 @cindex @code{.packed} directive, ARM
622 @item .packed @var{expression} [, @var{expression}]*
623 This directive writes 12-byte packed floating-point values to the
624 output section. These are not compatible with current ARM processors
627 @cindex @code{.pad} directive, ARM
628 @item .pad #@var{count}
629 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
630 A positive value indicates the function prologue allocated stack space by
631 decrementing the stack pointer.
633 @cindex @code{.personality} directive, ARM
634 @item .personality @var{name}
635 Sets the personality routine for the current function to @var{name}.
637 @cindex @code{.personalityindex} directive, ARM
638 @item .personalityindex @var{index}
639 Sets the personality routine for the current function to the EABI standard
640 routine number @var{index}
642 @cindex @code{.pool} directive, ARM
644 This is a synonym for .ltorg.
646 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
647 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
649 @cindex @code{.req} directive, ARM
650 @item @var{name} .req @var{register name}
651 This creates an alias for @var{register name} called @var{name}. For
658 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
661 @cindex @code{.save} directive, ARM
662 @item .save @var{reglist}
663 Generate unwinder annotations to restore the registers in @var{reglist}.
664 The format of @var{reglist} is the same as the corresponding store-multiple
668 @exdent @emph{core registers}
669 .save @{r4, r5, r6, lr@}
670 stmfd sp!, @{r4, r5, r6, lr@}
671 @exdent @emph{FPA registers}
674 @exdent @emph{VFP registers}
675 .save @{d8, d9, d10@}
676 fstmdx sp!, @{d8, d9, d10@}
677 @exdent @emph{iWMMXt registers}
679 wstrd wr11, [sp, #-8]!
680 wstrd wr10, [sp, #-8]!
683 wstrd wr11, [sp, #-8]!
685 wstrd wr10, [sp, #-8]!
689 @cindex @code{.setfp} directive, ARM
690 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
691 Make all unwinder annotations relative to a frame pointer. Without this
692 the unwinder will use offsets from the stack pointer.
694 The syntax of this directive is the same as the @code{sub} or @code{mov}
695 instruction used to set the frame pointer. @var{spreg} must be either
696 @code{sp} or mentioned in a previous @code{.movsp} directive.
706 @cindex @code{.secrel32} directive, ARM
707 @item .secrel32 @var{expression} [, @var{expression}]*
708 This directive emits relocations that evaluate to the section-relative
709 offset of each expression's symbol. This directive is only supported
712 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
714 @cindex @code{.thumb} directive, ARM
716 This performs the same action as @var{.code 16}.
718 @cindex @code{.thumb_func} directive, ARM
720 This directive specifies that the following symbol is the name of a
721 Thumb encoded function. This information is necessary in order to allow
722 the assembler and linker to generate correct code for interworking
723 between Arm and Thumb instructions and should be used even if
724 interworking is not going to be performed. The presence of this
725 directive also implies @code{.thumb}
727 This directive is not neccessary when generating EABI objects. On these
728 targets the encoding is implicit when generating Thumb code.
730 @cindex @code{.thumb_set} directive, ARM
732 This performs the equivalent of a @code{.set} directive in that it
733 creates a symbol which is an alias for another symbol (possibly not yet
734 defined). This directive also has the added property in that it marks
735 the aliased symbol as being a thumb function entry point, in the same
736 way that the @code{.thumb_func} directive does.
738 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
740 @cindex @code{.unreq} directive, ARM
741 @item .unreq @var{alias-name}
742 This undefines a register alias which was previously defined using the
743 @code{req}, @code{dn} or @code{qn} directives. For example:
750 An error occurs if the name is undefined. Note - this pseudo op can
751 be used to delete builtin in register name aliases (eg 'r0'). This
752 should only be done if it is really necessary.
754 @cindex @code{.unwind_raw} directive, ARM
755 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
756 Insert one of more arbitary unwind opcode bytes, which are known to adjust
757 the stack pointer by @var{offset} bytes.
759 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
762 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
764 @cindex @code{.vsave} directive, ARM
765 @item .vsave @var{vfp-reglist}
766 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
767 using FLDMD. Also works for VFPv3 registers
768 that are to be restored using VLDM.
769 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
773 @exdent @emph{VFP registers}
774 .vsave @{d8, d9, d10@}
775 fstmdd sp!, @{d8, d9, d10@}
776 @exdent @emph{VFPv3 registers}
777 .vsave @{d15, d16, d17@}
778 vstm sp!, @{d15, d16, d17@}
781 Since FLDMX and FSTMX are now deprecated, this directive should be
782 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
784 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
785 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
786 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
787 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
795 @cindex opcodes for ARM
796 @code{@value{AS}} implements all the standard ARM opcodes. It also
797 implements several pseudo opcodes, including several synthetic load
802 @cindex @code{NOP} pseudo op, ARM
808 This pseudo op will always evaluate to a legal ARM instruction that does
809 nothing. Currently it will evaluate to MOV r0, r0.
811 @cindex @code{LDR reg,=<label>} pseudo op, ARM
814 ldr <register> , = <expression>
817 If expression evaluates to a numeric constant then a MOV or MVN
818 instruction will be used in place of the LDR instruction, if the
819 constant can be generated by either of these instructions. Otherwise
820 the constant will be placed into the nearest literal pool (if it not
821 already there) and a PC relative LDR instruction will be generated.
823 @cindex @code{ADR reg,<label>} pseudo op, ARM
826 adr <register> <label>
829 This instruction will load the address of @var{label} into the indicated
830 register. The instruction will evaluate to a PC relative ADD or SUB
831 instruction depending upon where the label is located. If the label is
832 out of range, or if it is not defined in the same file (and section) as
833 the ADR instruction, then an error will be generated. This instruction
834 will not make use of the literal pool.
836 @cindex @code{ADRL reg,<label>} pseudo op, ARM
839 adrl <register> <label>
842 This instruction will load the address of @var{label} into the indicated
843 register. The instruction will evaluate to one or two PC relative ADD
844 or SUB instructions depending upon where the label is located. If a
845 second instruction is not needed a NOP instruction will be generated in
846 its place, so that this instruction is always 8 bytes long.
848 If the label is out of range, or if it is not defined in the same file
849 (and section) as the ADRL instruction, then an error will be generated.
850 This instruction will not make use of the literal pool.
854 For information on the ARM or Thumb instruction sets, see @cite{ARM
855 Software Development Toolkit Reference Manual}, Advanced RISC Machines
858 @node ARM Mapping Symbols
859 @section Mapping Symbols
861 The ARM ELF specification requires that special symbols be inserted
862 into object files to mark certain features:
868 At the start of a region of code containing ARM instructions.
872 At the start of a region of code containing THUMB instructions.
876 At the start of a region of data.
880 The assembler will automatically insert these symbols for you - there
881 is no need to code them yourself. Support for tagging symbols ($b,
882 $f, $p and $m) which is also mentioned in the current ARM ELF
883 specification is not implemented. This is because they have been
884 dropped from the new EABI and so tools cannot rely upon their
887 @node ARM Unwinding Tutorial
890 The ABI for the ARM Architecture specifies a standard format for
891 exception unwind information. This information is used when an
892 exception is thrown to determine where control should be transferred.
893 In particular, the unwind information is used to determine which
894 function called the function that threw the exception, and which
895 function called that one, and so forth. This information is also used
896 to restore the values of callee-saved registers in the function
897 catching the exception.
899 If you are writing functions in assembly code, and those functions
900 call other functions that throw exceptions, you must use assembly
901 pseudo ops to ensure that appropriate exception unwind information is
902 generated. Otherwise, if one of the functions called by your assembly
903 code throws an exception, the run-time library will be unable to
904 unwind the stack through your assembly code and your program will not
907 To illustrate the use of these pseudo ops, we will examine the code
908 that G++ generates for the following C++ input:
922 This example does not show how to throw or catch an exception from
923 assembly code. That is a much more complex operation and should
924 always be done in a high-level language, such as C++, that directly
927 The code generated by one particular version of G++ when compiling the
934 @ Function supports interworking.
935 @ args = 0, pretend = 0, frame = 8
936 @ frame_needed = 1, uses_anonymous_args = 0
958 Of course, the sequence of instructions varies based on the options
959 you pass to GCC and on the version of GCC in use. The exact
960 instructions are not important since we are focusing on the pseudo ops
961 that are used to generate unwind information.
963 An important assumption made by the unwinder is that the stack frame
964 does not change during the body of the function. In particular, since
965 we assume that the assembly code does not itself throw an exception,
966 the only point where an exception can be thrown is from a call, such
967 as the @code{bl} instruction above. At each call site, the same saved
968 registers (including @code{lr}, which indicates the return address)
969 must be located in the same locations relative to the frame pointer.
971 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
972 op appears immediately before the first instruction of the function
973 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
974 op appears immediately after the last instruction of the function.
975 These pseudo ops specify the range of the function.
977 Only the order of the other pseudos ops (e.g., @code{.setfp} or
978 @code{.pad}) matters; their exact locations are irrelevant. In the
979 example above, the compiler emits the pseudo ops with particular
980 instructions. That makes it easier to understand the code, but it is
981 not required for correctness. It would work just as well to emit all
982 of the pseudo ops other than @code{.fnend} in the same order, but
983 immediately after @code{.fnstart}.
985 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
986 indicates registers that have been saved to the stack so that they can
987 be restored before the function returns. The argument to the
988 @code{.save} pseudo op is a list of registers to save. If a register
989 is ``callee-saved'' (as specified by the ABI) and is modified by the
990 function you are writing, then your code must save the value before it
991 is modified and restore the original value before the function
992 returns. If an exception is thrown, the run-time library restores the
993 values of these registers from their locations on the stack before
994 returning control to the exception handler. (Of course, if an
995 exception is not thrown, the function that contains the @code{.save}
996 pseudo op restores these registers in the function epilogue, as is
997 done with the @code{ldmfd} instruction above.)
999 You do not have to save callee-saved registers at the very beginning
1000 of the function and you do not need to use the @code{.save} pseudo op
1001 immediately following the point at which the registers are saved.
1002 However, if you modify a callee-saved register, you must save it on
1003 the stack before modifying it and before calling any functions which
1004 might throw an exception. And, you must use the @code{.save} pseudo
1005 op to indicate that you have done so.
1007 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1008 modification of the stack pointer that does not save any registers.
1009 The argument is the number of bytes (in decimal) that are subtracted
1010 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1011 subtracting from the stack pointer increases the size of the stack.)
1013 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1014 indicates the register that contains the frame pointer. The first
1015 argument is the register that is set, which is typically @code{fp}.
1016 The second argument indicates the register from which the frame
1017 pointer takes its value. The third argument, if present, is the value
1018 (in decimal) added to the register specified by the second argument to
1019 compute the value of the frame pointer. You should not modify the
1020 frame pointer in the body of the function.
1022 If you do not use a frame pointer, then you should not use the
1023 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1024 should avoid modifying the stack pointer outside of the function
1025 prologue. Otherwise, the run-time library will be unable to find
1026 saved registers when it is unwinding the stack.
1028 The pseudo ops described above are sufficient for writing assembly
1029 code that calls functions which may throw exceptions. If you need to
1030 know more about the object-file format used to represent unwind
1031 information, you may consult the @cite{Exception Handling ABI for the
1032 ARM Architecture} available from @uref{http://infocenter.arm.com}.