1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa606te} (Faraday FA606TE processor),
106 @code{fa616te} (Faraday FA616TE processor),
107 @code{fa626te} (Faraday FA626TE processor),
108 @code{fmp626} (Faraday FMP626 processor),
109 @code{fa726te} (Faraday FA726TE processor),
129 @code{cortex-m0plus},
130 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
131 @code{i80200} (Intel XScale processor)
132 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
135 The special name @code{all} may be used to allow the
136 assembler to accept instructions valid for any ARM processor.
138 In addition to the basic instruction set, the assembler can be told to
139 accept various extension mnemonics that extend the processor using the
140 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
141 is equivalent to specifying @code{-mcpu=ep9312}.
143 Multiple extensions may be specified, separated by a @code{+}. The
144 extensions should be specified in ascending alphabetical order.
146 Some extensions may be restricted to particular architectures; this is
147 documented in the list of extensions below.
149 Extension mnemonics may also be removed from those the assembler accepts.
150 This is done be prepending @code{no} to the option that adds the extension.
151 Extensions that are removed should be listed after all extensions which have
152 been added, again in ascending alphabetical order. For example,
153 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
156 The following extensions are currently supported:
157 @code{idiv}, (Integer Divide Extensions for v7-A and v7-R architectures),
161 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
162 @code{os} (Operating System for v6M architecture),
163 @code{sec} (Security Extensions for v6K and v7-A architectures),
164 @code{virt} (Virtualization Extensions for v7-A architecture, implies
169 @cindex @code{-march=} command line option, ARM
170 @item -march=@var{architecture}[+@var{extension}@dots{}]
171 This option specifies the target architecture. The assembler will issue
172 an error message if an attempt is made to assemble an instruction which
173 will not execute on the target architecture. The following architecture
174 names are recognized:
205 If both @code{-mcpu} and
206 @code{-march} are specified, the assembler will use
207 the setting for @code{-mcpu}.
209 The architecture option can be extended with the same instruction set
210 extension options as the @code{-mcpu} option.
212 @cindex @code{-mfpu=} command line option, ARM
213 @item -mfpu=@var{floating-point-format}
215 This option specifies the floating point format to assemble for. The
216 assembler will issue an error message if an attempt is made to assemble
217 an instruction which will not execute on the target floating point unit.
218 The following format options are recognized:
238 @code{vfpv3-d16-fp16},
252 In addition to determining which instructions are assembled, this option
253 also affects the way in which the @code{.double} assembler directive behaves
254 when assembling little-endian code.
256 The default is dependent on the processor selected. For Architecture 5 or
257 later, the default is to assembler for VFP instructions; for earlier
258 architectures the default is to assemble for FPA instructions.
260 @cindex @code{-mthumb} command line option, ARM
262 This option specifies that the assembler should start assembling Thumb
263 instructions; that is, it should behave as though the file starts with a
264 @code{.code 16} directive.
266 @cindex @code{-mthumb-interwork} command line option, ARM
267 @item -mthumb-interwork
268 This option specifies that the output generated by the assembler should
269 be marked as supporting interworking.
271 @cindex @code{-mimplicit-it} command line option, ARM
272 @item -mimplicit-it=never
273 @itemx -mimplicit-it=always
274 @itemx -mimplicit-it=arm
275 @itemx -mimplicit-it=thumb
276 The @code{-mimplicit-it} option controls the behavior of the assembler when
277 conditional instructions are not enclosed in IT blocks.
278 There are four possible behaviors.
279 If @code{never} is specified, such constructs cause a warning in ARM
280 code and an error in Thumb-2 code.
281 If @code{always} is specified, such constructs are accepted in both
282 ARM and Thumb-2 code, where the IT instruction is added implicitly.
283 If @code{arm} is specified, such constructs are accepted in ARM code
284 and cause an error in Thumb-2 code.
285 If @code{thumb} is specified, such constructs cause a warning in ARM
286 code and are accepted in Thumb-2 code. If you omit this option, the
287 behavior is equivalent to @code{-mimplicit-it=arm}.
289 @cindex @code{-mapcs-26} command line option, ARM
290 @cindex @code{-mapcs-32} command line option, ARM
293 These options specify that the output generated by the assembler should
294 be marked as supporting the indicated version of the Arm Procedure.
297 @cindex @code{-matpcs} command line option, ARM
299 This option specifies that the output generated by the assembler should
300 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
301 enabled this option will cause the assembler to create an empty
302 debugging section in the object file called .arm.atpcs. Debuggers can
303 use this to determine the ABI being used by.
305 @cindex @code{-mapcs-float} command line option, ARM
307 This indicates the floating point variant of the APCS should be
308 used. In this variant floating point arguments are passed in FP
309 registers rather than integer registers.
311 @cindex @code{-mapcs-reentrant} command line option, ARM
312 @item -mapcs-reentrant
313 This indicates that the reentrant variant of the APCS should be used.
314 This variant supports position independent code.
316 @cindex @code{-mfloat-abi=} command line option, ARM
317 @item -mfloat-abi=@var{abi}
318 This option specifies that the output generated by the assembler should be
319 marked as using specified floating point ABI.
320 The following values are recognized:
326 @cindex @code{-eabi=} command line option, ARM
327 @item -meabi=@var{ver}
328 This option specifies which EABI version the produced object files should
330 The following values are recognized:
336 @cindex @code{-EB} command line option, ARM
338 This option specifies that the output generated by the assembler should
339 be marked as being encoded for a big-endian processor.
341 @cindex @code{-EL} command line option, ARM
343 This option specifies that the output generated by the assembler should
344 be marked as being encoded for a little-endian processor.
346 @cindex @code{-k} command line option, ARM
347 @cindex PIC code generation for ARM
349 This option specifies that the output of the assembler should be marked
350 as position-independent code (PIC).
352 @cindex @code{--fix-v4bx} command line option, ARM
354 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
355 the linker option of the same name.
357 @cindex @code{-mwarn-deprecated} command line option, ARM
358 @item -mwarn-deprecated
359 @itemx -mno-warn-deprecated
360 Enable or disable warnings about using deprecated options or
361 features. The default is to warn.
369 * ARM-Instruction-Set:: Instruction Set
370 * ARM-Chars:: Special Characters
371 * ARM-Regs:: Register Names
372 * ARM-Relocations:: Relocations
373 * ARM-Neon-Alignment:: NEON Alignment Specifiers
376 @node ARM-Instruction-Set
377 @subsection Instruction Set Syntax
378 Two slightly different syntaxes are support for ARM and THUMB
379 instructions. The default, @code{divided}, uses the old style where
380 ARM and THUMB instructions had their own, separate syntaxes. The new,
381 @code{unified} syntax, which can be selected via the @code{.syntax}
382 directive, and has the following main features:
386 Immediate operands do not require a @code{#} prefix.
389 The @code{IT} instruction may appear, and if it does it is validated
390 against subsequent conditional affixes. In ARM mode it does not
391 generate machine code, in THUMB mode it does.
394 For ARM instructions the conditional affixes always appear at the end
395 of the instruction. For THUMB instructions conditional affixes can be
396 used, but only inside the scope of an @code{IT} instruction.
399 All of the instructions new to the V6T2 architecture (and later) are
400 available. (Only a few such instructions can be written in the
401 @code{divided} syntax).
404 The @code{.N} and @code{.W} suffixes are recognized and honored.
407 All instructions set the flags if and only if they have an @code{s}
412 @subsection Special Characters
414 @cindex line comment character, ARM
415 @cindex ARM line comment character
416 The presence of a @samp{@@} anywhere on a line indicates the start of
417 a comment that extends to the end of that line.
419 If a @samp{#} appears as the first character of a line then the whole
420 line is treated as a comment, but in this case the line could also be
421 a logical line number directive (@pxref{Comments}) or a preprocessor
422 control command (@pxref{Preprocessing}).
424 @cindex line separator, ARM
425 @cindex statement separator, ARM
426 @cindex ARM line separator
427 The @samp{;} character can be used instead of a newline to separate
430 @cindex immediate character, ARM
431 @cindex ARM immediate character
432 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
434 @cindex identifiers, ARM
435 @cindex ARM identifiers
436 *TODO* Explain about /data modifier on symbols.
439 @subsection Register Names
441 @cindex ARM register names
442 @cindex register names, ARM
443 *TODO* Explain about ARM register naming, and the predefined names.
445 @node ARM-Neon-Alignment
446 @subsection NEON Alignment Specifiers
448 @cindex alignment for NEON instructions
449 Some NEON load/store instructions allow an optional address
451 The ARM documentation specifies that this is indicated by
452 @samp{@@ @var{align}}. However GAS already interprets
453 the @samp{@@} character as a "line comment" start,
454 so @samp{: @var{align}} is used instead. For example:
457 vld1.8 @{q0@}, [r0, :128]
460 @node ARM Floating Point
461 @section Floating Point
463 @cindex floating point, ARM (@sc{ieee})
464 @cindex ARM floating point (@sc{ieee})
465 The ARM family uses @sc{ieee} floating-point numbers.
467 @node ARM-Relocations
468 @subsection ARM relocation generation
470 @cindex data relocations, ARM
471 @cindex ARM data relocations
472 Specific data relocations can be generated by putting the relocation name
473 in parentheses after the symbol name. For example:
479 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
481 The following relocations are supported:
497 For compatibility with older toolchains the assembler also accepts
498 @code{(PLT)} after branch targets. On legacy targets this will
499 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
500 targets it will encode either the @samp{R_ARM_CALL} or
501 @samp{R_ARM_JUMP24} relocation, as appropriate.
503 @cindex MOVW and MOVT relocations, ARM
504 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
505 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
506 respectively. For example to load the 32-bit address of foo into r0:
509 MOVW r0, #:lower16:foo
510 MOVT r0, #:upper16:foo
514 @section ARM Machine Directives
516 @cindex machine directives, ARM
517 @cindex ARM machine directives
520 @c AAAAAAAAAAAAAAAAAAAAAAAAA
522 @cindex @code{.2byte} directive, ARM
523 @cindex @code{.4byte} directive, ARM
524 @cindex @code{.8byte} directive, ARM
525 @item .2byte @var{expression} [, @var{expression}]*
526 @itemx .4byte @var{expression} [, @var{expression}]*
527 @itemx .8byte @var{expression} [, @var{expression}]*
528 These directives write 2, 4 or 8 byte values to the output section.
530 @cindex @code{.align} directive, ARM
531 @item .align @var{expression} [, @var{expression}]
532 This is the generic @var{.align} directive. For the ARM however if the
533 first argument is zero (ie no alignment is needed) the assembler will
534 behave as if the argument had been 2 (ie pad to the next four byte
535 boundary). This is for compatibility with ARM's own assembler.
537 @cindex @code{.arch} directive, ARM
538 @item .arch @var{name}
539 Select the target architecture. Valid values for @var{name} are the same as
540 for the @option{-march} commandline option.
542 Specifying @code{.arch} clears any previously selected architecture
545 @cindex @code{.arch_extension} directive, ARM
546 @item .arch_extension @var{name}
547 Add or remove an architecture extension to the target architecture. Valid
548 values for @var{name} are the same as those accepted as architectural
549 extensions by the @option{-mcpu} commandline option.
551 @code{.arch_extension} may be used multiple times to add or remove extensions
552 incrementally to the architecture being compiled for.
554 @cindex @code{.arm} directive, ARM
556 This performs the same action as @var{.code 32}.
559 @cindex @code{.pad} directive, ARM
560 @item .pad #@var{count}
561 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
562 A positive value indicates the function prologue allocated stack space by
563 decrementing the stack pointer.
565 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
567 @cindex @code{.bss} directive, ARM
569 This directive switches to the @code{.bss} section.
571 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
573 @cindex @code{.cantunwind} directive, ARM
575 Prevents unwinding through the current function. No personality routine
576 or exception table data is required or permitted.
578 @cindex @code{.code} directive, ARM
579 @item .code @code{[16|32]}
580 This directive selects the instruction set being generated. The value 16
581 selects Thumb, with the value 32 selecting ARM.
583 @cindex @code{.cpu} directive, ARM
584 @item .cpu @var{name}
585 Select the target processor. Valid values for @var{name} are the same as
586 for the @option{-mcpu} commandline option.
588 Specifying @code{.cpu} clears any previously selected architecture
591 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
593 @cindex @code{.dn} and @code{.qn} directives, ARM
594 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
595 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
597 The @code{dn} and @code{qn} directives are used to create typed
598 and/or indexed register aliases for use in Advanced SIMD Extension
599 (Neon) instructions. The former should be used to create aliases
600 of double-precision registers, and the latter to create aliases of
601 quad-precision registers.
603 If these directives are used to create typed aliases, those aliases can
604 be used in Neon instructions instead of writing types after the mnemonic
605 or after each operand. For example:
614 This is equivalent to writing the following:
620 Aliases created using @code{dn} or @code{qn} can be destroyed using
623 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
625 @cindex @code{.eabi_attribute} directive, ARM
626 @item .eabi_attribute @var{tag}, @var{value}
627 Set the EABI object attribute @var{tag} to @var{value}.
629 The @var{tag} is either an attribute number, or one of the following:
630 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
631 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
632 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
633 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
634 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
635 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
636 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
637 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
638 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
639 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
640 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
641 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
642 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
643 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
644 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
645 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
646 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
647 @code{Tag_conformance}, @code{Tag_T2EE_use},
648 @code{Tag_Virtualization_use}
650 The @var{value} is either a @code{number}, @code{"string"}, or
651 @code{number, "string"} depending on the tag.
653 Note - the following legacy values are also accepted by @var{tag}:
654 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
655 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
657 @cindex @code{.even} directive, ARM
659 This directive aligns to an even-numbered address.
661 @cindex @code{.extend} directive, ARM
662 @cindex @code{.ldouble} directive, ARM
663 @item .extend @var{expression} [, @var{expression}]*
664 @itemx .ldouble @var{expression} [, @var{expression}]*
665 These directives write 12byte long double floating-point values to the
666 output section. These are not compatible with current ARM processors
669 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
672 @cindex @code{.fnend} directive, ARM
674 Marks the end of a function with an unwind table entry. The unwind index
675 table entry is created when this directive is processed.
677 If no personality routine has been specified then standard personality
678 routine 0 or 1 will be used, depending on the number of unwind opcodes
682 @cindex @code{.fnstart} directive, ARM
684 Marks the start of a function with an unwind table entry.
686 @cindex @code{.force_thumb} directive, ARM
688 This directive forces the selection of Thumb instructions, even if the
689 target processor does not support those instructions
691 @cindex @code{.fpu} directive, ARM
692 @item .fpu @var{name}
693 Select the floating-point unit to assemble for. Valid values for @var{name}
694 are the same as for the @option{-mfpu} commandline option.
696 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
697 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
699 @cindex @code{.handlerdata} directive, ARM
701 Marks the end of the current function, and the start of the exception table
702 entry for that function. Anything between this directive and the
703 @code{.fnend} directive will be added to the exception table entry.
705 Must be preceded by a @code{.personality} or @code{.personalityindex}
708 @c IIIIIIIIIIIIIIIIIIIIIIIIII
710 @cindex @code{.inst} directive, ARM
711 @item .inst @var{opcode} [ , @dots{} ]
712 @itemx .inst.n @var{opcode} [ , @dots{} ]
713 @itemx .inst.w @var{opcode} [ , @dots{} ]
714 Generates the instruction corresponding to the numerical value @var{opcode}.
715 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
716 specified explicitly, overriding the normal encoding rules.
718 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
719 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
720 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
722 @item .ldouble @var{expression} [, @var{expression}]*
725 @cindex @code{.ltorg} directive, ARM
727 This directive causes the current contents of the literal pool to be
728 dumped into the current section (which is assumed to be the .text
729 section) at the current location (aligned to a word boundary).
730 @code{GAS} maintains a separate literal pool for each section and each
731 sub-section. The @code{.ltorg} directive will only affect the literal
732 pool of the current section and sub-section. At the end of assembly
733 all remaining, un-empty literal pools will automatically be dumped.
735 Note - older versions of @code{GAS} would dump the current literal
736 pool any time a section change occurred. This is no longer done, since
737 it prevents accurate control of the placement of literal pools.
739 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
741 @cindex @code{.movsp} directive, ARM
742 @item .movsp @var{reg} [, #@var{offset}]
743 Tell the unwinder that @var{reg} contains an offset from the current
744 stack pointer. If @var{offset} is not specified then it is assumed to be
747 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
748 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
750 @cindex @code{.object_arch} directive, ARM
751 @item .object_arch @var{name}
752 Override the architecture recorded in the EABI object attribute section.
753 Valid values for @var{name} are the same as for the @code{.arch} directive.
754 Typically this is useful when code uses runtime detection of CPU features.
756 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
758 @cindex @code{.packed} directive, ARM
759 @item .packed @var{expression} [, @var{expression}]*
760 This directive writes 12-byte packed floating-point values to the
761 output section. These are not compatible with current ARM processors
764 @cindex @code{.pad} directive, ARM
765 @item .pad #@var{count}
766 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
767 A positive value indicates the function prologue allocated stack space by
768 decrementing the stack pointer.
770 @cindex @code{.personality} directive, ARM
771 @item .personality @var{name}
772 Sets the personality routine for the current function to @var{name}.
774 @cindex @code{.personalityindex} directive, ARM
775 @item .personalityindex @var{index}
776 Sets the personality routine for the current function to the EABI standard
777 routine number @var{index}
779 @cindex @code{.pool} directive, ARM
781 This is a synonym for .ltorg.
783 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
784 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
786 @cindex @code{.req} directive, ARM
787 @item @var{name} .req @var{register name}
788 This creates an alias for @var{register name} called @var{name}. For
795 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
798 @cindex @code{.save} directive, ARM
799 @item .save @var{reglist}
800 Generate unwinder annotations to restore the registers in @var{reglist}.
801 The format of @var{reglist} is the same as the corresponding store-multiple
805 @exdent @emph{core registers}
806 .save @{r4, r5, r6, lr@}
807 stmfd sp!, @{r4, r5, r6, lr@}
808 @exdent @emph{FPA registers}
811 @exdent @emph{VFP registers}
812 .save @{d8, d9, d10@}
813 fstmdx sp!, @{d8, d9, d10@}
814 @exdent @emph{iWMMXt registers}
816 wstrd wr11, [sp, #-8]!
817 wstrd wr10, [sp, #-8]!
820 wstrd wr11, [sp, #-8]!
822 wstrd wr10, [sp, #-8]!
826 @cindex @code{.setfp} directive, ARM
827 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
828 Make all unwinder annotations relative to a frame pointer. Without this
829 the unwinder will use offsets from the stack pointer.
831 The syntax of this directive is the same as the @code{add} or @code{mov}
832 instruction used to set the frame pointer. @var{spreg} must be either
833 @code{sp} or mentioned in a previous @code{.movsp} directive.
843 @cindex @code{.secrel32} directive, ARM
844 @item .secrel32 @var{expression} [, @var{expression}]*
845 This directive emits relocations that evaluate to the section-relative
846 offset of each expression's symbol. This directive is only supported
849 @cindex @code{.syntax} directive, ARM
850 @item .syntax [@code{unified} | @code{divided}]
851 This directive sets the Instruction Set Syntax as described in the
852 @ref{ARM-Instruction-Set} section.
854 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
856 @cindex @code{.thumb} directive, ARM
858 This performs the same action as @var{.code 16}.
860 @cindex @code{.thumb_func} directive, ARM
862 This directive specifies that the following symbol is the name of a
863 Thumb encoded function. This information is necessary in order to allow
864 the assembler and linker to generate correct code for interworking
865 between Arm and Thumb instructions and should be used even if
866 interworking is not going to be performed. The presence of this
867 directive also implies @code{.thumb}
869 This directive is not neccessary when generating EABI objects. On these
870 targets the encoding is implicit when generating Thumb code.
872 @cindex @code{.thumb_set} directive, ARM
874 This performs the equivalent of a @code{.set} directive in that it
875 creates a symbol which is an alias for another symbol (possibly not yet
876 defined). This directive also has the added property in that it marks
877 the aliased symbol as being a thumb function entry point, in the same
878 way that the @code{.thumb_func} directive does.
880 @cindex @code{.tlsdescseq} directive, ARM
881 @item .tlsdescseq @var{tls-variable}
882 This directive is used to annotate parts of an inlined TLS descriptor
883 trampoline. Normally the trampoline is provided by the linker, and
884 this directive is not needed.
886 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
888 @cindex @code{.unreq} directive, ARM
889 @item .unreq @var{alias-name}
890 This undefines a register alias which was previously defined using the
891 @code{req}, @code{dn} or @code{qn} directives. For example:
898 An error occurs if the name is undefined. Note - this pseudo op can
899 be used to delete builtin in register name aliases (eg 'r0'). This
900 should only be done if it is really necessary.
902 @cindex @code{.unwind_raw} directive, ARM
903 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
904 Insert one of more arbitary unwind opcode bytes, which are known to adjust
905 the stack pointer by @var{offset} bytes.
907 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
910 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
912 @cindex @code{.vsave} directive, ARM
913 @item .vsave @var{vfp-reglist}
914 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
915 using FLDMD. Also works for VFPv3 registers
916 that are to be restored using VLDM.
917 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
921 @exdent @emph{VFP registers}
922 .vsave @{d8, d9, d10@}
923 fstmdd sp!, @{d8, d9, d10@}
924 @exdent @emph{VFPv3 registers}
925 .vsave @{d15, d16, d17@}
926 vstm sp!, @{d15, d16, d17@}
929 Since FLDMX and FSTMX are now deprecated, this directive should be
930 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
932 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
933 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
934 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
935 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
943 @cindex opcodes for ARM
944 @code{@value{AS}} implements all the standard ARM opcodes. It also
945 implements several pseudo opcodes, including several synthetic load
950 @cindex @code{NOP} pseudo op, ARM
956 This pseudo op will always evaluate to a legal ARM instruction that does
957 nothing. Currently it will evaluate to MOV r0, r0.
959 @cindex @code{LDR reg,=<label>} pseudo op, ARM
962 ldr <register> , = <expression>
965 If expression evaluates to a numeric constant then a MOV or MVN
966 instruction will be used in place of the LDR instruction, if the
967 constant can be generated by either of these instructions. Otherwise
968 the constant will be placed into the nearest literal pool (if it not
969 already there) and a PC relative LDR instruction will be generated.
971 @cindex @code{ADR reg,<label>} pseudo op, ARM
974 adr <register> <label>
977 This instruction will load the address of @var{label} into the indicated
978 register. The instruction will evaluate to a PC relative ADD or SUB
979 instruction depending upon where the label is located. If the label is
980 out of range, or if it is not defined in the same file (and section) as
981 the ADR instruction, then an error will be generated. This instruction
982 will not make use of the literal pool.
984 @cindex @code{ADRL reg,<label>} pseudo op, ARM
987 adrl <register> <label>
990 This instruction will load the address of @var{label} into the indicated
991 register. The instruction will evaluate to one or two PC relative ADD
992 or SUB instructions depending upon where the label is located. If a
993 second instruction is not needed a NOP instruction will be generated in
994 its place, so that this instruction is always 8 bytes long.
996 If the label is out of range, or if it is not defined in the same file
997 (and section) as the ADRL instruction, then an error will be generated.
998 This instruction will not make use of the literal pool.
1002 For information on the ARM or Thumb instruction sets, see @cite{ARM
1003 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1006 @node ARM Mapping Symbols
1007 @section Mapping Symbols
1009 The ARM ELF specification requires that special symbols be inserted
1010 into object files to mark certain features:
1016 At the start of a region of code containing ARM instructions.
1020 At the start of a region of code containing THUMB instructions.
1024 At the start of a region of data.
1028 The assembler will automatically insert these symbols for you - there
1029 is no need to code them yourself. Support for tagging symbols ($b,
1030 $f, $p and $m) which is also mentioned in the current ARM ELF
1031 specification is not implemented. This is because they have been
1032 dropped from the new EABI and so tools cannot rely upon their
1035 @node ARM Unwinding Tutorial
1038 The ABI for the ARM Architecture specifies a standard format for
1039 exception unwind information. This information is used when an
1040 exception is thrown to determine where control should be transferred.
1041 In particular, the unwind information is used to determine which
1042 function called the function that threw the exception, and which
1043 function called that one, and so forth. This information is also used
1044 to restore the values of callee-saved registers in the function
1045 catching the exception.
1047 If you are writing functions in assembly code, and those functions
1048 call other functions that throw exceptions, you must use assembly
1049 pseudo ops to ensure that appropriate exception unwind information is
1050 generated. Otherwise, if one of the functions called by your assembly
1051 code throws an exception, the run-time library will be unable to
1052 unwind the stack through your assembly code and your program will not
1055 To illustrate the use of these pseudo ops, we will examine the code
1056 that G++ generates for the following C++ input:
1059 void callee (int *);
1070 This example does not show how to throw or catch an exception from
1071 assembly code. That is a much more complex operation and should
1072 always be done in a high-level language, such as C++, that directly
1073 supports exceptions.
1075 The code generated by one particular version of G++ when compiling the
1082 @ Function supports interworking.
1083 @ args = 0, pretend = 0, frame = 8
1084 @ frame_needed = 1, uses_anonymous_args = 0
1106 Of course, the sequence of instructions varies based on the options
1107 you pass to GCC and on the version of GCC in use. The exact
1108 instructions are not important since we are focusing on the pseudo ops
1109 that are used to generate unwind information.
1111 An important assumption made by the unwinder is that the stack frame
1112 does not change during the body of the function. In particular, since
1113 we assume that the assembly code does not itself throw an exception,
1114 the only point where an exception can be thrown is from a call, such
1115 as the @code{bl} instruction above. At each call site, the same saved
1116 registers (including @code{lr}, which indicates the return address)
1117 must be located in the same locations relative to the frame pointer.
1119 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1120 op appears immediately before the first instruction of the function
1121 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1122 op appears immediately after the last instruction of the function.
1123 These pseudo ops specify the range of the function.
1125 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1126 @code{.pad}) matters; their exact locations are irrelevant. In the
1127 example above, the compiler emits the pseudo ops with particular
1128 instructions. That makes it easier to understand the code, but it is
1129 not required for correctness. It would work just as well to emit all
1130 of the pseudo ops other than @code{.fnend} in the same order, but
1131 immediately after @code{.fnstart}.
1133 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1134 indicates registers that have been saved to the stack so that they can
1135 be restored before the function returns. The argument to the
1136 @code{.save} pseudo op is a list of registers to save. If a register
1137 is ``callee-saved'' (as specified by the ABI) and is modified by the
1138 function you are writing, then your code must save the value before it
1139 is modified and restore the original value before the function
1140 returns. If an exception is thrown, the run-time library restores the
1141 values of these registers from their locations on the stack before
1142 returning control to the exception handler. (Of course, if an
1143 exception is not thrown, the function that contains the @code{.save}
1144 pseudo op restores these registers in the function epilogue, as is
1145 done with the @code{ldmfd} instruction above.)
1147 You do not have to save callee-saved registers at the very beginning
1148 of the function and you do not need to use the @code{.save} pseudo op
1149 immediately following the point at which the registers are saved.
1150 However, if you modify a callee-saved register, you must save it on
1151 the stack before modifying it and before calling any functions which
1152 might throw an exception. And, you must use the @code{.save} pseudo
1153 op to indicate that you have done so.
1155 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1156 modification of the stack pointer that does not save any registers.
1157 The argument is the number of bytes (in decimal) that are subtracted
1158 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1159 subtracting from the stack pointer increases the size of the stack.)
1161 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1162 indicates the register that contains the frame pointer. The first
1163 argument is the register that is set, which is typically @code{fp}.
1164 The second argument indicates the register from which the frame
1165 pointer takes its value. The third argument, if present, is the value
1166 (in decimal) added to the register specified by the second argument to
1167 compute the value of the frame pointer. You should not modify the
1168 frame pointer in the body of the function.
1170 If you do not use a frame pointer, then you should not use the
1171 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1172 should avoid modifying the stack pointer outside of the function
1173 prologue. Otherwise, the run-time library will be unable to find
1174 saved registers when it is unwinding the stack.
1176 The pseudo ops described above are sufficient for writing assembly
1177 code that calls functions which may throw exceptions. If you need to
1178 know more about the object-file format used to represent unwind
1179 information, you may consult the @cite{Exception Handling ABI for the
1180 ARM Architecture} available from @uref{http://infocenter.arm.com}.