1 @c Copyright (C) 1996-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
141 @code{cortex-m0plus},
144 @code{marvell-whitney},
147 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
148 @code{i80200} (Intel XScale processor)
149 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
152 The special name @code{all} may be used to allow the
153 assembler to accept instructions valid for any ARM processor.
155 In addition to the basic instruction set, the assembler can be told to
156 accept various extension mnemonics that extend the processor using the
157 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
158 is equivalent to specifying @code{-mcpu=ep9312}.
160 Multiple extensions may be specified, separated by a @code{+}. The
161 extensions should be specified in ascending alphabetical order.
163 Some extensions may be restricted to particular architectures; this is
164 documented in the list of extensions below.
166 Extension mnemonics may also be removed from those the assembler accepts.
167 This is done be prepending @code{no} to the option that adds the extension.
168 Extensions that are removed should be listed after all extensions which have
169 been added, again in ascending alphabetical order. For example,
170 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
173 The following extensions are currently supported:
175 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
176 @code{fp} (Floating Point Extensions for v8-A architecture),
177 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
182 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
184 @code{os} (Operating System for v6M architecture),
185 @code{sec} (Security Extensions for v6K and v7-A architectures),
186 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
187 @code{virt} (Virtualization Extensions for v7-A architecture, implies
189 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
190 @code{ras} (Reliability, Availability and Serviceability extensions
191 for v8-A architecture),
192 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
197 @cindex @code{-march=} command line option, ARM
198 @item -march=@var{architecture}[+@var{extension}@dots{}]
199 This option specifies the target architecture. The assembler will issue
200 an error message if an attempt is made to assemble an instruction which
201 will not execute on the target architecture. The following architecture
202 names are recognized:
240 If both @code{-mcpu} and
241 @code{-march} are specified, the assembler will use
242 the setting for @code{-mcpu}.
244 The architecture option can be extended with the same instruction set
245 extension options as the @code{-mcpu} option.
247 @cindex @code{-mfpu=} command line option, ARM
248 @item -mfpu=@var{floating-point-format}
250 This option specifies the floating point format to assemble for. The
251 assembler will issue an error message if an attempt is made to assemble
252 an instruction which will not execute on the target floating point unit.
253 The following format options are recognized:
273 @code{vfpv3-d16-fp16},
290 @code{neon-fp-armv8},
291 @code{crypto-neon-fp-armv8},
292 @code{neon-fp-armv8.1}
294 @code{crypto-neon-fp-armv8.1}.
296 In addition to determining which instructions are assembled, this option
297 also affects the way in which the @code{.double} assembler directive behaves
298 when assembling little-endian code.
300 The default is dependent on the processor selected. For Architecture 5 or
301 later, the default is to assemble for VFP instructions; for earlier
302 architectures the default is to assemble for FPA instructions.
304 @cindex @code{-mthumb} command line option, ARM
306 This option specifies that the assembler should start assembling Thumb
307 instructions; that is, it should behave as though the file starts with a
308 @code{.code 16} directive.
310 @cindex @code{-mthumb-interwork} command line option, ARM
311 @item -mthumb-interwork
312 This option specifies that the output generated by the assembler should
313 be marked as supporting interworking.
315 @cindex @code{-mimplicit-it} command line option, ARM
316 @item -mimplicit-it=never
317 @itemx -mimplicit-it=always
318 @itemx -mimplicit-it=arm
319 @itemx -mimplicit-it=thumb
320 The @code{-mimplicit-it} option controls the behavior of the assembler when
321 conditional instructions are not enclosed in IT blocks.
322 There are four possible behaviors.
323 If @code{never} is specified, such constructs cause a warning in ARM
324 code and an error in Thumb-2 code.
325 If @code{always} is specified, such constructs are accepted in both
326 ARM and Thumb-2 code, where the IT instruction is added implicitly.
327 If @code{arm} is specified, such constructs are accepted in ARM code
328 and cause an error in Thumb-2 code.
329 If @code{thumb} is specified, such constructs cause a warning in ARM
330 code and are accepted in Thumb-2 code. If you omit this option, the
331 behavior is equivalent to @code{-mimplicit-it=arm}.
333 @cindex @code{-mapcs-26} command line option, ARM
334 @cindex @code{-mapcs-32} command line option, ARM
337 These options specify that the output generated by the assembler should
338 be marked as supporting the indicated version of the Arm Procedure.
341 @cindex @code{-matpcs} command line option, ARM
343 This option specifies that the output generated by the assembler should
344 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
345 enabled this option will cause the assembler to create an empty
346 debugging section in the object file called .arm.atpcs. Debuggers can
347 use this to determine the ABI being used by.
349 @cindex @code{-mapcs-float} command line option, ARM
351 This indicates the floating point variant of the APCS should be
352 used. In this variant floating point arguments are passed in FP
353 registers rather than integer registers.
355 @cindex @code{-mapcs-reentrant} command line option, ARM
356 @item -mapcs-reentrant
357 This indicates that the reentrant variant of the APCS should be used.
358 This variant supports position independent code.
360 @cindex @code{-mfloat-abi=} command line option, ARM
361 @item -mfloat-abi=@var{abi}
362 This option specifies that the output generated by the assembler should be
363 marked as using specified floating point ABI.
364 The following values are recognized:
370 @cindex @code{-eabi=} command line option, ARM
371 @item -meabi=@var{ver}
372 This option specifies which EABI version the produced object files should
374 The following values are recognized:
380 @cindex @code{-EB} command line option, ARM
382 This option specifies that the output generated by the assembler should
383 be marked as being encoded for a big-endian processor.
385 Note: If a program is being built for a system with big-endian data
386 and little-endian instructions then it should be assembled with the
387 @option{-EB} option, (all of it, code and data) and then linked with
388 the @option{--be8} option. This will reverse the endianness of the
389 instructions back to little-endian, but leave the data as big-endian.
391 @cindex @code{-EL} command line option, ARM
393 This option specifies that the output generated by the assembler should
394 be marked as being encoded for a little-endian processor.
396 @cindex @code{-k} command line option, ARM
397 @cindex PIC code generation for ARM
399 This option specifies that the output of the assembler should be marked
400 as position-independent code (PIC).
402 @cindex @code{--fix-v4bx} command line option, ARM
404 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
405 the linker option of the same name.
407 @cindex @code{-mwarn-deprecated} command line option, ARM
408 @item -mwarn-deprecated
409 @itemx -mno-warn-deprecated
410 Enable or disable warnings about using deprecated options or
411 features. The default is to warn.
413 @cindex @code{-mccs} command line option, ARM
415 Turns on CodeComposer Studio assembly syntax compatibility mode.
417 @cindex @code{-mwarn-syms} command line option, ARM
419 @itemx -mno-warn-syms
420 Enable or disable warnings about symbols that match the names of ARM
421 instructions. The default is to warn.
429 * ARM-Instruction-Set:: Instruction Set
430 * ARM-Chars:: Special Characters
431 * ARM-Regs:: Register Names
432 * ARM-Relocations:: Relocations
433 * ARM-Neon-Alignment:: NEON Alignment Specifiers
436 @node ARM-Instruction-Set
437 @subsection Instruction Set Syntax
438 Two slightly different syntaxes are support for ARM and THUMB
439 instructions. The default, @code{divided}, uses the old style where
440 ARM and THUMB instructions had their own, separate syntaxes. The new,
441 @code{unified} syntax, which can be selected via the @code{.syntax}
442 directive, and has the following main features:
446 Immediate operands do not require a @code{#} prefix.
449 The @code{IT} instruction may appear, and if it does it is validated
450 against subsequent conditional affixes. In ARM mode it does not
451 generate machine code, in THUMB mode it does.
454 For ARM instructions the conditional affixes always appear at the end
455 of the instruction. For THUMB instructions conditional affixes can be
456 used, but only inside the scope of an @code{IT} instruction.
459 All of the instructions new to the V6T2 architecture (and later) are
460 available. (Only a few such instructions can be written in the
461 @code{divided} syntax).
464 The @code{.N} and @code{.W} suffixes are recognized and honored.
467 All instructions set the flags if and only if they have an @code{s}
472 @subsection Special Characters
474 @cindex line comment character, ARM
475 @cindex ARM line comment character
476 The presence of a @samp{@@} anywhere on a line indicates the start of
477 a comment that extends to the end of that line.
479 If a @samp{#} appears as the first character of a line then the whole
480 line is treated as a comment, but in this case the line could also be
481 a logical line number directive (@pxref{Comments}) or a preprocessor
482 control command (@pxref{Preprocessing}).
484 @cindex line separator, ARM
485 @cindex statement separator, ARM
486 @cindex ARM line separator
487 The @samp{;} character can be used instead of a newline to separate
490 @cindex immediate character, ARM
491 @cindex ARM immediate character
492 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
494 @cindex identifiers, ARM
495 @cindex ARM identifiers
496 *TODO* Explain about /data modifier on symbols.
499 @subsection Register Names
501 @cindex ARM register names
502 @cindex register names, ARM
503 *TODO* Explain about ARM register naming, and the predefined names.
505 @node ARM-Relocations
506 @subsection ARM relocation generation
508 @cindex data relocations, ARM
509 @cindex ARM data relocations
510 Specific data relocations can be generated by putting the relocation name
511 in parentheses after the symbol name. For example:
517 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
519 The following relocations are supported:
535 For compatibility with older toolchains the assembler also accepts
536 @code{(PLT)} after branch targets. On legacy targets this will
537 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
538 targets it will encode either the @samp{R_ARM_CALL} or
539 @samp{R_ARM_JUMP24} relocation, as appropriate.
541 @cindex MOVW and MOVT relocations, ARM
542 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
543 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
544 respectively. For example to load the 32-bit address of foo into r0:
547 MOVW r0, #:lower16:foo
548 MOVT r0, #:upper16:foo
551 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
552 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
553 generated by prefixing the value with @samp{#:lower0_7:#},
554 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
555 respectively. For example to load the 32-bit address of foo into r0:
558 MOVS r0, #:upper8_15:#foo
560 ADDS r0, #:upper0_7:#foo
562 ADDS r0, #:lower8_15:#foo
564 ADDS r0, #:lower0_7:#foo
567 @node ARM-Neon-Alignment
568 @subsection NEON Alignment Specifiers
570 @cindex alignment for NEON instructions
571 Some NEON load/store instructions allow an optional address
573 The ARM documentation specifies that this is indicated by
574 @samp{@@ @var{align}}. However GAS already interprets
575 the @samp{@@} character as a "line comment" start,
576 so @samp{: @var{align}} is used instead. For example:
579 vld1.8 @{q0@}, [r0, :128]
582 @node ARM Floating Point
583 @section Floating Point
585 @cindex floating point, ARM (@sc{ieee})
586 @cindex ARM floating point (@sc{ieee})
587 The ARM family uses @sc{ieee} floating-point numbers.
590 @section ARM Machine Directives
592 @cindex machine directives, ARM
593 @cindex ARM machine directives
596 @c AAAAAAAAAAAAAAAAAAAAAAAAA
599 @cindex @code{.2byte} directive, ARM
600 @cindex @code{.4byte} directive, ARM
601 @cindex @code{.8byte} directive, ARM
602 @item .2byte @var{expression} [, @var{expression}]*
603 @itemx .4byte @var{expression} [, @var{expression}]*
604 @itemx .8byte @var{expression} [, @var{expression}]*
605 These directives write 2, 4 or 8 byte values to the output section.
608 @cindex @code{.align} directive, ARM
609 @item .align @var{expression} [, @var{expression}]
610 This is the generic @var{.align} directive. For the ARM however if the
611 first argument is zero (ie no alignment is needed) the assembler will
612 behave as if the argument had been 2 (ie pad to the next four byte
613 boundary). This is for compatibility with ARM's own assembler.
615 @cindex @code{.arch} directive, ARM
616 @item .arch @var{name}
617 Select the target architecture. Valid values for @var{name} are the same as
618 for the @option{-march} commandline option.
620 Specifying @code{.arch} clears any previously selected architecture
623 @cindex @code{.arch_extension} directive, ARM
624 @item .arch_extension @var{name}
625 Add or remove an architecture extension to the target architecture. Valid
626 values for @var{name} are the same as those accepted as architectural
627 extensions by the @option{-mcpu} commandline option.
629 @code{.arch_extension} may be used multiple times to add or remove extensions
630 incrementally to the architecture being compiled for.
632 @cindex @code{.arm} directive, ARM
634 This performs the same action as @var{.code 32}.
636 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
638 @cindex @code{.bss} directive, ARM
640 This directive switches to the @code{.bss} section.
642 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
644 @cindex @code{.cantunwind} directive, ARM
646 Prevents unwinding through the current function. No personality routine
647 or exception table data is required or permitted.
649 @cindex @code{.code} directive, ARM
650 @item .code @code{[16|32]}
651 This directive selects the instruction set being generated. The value 16
652 selects Thumb, with the value 32 selecting ARM.
654 @cindex @code{.cpu} directive, ARM
655 @item .cpu @var{name}
656 Select the target processor. Valid values for @var{name} are the same as
657 for the @option{-mcpu} commandline option.
659 Specifying @code{.cpu} clears any previously selected architecture
662 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
664 @cindex @code{.dn} and @code{.qn} directives, ARM
665 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
666 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
668 The @code{dn} and @code{qn} directives are used to create typed
669 and/or indexed register aliases for use in Advanced SIMD Extension
670 (Neon) instructions. The former should be used to create aliases
671 of double-precision registers, and the latter to create aliases of
672 quad-precision registers.
674 If these directives are used to create typed aliases, those aliases can
675 be used in Neon instructions instead of writing types after the mnemonic
676 or after each operand. For example:
685 This is equivalent to writing the following:
691 Aliases created using @code{dn} or @code{qn} can be destroyed using
694 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
696 @cindex @code{.eabi_attribute} directive, ARM
697 @item .eabi_attribute @var{tag}, @var{value}
698 Set the EABI object attribute @var{tag} to @var{value}.
700 The @var{tag} is either an attribute number, or one of the following:
701 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
702 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
703 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
704 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
705 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
706 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
707 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
708 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
709 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
710 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
711 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
712 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
713 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
714 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
715 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
716 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
717 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
718 @code{Tag_conformance}, @code{Tag_T2EE_use},
719 @code{Tag_Virtualization_use}
721 The @var{value} is either a @code{number}, @code{"string"}, or
722 @code{number, "string"} depending on the tag.
724 Note - the following legacy values are also accepted by @var{tag}:
725 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
726 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
728 @cindex @code{.even} directive, ARM
730 This directive aligns to an even-numbered address.
732 @cindex @code{.extend} directive, ARM
733 @cindex @code{.ldouble} directive, ARM
734 @item .extend @var{expression} [, @var{expression}]*
735 @itemx .ldouble @var{expression} [, @var{expression}]*
736 These directives write 12byte long double floating-point values to the
737 output section. These are not compatible with current ARM processors
740 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
743 @cindex @code{.fnend} directive, ARM
745 Marks the end of a function with an unwind table entry. The unwind index
746 table entry is created when this directive is processed.
748 If no personality routine has been specified then standard personality
749 routine 0 or 1 will be used, depending on the number of unwind opcodes
753 @cindex @code{.fnstart} directive, ARM
755 Marks the start of a function with an unwind table entry.
757 @cindex @code{.force_thumb} directive, ARM
759 This directive forces the selection of Thumb instructions, even if the
760 target processor does not support those instructions
762 @cindex @code{.fpu} directive, ARM
763 @item .fpu @var{name}
764 Select the floating-point unit to assemble for. Valid values for @var{name}
765 are the same as for the @option{-mfpu} commandline option.
767 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
768 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
770 @cindex @code{.handlerdata} directive, ARM
772 Marks the end of the current function, and the start of the exception table
773 entry for that function. Anything between this directive and the
774 @code{.fnend} directive will be added to the exception table entry.
776 Must be preceded by a @code{.personality} or @code{.personalityindex}
779 @c IIIIIIIIIIIIIIIIIIIIIIIIII
781 @cindex @code{.inst} directive, ARM
782 @item .inst @var{opcode} [ , @dots{} ]
783 @itemx .inst.n @var{opcode} [ , @dots{} ]
784 @itemx .inst.w @var{opcode} [ , @dots{} ]
785 Generates the instruction corresponding to the numerical value @var{opcode}.
786 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
787 specified explicitly, overriding the normal encoding rules.
789 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
790 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
791 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
793 @item .ldouble @var{expression} [, @var{expression}]*
796 @cindex @code{.ltorg} directive, ARM
798 This directive causes the current contents of the literal pool to be
799 dumped into the current section (which is assumed to be the .text
800 section) at the current location (aligned to a word boundary).
801 @code{GAS} maintains a separate literal pool for each section and each
802 sub-section. The @code{.ltorg} directive will only affect the literal
803 pool of the current section and sub-section. At the end of assembly
804 all remaining, un-empty literal pools will automatically be dumped.
806 Note - older versions of @code{GAS} would dump the current literal
807 pool any time a section change occurred. This is no longer done, since
808 it prevents accurate control of the placement of literal pools.
810 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
812 @cindex @code{.movsp} directive, ARM
813 @item .movsp @var{reg} [, #@var{offset}]
814 Tell the unwinder that @var{reg} contains an offset from the current
815 stack pointer. If @var{offset} is not specified then it is assumed to be
818 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
819 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
821 @cindex @code{.object_arch} directive, ARM
822 @item .object_arch @var{name}
823 Override the architecture recorded in the EABI object attribute section.
824 Valid values for @var{name} are the same as for the @code{.arch} directive.
825 Typically this is useful when code uses runtime detection of CPU features.
827 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
829 @cindex @code{.packed} directive, ARM
830 @item .packed @var{expression} [, @var{expression}]*
831 This directive writes 12-byte packed floating-point values to the
832 output section. These are not compatible with current ARM processors
836 @cindex @code{.pad} directive, ARM
837 @item .pad #@var{count}
838 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
839 A positive value indicates the function prologue allocated stack space by
840 decrementing the stack pointer.
842 @cindex @code{.personality} directive, ARM
843 @item .personality @var{name}
844 Sets the personality routine for the current function to @var{name}.
846 @cindex @code{.personalityindex} directive, ARM
847 @item .personalityindex @var{index}
848 Sets the personality routine for the current function to the EABI standard
849 routine number @var{index}
851 @cindex @code{.pool} directive, ARM
853 This is a synonym for .ltorg.
855 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
856 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
858 @cindex @code{.req} directive, ARM
859 @item @var{name} .req @var{register name}
860 This creates an alias for @var{register name} called @var{name}. For
867 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
870 @cindex @code{.save} directive, ARM
871 @item .save @var{reglist}
872 Generate unwinder annotations to restore the registers in @var{reglist}.
873 The format of @var{reglist} is the same as the corresponding store-multiple
877 @exdent @emph{core registers}
878 .save @{r4, r5, r6, lr@}
879 stmfd sp!, @{r4, r5, r6, lr@}
880 @exdent @emph{FPA registers}
883 @exdent @emph{VFP registers}
884 .save @{d8, d9, d10@}
885 fstmdx sp!, @{d8, d9, d10@}
886 @exdent @emph{iWMMXt registers}
888 wstrd wr11, [sp, #-8]!
889 wstrd wr10, [sp, #-8]!
892 wstrd wr11, [sp, #-8]!
894 wstrd wr10, [sp, #-8]!
898 @cindex @code{.setfp} directive, ARM
899 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
900 Make all unwinder annotations relative to a frame pointer. Without this
901 the unwinder will use offsets from the stack pointer.
903 The syntax of this directive is the same as the @code{add} or @code{mov}
904 instruction used to set the frame pointer. @var{spreg} must be either
905 @code{sp} or mentioned in a previous @code{.movsp} directive.
915 @cindex @code{.secrel32} directive, ARM
916 @item .secrel32 @var{expression} [, @var{expression}]*
917 This directive emits relocations that evaluate to the section-relative
918 offset of each expression's symbol. This directive is only supported
921 @cindex @code{.syntax} directive, ARM
922 @item .syntax [@code{unified} | @code{divided}]
923 This directive sets the Instruction Set Syntax as described in the
924 @ref{ARM-Instruction-Set} section.
926 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
928 @cindex @code{.thumb} directive, ARM
930 This performs the same action as @var{.code 16}.
932 @cindex @code{.thumb_func} directive, ARM
934 This directive specifies that the following symbol is the name of a
935 Thumb encoded function. This information is necessary in order to allow
936 the assembler and linker to generate correct code for interworking
937 between Arm and Thumb instructions and should be used even if
938 interworking is not going to be performed. The presence of this
939 directive also implies @code{.thumb}
941 This directive is not necessary when generating EABI objects. On these
942 targets the encoding is implicit when generating Thumb code.
944 @cindex @code{.thumb_set} directive, ARM
946 This performs the equivalent of a @code{.set} directive in that it
947 creates a symbol which is an alias for another symbol (possibly not yet
948 defined). This directive also has the added property in that it marks
949 the aliased symbol as being a thumb function entry point, in the same
950 way that the @code{.thumb_func} directive does.
952 @cindex @code{.tlsdescseq} directive, ARM
953 @item .tlsdescseq @var{tls-variable}
954 This directive is used to annotate parts of an inlined TLS descriptor
955 trampoline. Normally the trampoline is provided by the linker, and
956 this directive is not needed.
958 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
960 @cindex @code{.unreq} directive, ARM
961 @item .unreq @var{alias-name}
962 This undefines a register alias which was previously defined using the
963 @code{req}, @code{dn} or @code{qn} directives. For example:
970 An error occurs if the name is undefined. Note - this pseudo op can
971 be used to delete builtin in register name aliases (eg 'r0'). This
972 should only be done if it is really necessary.
974 @cindex @code{.unwind_raw} directive, ARM
975 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
976 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
977 the stack pointer by @var{offset} bytes.
979 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
982 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
984 @cindex @code{.vsave} directive, ARM
985 @item .vsave @var{vfp-reglist}
986 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
987 using FLDMD. Also works for VFPv3 registers
988 that are to be restored using VLDM.
989 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
993 @exdent @emph{VFP registers}
994 .vsave @{d8, d9, d10@}
995 fstmdd sp!, @{d8, d9, d10@}
996 @exdent @emph{VFPv3 registers}
997 .vsave @{d15, d16, d17@}
998 vstm sp!, @{d15, d16, d17@}
1001 Since FLDMX and FSTMX are now deprecated, this directive should be
1002 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1004 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1005 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1006 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1007 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1015 @cindex opcodes for ARM
1016 @code{@value{AS}} implements all the standard ARM opcodes. It also
1017 implements several pseudo opcodes, including several synthetic load
1022 @cindex @code{NOP} pseudo op, ARM
1028 This pseudo op will always evaluate to a legal ARM instruction that does
1029 nothing. Currently it will evaluate to MOV r0, r0.
1031 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1034 ldr <register> , = <expression>
1037 If expression evaluates to a numeric constant then a MOV or MVN
1038 instruction will be used in place of the LDR instruction, if the
1039 constant can be generated by either of these instructions. Otherwise
1040 the constant will be placed into the nearest literal pool (if it not
1041 already there) and a PC relative LDR instruction will be generated.
1043 @cindex @code{ADR reg,<label>} pseudo op, ARM
1046 adr <register> <label>
1049 This instruction will load the address of @var{label} into the indicated
1050 register. The instruction will evaluate to a PC relative ADD or SUB
1051 instruction depending upon where the label is located. If the label is
1052 out of range, or if it is not defined in the same file (and section) as
1053 the ADR instruction, then an error will be generated. This instruction
1054 will not make use of the literal pool.
1056 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1059 adrl <register> <label>
1062 This instruction will load the address of @var{label} into the indicated
1063 register. The instruction will evaluate to one or two PC relative ADD
1064 or SUB instructions depending upon where the label is located. If a
1065 second instruction is not needed a NOP instruction will be generated in
1066 its place, so that this instruction is always 8 bytes long.
1068 If the label is out of range, or if it is not defined in the same file
1069 (and section) as the ADRL instruction, then an error will be generated.
1070 This instruction will not make use of the literal pool.
1074 For information on the ARM or Thumb instruction sets, see @cite{ARM
1075 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1078 @node ARM Mapping Symbols
1079 @section Mapping Symbols
1081 The ARM ELF specification requires that special symbols be inserted
1082 into object files to mark certain features:
1088 At the start of a region of code containing ARM instructions.
1092 At the start of a region of code containing THUMB instructions.
1096 At the start of a region of data.
1100 The assembler will automatically insert these symbols for you - there
1101 is no need to code them yourself. Support for tagging symbols ($b,
1102 $f, $p and $m) which is also mentioned in the current ARM ELF
1103 specification is not implemented. This is because they have been
1104 dropped from the new EABI and so tools cannot rely upon their
1107 @node ARM Unwinding Tutorial
1110 The ABI for the ARM Architecture specifies a standard format for
1111 exception unwind information. This information is used when an
1112 exception is thrown to determine where control should be transferred.
1113 In particular, the unwind information is used to determine which
1114 function called the function that threw the exception, and which
1115 function called that one, and so forth. This information is also used
1116 to restore the values of callee-saved registers in the function
1117 catching the exception.
1119 If you are writing functions in assembly code, and those functions
1120 call other functions that throw exceptions, you must use assembly
1121 pseudo ops to ensure that appropriate exception unwind information is
1122 generated. Otherwise, if one of the functions called by your assembly
1123 code throws an exception, the run-time library will be unable to
1124 unwind the stack through your assembly code and your program will not
1127 To illustrate the use of these pseudo ops, we will examine the code
1128 that G++ generates for the following C++ input:
1131 void callee (int *);
1142 This example does not show how to throw or catch an exception from
1143 assembly code. That is a much more complex operation and should
1144 always be done in a high-level language, such as C++, that directly
1145 supports exceptions.
1147 The code generated by one particular version of G++ when compiling the
1154 @ Function supports interworking.
1155 @ args = 0, pretend = 0, frame = 8
1156 @ frame_needed = 1, uses_anonymous_args = 0
1178 Of course, the sequence of instructions varies based on the options
1179 you pass to GCC and on the version of GCC in use. The exact
1180 instructions are not important since we are focusing on the pseudo ops
1181 that are used to generate unwind information.
1183 An important assumption made by the unwinder is that the stack frame
1184 does not change during the body of the function. In particular, since
1185 we assume that the assembly code does not itself throw an exception,
1186 the only point where an exception can be thrown is from a call, such
1187 as the @code{bl} instruction above. At each call site, the same saved
1188 registers (including @code{lr}, which indicates the return address)
1189 must be located in the same locations relative to the frame pointer.
1191 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1192 op appears immediately before the first instruction of the function
1193 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1194 op appears immediately after the last instruction of the function.
1195 These pseudo ops specify the range of the function.
1197 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1198 @code{.pad}) matters; their exact locations are irrelevant. In the
1199 example above, the compiler emits the pseudo ops with particular
1200 instructions. That makes it easier to understand the code, but it is
1201 not required for correctness. It would work just as well to emit all
1202 of the pseudo ops other than @code{.fnend} in the same order, but
1203 immediately after @code{.fnstart}.
1205 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1206 indicates registers that have been saved to the stack so that they can
1207 be restored before the function returns. The argument to the
1208 @code{.save} pseudo op is a list of registers to save. If a register
1209 is ``callee-saved'' (as specified by the ABI) and is modified by the
1210 function you are writing, then your code must save the value before it
1211 is modified and restore the original value before the function
1212 returns. If an exception is thrown, the run-time library restores the
1213 values of these registers from their locations on the stack before
1214 returning control to the exception handler. (Of course, if an
1215 exception is not thrown, the function that contains the @code{.save}
1216 pseudo op restores these registers in the function epilogue, as is
1217 done with the @code{ldmfd} instruction above.)
1219 You do not have to save callee-saved registers at the very beginning
1220 of the function and you do not need to use the @code{.save} pseudo op
1221 immediately following the point at which the registers are saved.
1222 However, if you modify a callee-saved register, you must save it on
1223 the stack before modifying it and before calling any functions which
1224 might throw an exception. And, you must use the @code{.save} pseudo
1225 op to indicate that you have done so.
1227 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1228 modification of the stack pointer that does not save any registers.
1229 The argument is the number of bytes (in decimal) that are subtracted
1230 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1231 subtracting from the stack pointer increases the size of the stack.)
1233 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1234 indicates the register that contains the frame pointer. The first
1235 argument is the register that is set, which is typically @code{fp}.
1236 The second argument indicates the register from which the frame
1237 pointer takes its value. The third argument, if present, is the value
1238 (in decimal) added to the register specified by the second argument to
1239 compute the value of the frame pointer. You should not modify the
1240 frame pointer in the body of the function.
1242 If you do not use a frame pointer, then you should not use the
1243 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1244 should avoid modifying the stack pointer outside of the function
1245 prologue. Otherwise, the run-time library will be unable to find
1246 saved registers when it is unwinding the stack.
1248 The pseudo ops described above are sufficient for writing assembly
1249 code that calls functions which may throw exceptions. If you need to
1250 know more about the object-file format used to represent unwind
1251 information, you may consult the @cite{Exception Handling ABI for the
1252 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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