[ARM] Support for ARMv8.1 Adv.SIMD extension
[deliverable/binutils-gdb.git] / gas / doc / c-arm.texi
1 @c Copyright (C) 1996-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
4
5 @ifset GENERIC
6 @page
7 @node ARM-Dependent
8 @chapter ARM Dependent Features
9 @end ifset
10
11 @ifclear GENERIC
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
14 @end ifclear
15
16 @cindex ARM support
17 @cindex Thumb support
18 @menu
19 * ARM Options:: Options
20 * ARM Syntax:: Syntax
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
26 @end menu
27
28 @node ARM Options
29 @section Options
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
32
33 @table @code
34
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
40 recognized:
41 @code{arm1},
42 @code{arm2},
43 @code{arm250},
44 @code{arm3},
45 @code{arm6},
46 @code{arm60},
47 @code{arm600},
48 @code{arm610},
49 @code{arm620},
50 @code{arm7},
51 @code{arm7m},
52 @code{arm7d},
53 @code{arm7dm},
54 @code{arm7di},
55 @code{arm7dmi},
56 @code{arm70},
57 @code{arm700},
58 @code{arm700i},
59 @code{arm710},
60 @code{arm710t},
61 @code{arm720},
62 @code{arm720t},
63 @code{arm740t},
64 @code{arm710c},
65 @code{arm7100},
66 @code{arm7500},
67 @code{arm7500fe},
68 @code{arm7t},
69 @code{arm7tdmi},
70 @code{arm7tdmi-s},
71 @code{arm8},
72 @code{arm810},
73 @code{strongarm},
74 @code{strongarm1},
75 @code{strongarm110},
76 @code{strongarm1100},
77 @code{strongarm1110},
78 @code{arm9},
79 @code{arm920},
80 @code{arm920t},
81 @code{arm922t},
82 @code{arm940t},
83 @code{arm9tdmi},
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
86 @code{arm9e},
87 @code{arm926e},
88 @code{arm926ej-s},
89 @code{arm946e-r0},
90 @code{arm946e},
91 @code{arm946e-s},
92 @code{arm966e-r0},
93 @code{arm966e},
94 @code{arm966e-s},
95 @code{arm968e-s},
96 @code{arm10t},
97 @code{arm10tdmi},
98 @code{arm10e},
99 @code{arm1020},
100 @code{arm1020t},
101 @code{arm1020e},
102 @code{arm1022e},
103 @code{arm1026ej-s},
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
109 @code{arm1136j-s},
110 @code{arm1136jf-s},
111 @code{arm1156t2-s},
112 @code{arm1156t2f-s},
113 @code{arm1176jz-s},
114 @code{arm1176jzf-s},
115 @code{mpcore},
116 @code{mpcorenovfp},
117 @code{cortex-a5},
118 @code{cortex-a7},
119 @code{cortex-a8},
120 @code{cortex-a9},
121 @code{cortex-a15},
122 @code{cortex-a53},
123 @code{cortex-a57},
124 @code{cortex-a72},
125 @code{cortex-r4},
126 @code{cortex-r4f},
127 @code{cortex-r5},
128 @code{cortex-r7},
129 @code{cortex-m7},
130 @code{cortex-m4},
131 @code{cortex-m3},
132 @code{cortex-m1},
133 @code{cortex-m0},
134 @code{cortex-m0plus},
135 @code{exynos-m1},
136 @code{marvell-pj4},
137 @code{marvell-whitney},
138 @code{xgene1},
139 @code{xgene2},
140 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
141 @code{i80200} (Intel XScale processor)
142 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
143 and
144 @code{xscale}.
145 The special name @code{all} may be used to allow the
146 assembler to accept instructions valid for any ARM processor.
147
148 In addition to the basic instruction set, the assembler can be told to
149 accept various extension mnemonics that extend the processor using the
150 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
151 is equivalent to specifying @code{-mcpu=ep9312}.
152
153 Multiple extensions may be specified, separated by a @code{+}. The
154 extensions should be specified in ascending alphabetical order.
155
156 Some extensions may be restricted to particular architectures; this is
157 documented in the list of extensions below.
158
159 Extension mnemonics may also be removed from those the assembler accepts.
160 This is done be prepending @code{no} to the option that adds the extension.
161 Extensions that are removed should be listed after all extensions which have
162 been added, again in ascending alphabetical order. For example,
163 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
164
165
166 The following extensions are currently supported:
167 @code{crc}
168 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
169 @code{fp} (Floating Point Extensions for v8-A architecture),
170 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
171 @code{iwmmxt},
172 @code{iwmmxt2},
173 @code{xscale},
174 @code{maverick},
175 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
176 architectures),
177 @code{os} (Operating System for v6M architecture),
178 @code{sec} (Security Extensions for v6K and v7-A architectures),
179 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
180 @code{virt} (Virtualization Extensions for v7-A architecture, implies
181 @code{idiv}),
182 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
183 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
184 @code{simd})
185 and
186 @code{xscale}.
187
188 @cindex @code{-march=} command line option, ARM
189 @item -march=@var{architecture}[+@var{extension}@dots{}]
190 This option specifies the target architecture. The assembler will issue
191 an error message if an attempt is made to assemble an instruction which
192 will not execute on the target architecture. The following architecture
193 names are recognized:
194 @code{armv1},
195 @code{armv2},
196 @code{armv2a},
197 @code{armv2s},
198 @code{armv3},
199 @code{armv3m},
200 @code{armv4},
201 @code{armv4xm},
202 @code{armv4t},
203 @code{armv4txm},
204 @code{armv5},
205 @code{armv5t},
206 @code{armv5txm},
207 @code{armv5te},
208 @code{armv5texp},
209 @code{armv6},
210 @code{armv6j},
211 @code{armv6k},
212 @code{armv6z},
213 @code{armv6zk},
214 @code{armv6-m},
215 @code{armv6s-m},
216 @code{armv7},
217 @code{armv7-a},
218 @code{armv7ve},
219 @code{armv7-r},
220 @code{armv7-m},
221 @code{armv7e-m},
222 @code{armv8-a},
223 @code{iwmmxt}
224 @code{iwmmxt2}
225 and
226 @code{xscale}.
227 If both @code{-mcpu} and
228 @code{-march} are specified, the assembler will use
229 the setting for @code{-mcpu}.
230
231 The architecture option can be extended with the same instruction set
232 extension options as the @code{-mcpu} option.
233
234 @cindex @code{-mfpu=} command line option, ARM
235 @item -mfpu=@var{floating-point-format}
236
237 This option specifies the floating point format to assemble for. The
238 assembler will issue an error message if an attempt is made to assemble
239 an instruction which will not execute on the target floating point unit.
240 The following format options are recognized:
241 @code{softfpa},
242 @code{fpe},
243 @code{fpe2},
244 @code{fpe3},
245 @code{fpa},
246 @code{fpa10},
247 @code{fpa11},
248 @code{arm7500fe},
249 @code{softvfp},
250 @code{softvfp+vfp},
251 @code{vfp},
252 @code{vfp10},
253 @code{vfp10-r0},
254 @code{vfp9},
255 @code{vfpxd},
256 @code{vfpv2},
257 @code{vfpv3},
258 @code{vfpv3-fp16},
259 @code{vfpv3-d16},
260 @code{vfpv3-d16-fp16},
261 @code{vfpv3xd},
262 @code{vfpv3xd-d16},
263 @code{vfpv4},
264 @code{vfpv4-d16},
265 @code{fpv4-sp-d16},
266 @code{fpv5-sp-d16},
267 @code{fpv5-d16},
268 @code{fp-armv8},
269 @code{arm1020t},
270 @code{arm1020e},
271 @code{arm1136jf-s},
272 @code{maverick},
273 @code{neon},
274 @code{neon-vfpv4},
275 @code{neon-fp-armv8},
276 @code{crypto-neon-fp-armv8}.
277 and
278 @code{neon-fp-armv8-1},
279
280 In addition to determining which instructions are assembled, this option
281 also affects the way in which the @code{.double} assembler directive behaves
282 when assembling little-endian code.
283
284 The default is dependent on the processor selected. For Architecture 5 or
285 later, the default is to assembler for VFP instructions; for earlier
286 architectures the default is to assemble for FPA instructions.
287
288 @cindex @code{-mthumb} command line option, ARM
289 @item -mthumb
290 This option specifies that the assembler should start assembling Thumb
291 instructions; that is, it should behave as though the file starts with a
292 @code{.code 16} directive.
293
294 @cindex @code{-mthumb-interwork} command line option, ARM
295 @item -mthumb-interwork
296 This option specifies that the output generated by the assembler should
297 be marked as supporting interworking.
298
299 @cindex @code{-mimplicit-it} command line option, ARM
300 @item -mimplicit-it=never
301 @itemx -mimplicit-it=always
302 @itemx -mimplicit-it=arm
303 @itemx -mimplicit-it=thumb
304 The @code{-mimplicit-it} option controls the behavior of the assembler when
305 conditional instructions are not enclosed in IT blocks.
306 There are four possible behaviors.
307 If @code{never} is specified, such constructs cause a warning in ARM
308 code and an error in Thumb-2 code.
309 If @code{always} is specified, such constructs are accepted in both
310 ARM and Thumb-2 code, where the IT instruction is added implicitly.
311 If @code{arm} is specified, such constructs are accepted in ARM code
312 and cause an error in Thumb-2 code.
313 If @code{thumb} is specified, such constructs cause a warning in ARM
314 code and are accepted in Thumb-2 code. If you omit this option, the
315 behavior is equivalent to @code{-mimplicit-it=arm}.
316
317 @cindex @code{-mapcs-26} command line option, ARM
318 @cindex @code{-mapcs-32} command line option, ARM
319 @item -mapcs-26
320 @itemx -mapcs-32
321 These options specify that the output generated by the assembler should
322 be marked as supporting the indicated version of the Arm Procedure.
323 Calling Standard.
324
325 @cindex @code{-matpcs} command line option, ARM
326 @item -matpcs
327 This option specifies that the output generated by the assembler should
328 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
329 enabled this option will cause the assembler to create an empty
330 debugging section in the object file called .arm.atpcs. Debuggers can
331 use this to determine the ABI being used by.
332
333 @cindex @code{-mapcs-float} command line option, ARM
334 @item -mapcs-float
335 This indicates the floating point variant of the APCS should be
336 used. In this variant floating point arguments are passed in FP
337 registers rather than integer registers.
338
339 @cindex @code{-mapcs-reentrant} command line option, ARM
340 @item -mapcs-reentrant
341 This indicates that the reentrant variant of the APCS should be used.
342 This variant supports position independent code.
343
344 @cindex @code{-mfloat-abi=} command line option, ARM
345 @item -mfloat-abi=@var{abi}
346 This option specifies that the output generated by the assembler should be
347 marked as using specified floating point ABI.
348 The following values are recognized:
349 @code{soft},
350 @code{softfp}
351 and
352 @code{hard}.
353
354 @cindex @code{-eabi=} command line option, ARM
355 @item -meabi=@var{ver}
356 This option specifies which EABI version the produced object files should
357 conform to.
358 The following values are recognized:
359 @code{gnu},
360 @code{4}
361 and
362 @code{5}.
363
364 @cindex @code{-EB} command line option, ARM
365 @item -EB
366 This option specifies that the output generated by the assembler should
367 be marked as being encoded for a big-endian processor.
368
369 Note: If a program is being built for a system with big-endian data
370 and little-endian instructions then it should be assembled with the
371 @option{-EB} option, (all of it, code and data) and then linked with
372 the @option{--be8} option. This will reverse the endianness of the
373 instructions back to little-endian, but leave the data as big-endian.
374
375 @cindex @code{-EL} command line option, ARM
376 @item -EL
377 This option specifies that the output generated by the assembler should
378 be marked as being encoded for a little-endian processor.
379
380 @cindex @code{-k} command line option, ARM
381 @cindex PIC code generation for ARM
382 @item -k
383 This option specifies that the output of the assembler should be marked
384 as position-independent code (PIC).
385
386 @cindex @code{--fix-v4bx} command line option, ARM
387 @item --fix-v4bx
388 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
389 the linker option of the same name.
390
391 @cindex @code{-mwarn-deprecated} command line option, ARM
392 @item -mwarn-deprecated
393 @itemx -mno-warn-deprecated
394 Enable or disable warnings about using deprecated options or
395 features. The default is to warn.
396
397 @cindex @code{-mccs} command line option, ARM
398 @item -mccs
399 Turns on CodeComposer Studio assembly syntax compatibility mode.
400
401 @cindex @code{-mwarn-syms} command line option, ARM
402 @item -mwarn-syms
403 @itemx -mno-warn-syms
404 Enable or disable warnings about symbols that match the names of ARM
405 instructions. The default is to warn.
406
407 @end table
408
409
410 @node ARM Syntax
411 @section Syntax
412 @menu
413 * ARM-Instruction-Set:: Instruction Set
414 * ARM-Chars:: Special Characters
415 * ARM-Regs:: Register Names
416 * ARM-Relocations:: Relocations
417 * ARM-Neon-Alignment:: NEON Alignment Specifiers
418 @end menu
419
420 @node ARM-Instruction-Set
421 @subsection Instruction Set Syntax
422 Two slightly different syntaxes are support for ARM and THUMB
423 instructions. The default, @code{divided}, uses the old style where
424 ARM and THUMB instructions had their own, separate syntaxes. The new,
425 @code{unified} syntax, which can be selected via the @code{.syntax}
426 directive, and has the following main features:
427
428 @itemize @bullet
429 @item
430 Immediate operands do not require a @code{#} prefix.
431
432 @item
433 The @code{IT} instruction may appear, and if it does it is validated
434 against subsequent conditional affixes. In ARM mode it does not
435 generate machine code, in THUMB mode it does.
436
437 @item
438 For ARM instructions the conditional affixes always appear at the end
439 of the instruction. For THUMB instructions conditional affixes can be
440 used, but only inside the scope of an @code{IT} instruction.
441
442 @item
443 All of the instructions new to the V6T2 architecture (and later) are
444 available. (Only a few such instructions can be written in the
445 @code{divided} syntax).
446
447 @item
448 The @code{.N} and @code{.W} suffixes are recognized and honored.
449
450 @item
451 All instructions set the flags if and only if they have an @code{s}
452 affix.
453 @end itemize
454
455 @node ARM-Chars
456 @subsection Special Characters
457
458 @cindex line comment character, ARM
459 @cindex ARM line comment character
460 The presence of a @samp{@@} anywhere on a line indicates the start of
461 a comment that extends to the end of that line.
462
463 If a @samp{#} appears as the first character of a line then the whole
464 line is treated as a comment, but in this case the line could also be
465 a logical line number directive (@pxref{Comments}) or a preprocessor
466 control command (@pxref{Preprocessing}).
467
468 @cindex line separator, ARM
469 @cindex statement separator, ARM
470 @cindex ARM line separator
471 The @samp{;} character can be used instead of a newline to separate
472 statements.
473
474 @cindex immediate character, ARM
475 @cindex ARM immediate character
476 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
477
478 @cindex identifiers, ARM
479 @cindex ARM identifiers
480 *TODO* Explain about /data modifier on symbols.
481
482 @node ARM-Regs
483 @subsection Register Names
484
485 @cindex ARM register names
486 @cindex register names, ARM
487 *TODO* Explain about ARM register naming, and the predefined names.
488
489 @node ARM-Relocations
490 @subsection ARM relocation generation
491
492 @cindex data relocations, ARM
493 @cindex ARM data relocations
494 Specific data relocations can be generated by putting the relocation name
495 in parentheses after the symbol name. For example:
496
497 @smallexample
498 .word foo(TARGET1)
499 @end smallexample
500
501 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
502 @var{foo}.
503 The following relocations are supported:
504 @code{GOT},
505 @code{GOTOFF},
506 @code{TARGET1},
507 @code{TARGET2},
508 @code{SBREL},
509 @code{TLSGD},
510 @code{TLSLDM},
511 @code{TLSLDO},
512 @code{TLSDESC},
513 @code{TLSCALL},
514 @code{GOTTPOFF},
515 @code{GOT_PREL}
516 and
517 @code{TPOFF}.
518
519 For compatibility with older toolchains the assembler also accepts
520 @code{(PLT)} after branch targets. On legacy targets this will
521 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
522 targets it will encode either the @samp{R_ARM_CALL} or
523 @samp{R_ARM_JUMP24} relocation, as appropriate.
524
525 @cindex MOVW and MOVT relocations, ARM
526 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
527 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
528 respectively. For example to load the 32-bit address of foo into r0:
529
530 @smallexample
531 MOVW r0, #:lower16:foo
532 MOVT r0, #:upper16:foo
533 @end smallexample
534
535 @node ARM-Neon-Alignment
536 @subsection NEON Alignment Specifiers
537
538 @cindex alignment for NEON instructions
539 Some NEON load/store instructions allow an optional address
540 alignment qualifier.
541 The ARM documentation specifies that this is indicated by
542 @samp{@@ @var{align}}. However GAS already interprets
543 the @samp{@@} character as a "line comment" start,
544 so @samp{: @var{align}} is used instead. For example:
545
546 @smallexample
547 vld1.8 @{q0@}, [r0, :128]
548 @end smallexample
549
550 @node ARM Floating Point
551 @section Floating Point
552
553 @cindex floating point, ARM (@sc{ieee})
554 @cindex ARM floating point (@sc{ieee})
555 The ARM family uses @sc{ieee} floating-point numbers.
556
557 @node ARM Directives
558 @section ARM Machine Directives
559
560 @cindex machine directives, ARM
561 @cindex ARM machine directives
562 @table @code
563
564 @c AAAAAAAAAAAAAAAAAAAAAAAAA
565
566 @cindex @code{.2byte} directive, ARM
567 @cindex @code{.4byte} directive, ARM
568 @cindex @code{.8byte} directive, ARM
569 @item .2byte @var{expression} [, @var{expression}]*
570 @itemx .4byte @var{expression} [, @var{expression}]*
571 @itemx .8byte @var{expression} [, @var{expression}]*
572 These directives write 2, 4 or 8 byte values to the output section.
573
574 @cindex @code{.align} directive, ARM
575 @item .align @var{expression} [, @var{expression}]
576 This is the generic @var{.align} directive. For the ARM however if the
577 first argument is zero (ie no alignment is needed) the assembler will
578 behave as if the argument had been 2 (ie pad to the next four byte
579 boundary). This is for compatibility with ARM's own assembler.
580
581 @cindex @code{.arch} directive, ARM
582 @item .arch @var{name}
583 Select the target architecture. Valid values for @var{name} are the same as
584 for the @option{-march} commandline option.
585
586 Specifying @code{.arch} clears any previously selected architecture
587 extensions.
588
589 @cindex @code{.arch_extension} directive, ARM
590 @item .arch_extension @var{name}
591 Add or remove an architecture extension to the target architecture. Valid
592 values for @var{name} are the same as those accepted as architectural
593 extensions by the @option{-mcpu} commandline option.
594
595 @code{.arch_extension} may be used multiple times to add or remove extensions
596 incrementally to the architecture being compiled for.
597
598 @cindex @code{.arm} directive, ARM
599 @item .arm
600 This performs the same action as @var{.code 32}.
601
602 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
603
604 @cindex @code{.bss} directive, ARM
605 @item .bss
606 This directive switches to the @code{.bss} section.
607
608 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
609
610 @cindex @code{.cantunwind} directive, ARM
611 @item .cantunwind
612 Prevents unwinding through the current function. No personality routine
613 or exception table data is required or permitted.
614
615 @cindex @code{.code} directive, ARM
616 @item .code @code{[16|32]}
617 This directive selects the instruction set being generated. The value 16
618 selects Thumb, with the value 32 selecting ARM.
619
620 @cindex @code{.cpu} directive, ARM
621 @item .cpu @var{name}
622 Select the target processor. Valid values for @var{name} are the same as
623 for the @option{-mcpu} commandline option.
624
625 Specifying @code{.cpu} clears any previously selected architecture
626 extensions.
627
628 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
629
630 @cindex @code{.dn} and @code{.qn} directives, ARM
631 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
632 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
633
634 The @code{dn} and @code{qn} directives are used to create typed
635 and/or indexed register aliases for use in Advanced SIMD Extension
636 (Neon) instructions. The former should be used to create aliases
637 of double-precision registers, and the latter to create aliases of
638 quad-precision registers.
639
640 If these directives are used to create typed aliases, those aliases can
641 be used in Neon instructions instead of writing types after the mnemonic
642 or after each operand. For example:
643
644 @smallexample
645 x .dn d2.f32
646 y .dn d3.f32
647 z .dn d4.f32[1]
648 vmul x,y,z
649 @end smallexample
650
651 This is equivalent to writing the following:
652
653 @smallexample
654 vmul.f32 d2,d3,d4[1]
655 @end smallexample
656
657 Aliases created using @code{dn} or @code{qn} can be destroyed using
658 @code{unreq}.
659
660 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
661
662 @cindex @code{.eabi_attribute} directive, ARM
663 @item .eabi_attribute @var{tag}, @var{value}
664 Set the EABI object attribute @var{tag} to @var{value}.
665
666 The @var{tag} is either an attribute number, or one of the following:
667 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
668 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
669 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
670 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
671 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
672 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
673 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
674 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
675 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
676 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
677 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
678 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
679 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
680 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
681 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
682 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
683 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
684 @code{Tag_conformance}, @code{Tag_T2EE_use},
685 @code{Tag_Virtualization_use}
686
687 The @var{value} is either a @code{number}, @code{"string"}, or
688 @code{number, "string"} depending on the tag.
689
690 Note - the following legacy values are also accepted by @var{tag}:
691 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
692 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
693
694 @cindex @code{.even} directive, ARM
695 @item .even
696 This directive aligns to an even-numbered address.
697
698 @cindex @code{.extend} directive, ARM
699 @cindex @code{.ldouble} directive, ARM
700 @item .extend @var{expression} [, @var{expression}]*
701 @itemx .ldouble @var{expression} [, @var{expression}]*
702 These directives write 12byte long double floating-point values to the
703 output section. These are not compatible with current ARM processors
704 or ABIs.
705
706 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
707
708 @anchor{arm_fnend}
709 @cindex @code{.fnend} directive, ARM
710 @item .fnend
711 Marks the end of a function with an unwind table entry. The unwind index
712 table entry is created when this directive is processed.
713
714 If no personality routine has been specified then standard personality
715 routine 0 or 1 will be used, depending on the number of unwind opcodes
716 required.
717
718 @anchor{arm_fnstart}
719 @cindex @code{.fnstart} directive, ARM
720 @item .fnstart
721 Marks the start of a function with an unwind table entry.
722
723 @cindex @code{.force_thumb} directive, ARM
724 @item .force_thumb
725 This directive forces the selection of Thumb instructions, even if the
726 target processor does not support those instructions
727
728 @cindex @code{.fpu} directive, ARM
729 @item .fpu @var{name}
730 Select the floating-point unit to assemble for. Valid values for @var{name}
731 are the same as for the @option{-mfpu} commandline option.
732
733 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
734 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
735
736 @cindex @code{.handlerdata} directive, ARM
737 @item .handlerdata
738 Marks the end of the current function, and the start of the exception table
739 entry for that function. Anything between this directive and the
740 @code{.fnend} directive will be added to the exception table entry.
741
742 Must be preceded by a @code{.personality} or @code{.personalityindex}
743 directive.
744
745 @c IIIIIIIIIIIIIIIIIIIIIIIIII
746
747 @cindex @code{.inst} directive, ARM
748 @item .inst @var{opcode} [ , @dots{} ]
749 @itemx .inst.n @var{opcode} [ , @dots{} ]
750 @itemx .inst.w @var{opcode} [ , @dots{} ]
751 Generates the instruction corresponding to the numerical value @var{opcode}.
752 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
753 specified explicitly, overriding the normal encoding rules.
754
755 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
756 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
757 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
758
759 @item .ldouble @var{expression} [, @var{expression}]*
760 See @code{.extend}.
761
762 @cindex @code{.ltorg} directive, ARM
763 @item .ltorg
764 This directive causes the current contents of the literal pool to be
765 dumped into the current section (which is assumed to be the .text
766 section) at the current location (aligned to a word boundary).
767 @code{GAS} maintains a separate literal pool for each section and each
768 sub-section. The @code{.ltorg} directive will only affect the literal
769 pool of the current section and sub-section. At the end of assembly
770 all remaining, un-empty literal pools will automatically be dumped.
771
772 Note - older versions of @code{GAS} would dump the current literal
773 pool any time a section change occurred. This is no longer done, since
774 it prevents accurate control of the placement of literal pools.
775
776 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
777
778 @cindex @code{.movsp} directive, ARM
779 @item .movsp @var{reg} [, #@var{offset}]
780 Tell the unwinder that @var{reg} contains an offset from the current
781 stack pointer. If @var{offset} is not specified then it is assumed to be
782 zero.
783
784 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
785 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
786
787 @cindex @code{.object_arch} directive, ARM
788 @item .object_arch @var{name}
789 Override the architecture recorded in the EABI object attribute section.
790 Valid values for @var{name} are the same as for the @code{.arch} directive.
791 Typically this is useful when code uses runtime detection of CPU features.
792
793 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
794
795 @cindex @code{.packed} directive, ARM
796 @item .packed @var{expression} [, @var{expression}]*
797 This directive writes 12-byte packed floating-point values to the
798 output section. These are not compatible with current ARM processors
799 or ABIs.
800
801 @anchor{arm_pad}
802 @cindex @code{.pad} directive, ARM
803 @item .pad #@var{count}
804 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
805 A positive value indicates the function prologue allocated stack space by
806 decrementing the stack pointer.
807
808 @cindex @code{.personality} directive, ARM
809 @item .personality @var{name}
810 Sets the personality routine for the current function to @var{name}.
811
812 @cindex @code{.personalityindex} directive, ARM
813 @item .personalityindex @var{index}
814 Sets the personality routine for the current function to the EABI standard
815 routine number @var{index}
816
817 @cindex @code{.pool} directive, ARM
818 @item .pool
819 This is a synonym for .ltorg.
820
821 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
822 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
823
824 @cindex @code{.req} directive, ARM
825 @item @var{name} .req @var{register name}
826 This creates an alias for @var{register name} called @var{name}. For
827 example:
828
829 @smallexample
830 foo .req r0
831 @end smallexample
832
833 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
834
835 @anchor{arm_save}
836 @cindex @code{.save} directive, ARM
837 @item .save @var{reglist}
838 Generate unwinder annotations to restore the registers in @var{reglist}.
839 The format of @var{reglist} is the same as the corresponding store-multiple
840 instruction.
841
842 @smallexample
843 @exdent @emph{core registers}
844 .save @{r4, r5, r6, lr@}
845 stmfd sp!, @{r4, r5, r6, lr@}
846 @exdent @emph{FPA registers}
847 .save f4, 2
848 sfmfd f4, 2, [sp]!
849 @exdent @emph{VFP registers}
850 .save @{d8, d9, d10@}
851 fstmdx sp!, @{d8, d9, d10@}
852 @exdent @emph{iWMMXt registers}
853 .save @{wr10, wr11@}
854 wstrd wr11, [sp, #-8]!
855 wstrd wr10, [sp, #-8]!
856 or
857 .save wr11
858 wstrd wr11, [sp, #-8]!
859 .save wr10
860 wstrd wr10, [sp, #-8]!
861 @end smallexample
862
863 @anchor{arm_setfp}
864 @cindex @code{.setfp} directive, ARM
865 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
866 Make all unwinder annotations relative to a frame pointer. Without this
867 the unwinder will use offsets from the stack pointer.
868
869 The syntax of this directive is the same as the @code{add} or @code{mov}
870 instruction used to set the frame pointer. @var{spreg} must be either
871 @code{sp} or mentioned in a previous @code{.movsp} directive.
872
873 @smallexample
874 .movsp ip
875 mov ip, sp
876 @dots{}
877 .setfp fp, ip, #4
878 add fp, ip, #4
879 @end smallexample
880
881 @cindex @code{.secrel32} directive, ARM
882 @item .secrel32 @var{expression} [, @var{expression}]*
883 This directive emits relocations that evaluate to the section-relative
884 offset of each expression's symbol. This directive is only supported
885 for PE targets.
886
887 @cindex @code{.syntax} directive, ARM
888 @item .syntax [@code{unified} | @code{divided}]
889 This directive sets the Instruction Set Syntax as described in the
890 @ref{ARM-Instruction-Set} section.
891
892 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
893
894 @cindex @code{.thumb} directive, ARM
895 @item .thumb
896 This performs the same action as @var{.code 16}.
897
898 @cindex @code{.thumb_func} directive, ARM
899 @item .thumb_func
900 This directive specifies that the following symbol is the name of a
901 Thumb encoded function. This information is necessary in order to allow
902 the assembler and linker to generate correct code for interworking
903 between Arm and Thumb instructions and should be used even if
904 interworking is not going to be performed. The presence of this
905 directive also implies @code{.thumb}
906
907 This directive is not neccessary when generating EABI objects. On these
908 targets the encoding is implicit when generating Thumb code.
909
910 @cindex @code{.thumb_set} directive, ARM
911 @item .thumb_set
912 This performs the equivalent of a @code{.set} directive in that it
913 creates a symbol which is an alias for another symbol (possibly not yet
914 defined). This directive also has the added property in that it marks
915 the aliased symbol as being a thumb function entry point, in the same
916 way that the @code{.thumb_func} directive does.
917
918 @cindex @code{.tlsdescseq} directive, ARM
919 @item .tlsdescseq @var{tls-variable}
920 This directive is used to annotate parts of an inlined TLS descriptor
921 trampoline. Normally the trampoline is provided by the linker, and
922 this directive is not needed.
923
924 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
925
926 @cindex @code{.unreq} directive, ARM
927 @item .unreq @var{alias-name}
928 This undefines a register alias which was previously defined using the
929 @code{req}, @code{dn} or @code{qn} directives. For example:
930
931 @smallexample
932 foo .req r0
933 .unreq foo
934 @end smallexample
935
936 An error occurs if the name is undefined. Note - this pseudo op can
937 be used to delete builtin in register name aliases (eg 'r0'). This
938 should only be done if it is really necessary.
939
940 @cindex @code{.unwind_raw} directive, ARM
941 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
942 Insert one of more arbitary unwind opcode bytes, which are known to adjust
943 the stack pointer by @var{offset} bytes.
944
945 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
946 @code{.save @{r0@}}
947
948 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
949
950 @cindex @code{.vsave} directive, ARM
951 @item .vsave @var{vfp-reglist}
952 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
953 using FLDMD. Also works for VFPv3 registers
954 that are to be restored using VLDM.
955 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
956 instruction.
957
958 @smallexample
959 @exdent @emph{VFP registers}
960 .vsave @{d8, d9, d10@}
961 fstmdd sp!, @{d8, d9, d10@}
962 @exdent @emph{VFPv3 registers}
963 .vsave @{d15, d16, d17@}
964 vstm sp!, @{d15, d16, d17@}
965 @end smallexample
966
967 Since FLDMX and FSTMX are now deprecated, this directive should be
968 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
969
970 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
971 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
972 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
973 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
974
975 @end table
976
977 @node ARM Opcodes
978 @section Opcodes
979
980 @cindex ARM opcodes
981 @cindex opcodes for ARM
982 @code{@value{AS}} implements all the standard ARM opcodes. It also
983 implements several pseudo opcodes, including several synthetic load
984 instructions.
985
986 @table @code
987
988 @cindex @code{NOP} pseudo op, ARM
989 @item NOP
990 @smallexample
991 nop
992 @end smallexample
993
994 This pseudo op will always evaluate to a legal ARM instruction that does
995 nothing. Currently it will evaluate to MOV r0, r0.
996
997 @cindex @code{LDR reg,=<label>} pseudo op, ARM
998 @item LDR
999 @smallexample
1000 ldr <register> , = <expression>
1001 @end smallexample
1002
1003 If expression evaluates to a numeric constant then a MOV or MVN
1004 instruction will be used in place of the LDR instruction, if the
1005 constant can be generated by either of these instructions. Otherwise
1006 the constant will be placed into the nearest literal pool (if it not
1007 already there) and a PC relative LDR instruction will be generated.
1008
1009 @cindex @code{ADR reg,<label>} pseudo op, ARM
1010 @item ADR
1011 @smallexample
1012 adr <register> <label>
1013 @end smallexample
1014
1015 This instruction will load the address of @var{label} into the indicated
1016 register. The instruction will evaluate to a PC relative ADD or SUB
1017 instruction depending upon where the label is located. If the label is
1018 out of range, or if it is not defined in the same file (and section) as
1019 the ADR instruction, then an error will be generated. This instruction
1020 will not make use of the literal pool.
1021
1022 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1023 @item ADRL
1024 @smallexample
1025 adrl <register> <label>
1026 @end smallexample
1027
1028 This instruction will load the address of @var{label} into the indicated
1029 register. The instruction will evaluate to one or two PC relative ADD
1030 or SUB instructions depending upon where the label is located. If a
1031 second instruction is not needed a NOP instruction will be generated in
1032 its place, so that this instruction is always 8 bytes long.
1033
1034 If the label is out of range, or if it is not defined in the same file
1035 (and section) as the ADRL instruction, then an error will be generated.
1036 This instruction will not make use of the literal pool.
1037
1038 @end table
1039
1040 For information on the ARM or Thumb instruction sets, see @cite{ARM
1041 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1042 Ltd.
1043
1044 @node ARM Mapping Symbols
1045 @section Mapping Symbols
1046
1047 The ARM ELF specification requires that special symbols be inserted
1048 into object files to mark certain features:
1049
1050 @table @code
1051
1052 @cindex @code{$a}
1053 @item $a
1054 At the start of a region of code containing ARM instructions.
1055
1056 @cindex @code{$t}
1057 @item $t
1058 At the start of a region of code containing THUMB instructions.
1059
1060 @cindex @code{$d}
1061 @item $d
1062 At the start of a region of data.
1063
1064 @end table
1065
1066 The assembler will automatically insert these symbols for you - there
1067 is no need to code them yourself. Support for tagging symbols ($b,
1068 $f, $p and $m) which is also mentioned in the current ARM ELF
1069 specification is not implemented. This is because they have been
1070 dropped from the new EABI and so tools cannot rely upon their
1071 presence.
1072
1073 @node ARM Unwinding Tutorial
1074 @section Unwinding
1075
1076 The ABI for the ARM Architecture specifies a standard format for
1077 exception unwind information. This information is used when an
1078 exception is thrown to determine where control should be transferred.
1079 In particular, the unwind information is used to determine which
1080 function called the function that threw the exception, and which
1081 function called that one, and so forth. This information is also used
1082 to restore the values of callee-saved registers in the function
1083 catching the exception.
1084
1085 If you are writing functions in assembly code, and those functions
1086 call other functions that throw exceptions, you must use assembly
1087 pseudo ops to ensure that appropriate exception unwind information is
1088 generated. Otherwise, if one of the functions called by your assembly
1089 code throws an exception, the run-time library will be unable to
1090 unwind the stack through your assembly code and your program will not
1091 behave correctly.
1092
1093 To illustrate the use of these pseudo ops, we will examine the code
1094 that G++ generates for the following C++ input:
1095
1096 @verbatim
1097 void callee (int *);
1098
1099 int
1100 caller ()
1101 {
1102 int i;
1103 callee (&i);
1104 return i;
1105 }
1106 @end verbatim
1107
1108 This example does not show how to throw or catch an exception from
1109 assembly code. That is a much more complex operation and should
1110 always be done in a high-level language, such as C++, that directly
1111 supports exceptions.
1112
1113 The code generated by one particular version of G++ when compiling the
1114 example above is:
1115
1116 @verbatim
1117 _Z6callerv:
1118 .fnstart
1119 .LFB2:
1120 @ Function supports interworking.
1121 @ args = 0, pretend = 0, frame = 8
1122 @ frame_needed = 1, uses_anonymous_args = 0
1123 stmfd sp!, {fp, lr}
1124 .save {fp, lr}
1125 .LCFI0:
1126 .setfp fp, sp, #4
1127 add fp, sp, #4
1128 .LCFI1:
1129 .pad #8
1130 sub sp, sp, #8
1131 .LCFI2:
1132 sub r3, fp, #8
1133 mov r0, r3
1134 bl _Z6calleePi
1135 ldr r3, [fp, #-8]
1136 mov r0, r3
1137 sub sp, fp, #4
1138 ldmfd sp!, {fp, lr}
1139 bx lr
1140 .LFE2:
1141 .fnend
1142 @end verbatim
1143
1144 Of course, the sequence of instructions varies based on the options
1145 you pass to GCC and on the version of GCC in use. The exact
1146 instructions are not important since we are focusing on the pseudo ops
1147 that are used to generate unwind information.
1148
1149 An important assumption made by the unwinder is that the stack frame
1150 does not change during the body of the function. In particular, since
1151 we assume that the assembly code does not itself throw an exception,
1152 the only point where an exception can be thrown is from a call, such
1153 as the @code{bl} instruction above. At each call site, the same saved
1154 registers (including @code{lr}, which indicates the return address)
1155 must be located in the same locations relative to the frame pointer.
1156
1157 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1158 op appears immediately before the first instruction of the function
1159 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1160 op appears immediately after the last instruction of the function.
1161 These pseudo ops specify the range of the function.
1162
1163 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1164 @code{.pad}) matters; their exact locations are irrelevant. In the
1165 example above, the compiler emits the pseudo ops with particular
1166 instructions. That makes it easier to understand the code, but it is
1167 not required for correctness. It would work just as well to emit all
1168 of the pseudo ops other than @code{.fnend} in the same order, but
1169 immediately after @code{.fnstart}.
1170
1171 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1172 indicates registers that have been saved to the stack so that they can
1173 be restored before the function returns. The argument to the
1174 @code{.save} pseudo op is a list of registers to save. If a register
1175 is ``callee-saved'' (as specified by the ABI) and is modified by the
1176 function you are writing, then your code must save the value before it
1177 is modified and restore the original value before the function
1178 returns. If an exception is thrown, the run-time library restores the
1179 values of these registers from their locations on the stack before
1180 returning control to the exception handler. (Of course, if an
1181 exception is not thrown, the function that contains the @code{.save}
1182 pseudo op restores these registers in the function epilogue, as is
1183 done with the @code{ldmfd} instruction above.)
1184
1185 You do not have to save callee-saved registers at the very beginning
1186 of the function and you do not need to use the @code{.save} pseudo op
1187 immediately following the point at which the registers are saved.
1188 However, if you modify a callee-saved register, you must save it on
1189 the stack before modifying it and before calling any functions which
1190 might throw an exception. And, you must use the @code{.save} pseudo
1191 op to indicate that you have done so.
1192
1193 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1194 modification of the stack pointer that does not save any registers.
1195 The argument is the number of bytes (in decimal) that are subtracted
1196 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1197 subtracting from the stack pointer increases the size of the stack.)
1198
1199 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1200 indicates the register that contains the frame pointer. The first
1201 argument is the register that is set, which is typically @code{fp}.
1202 The second argument indicates the register from which the frame
1203 pointer takes its value. The third argument, if present, is the value
1204 (in decimal) added to the register specified by the second argument to
1205 compute the value of the frame pointer. You should not modify the
1206 frame pointer in the body of the function.
1207
1208 If you do not use a frame pointer, then you should not use the
1209 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1210 should avoid modifying the stack pointer outside of the function
1211 prologue. Otherwise, the run-time library will be unable to find
1212 saved registers when it is unwinding the stack.
1213
1214 The pseudo ops described above are sufficient for writing assembly
1215 code that calls functions which may throw exceptions. If you need to
1216 know more about the object-file format used to represent unwind
1217 information, you may consult the @cite{Exception Handling ABI for the
1218 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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