1 @c Copyright (C) 1996-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
134 @code{cortex-m0plus},
137 @code{marvell-whitney},
140 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
141 @code{i80200} (Intel XScale processor)
142 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
145 The special name @code{all} may be used to allow the
146 assembler to accept instructions valid for any ARM processor.
148 In addition to the basic instruction set, the assembler can be told to
149 accept various extension mnemonics that extend the processor using the
150 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
151 is equivalent to specifying @code{-mcpu=ep9312}.
153 Multiple extensions may be specified, separated by a @code{+}. The
154 extensions should be specified in ascending alphabetical order.
156 Some extensions may be restricted to particular architectures; this is
157 documented in the list of extensions below.
159 Extension mnemonics may also be removed from those the assembler accepts.
160 This is done be prepending @code{no} to the option that adds the extension.
161 Extensions that are removed should be listed after all extensions which have
162 been added, again in ascending alphabetical order. For example,
163 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
166 The following extensions are currently supported:
168 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
169 @code{fp} (Floating Point Extensions for v8-A architecture),
170 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
175 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
177 @code{os} (Operating System for v6M architecture),
178 @code{sec} (Security Extensions for v6K and v7-A architectures),
179 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
180 @code{virt} (Virtualization Extensions for v7-A architecture, implies
182 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
183 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
188 @cindex @code{-march=} command line option, ARM
189 @item -march=@var{architecture}[+@var{extension}@dots{}]
190 This option specifies the target architecture. The assembler will issue
191 an error message if an attempt is made to assemble an instruction which
192 will not execute on the target architecture. The following architecture
193 names are recognized:
227 If both @code{-mcpu} and
228 @code{-march} are specified, the assembler will use
229 the setting for @code{-mcpu}.
231 The architecture option can be extended with the same instruction set
232 extension options as the @code{-mcpu} option.
234 @cindex @code{-mfpu=} command line option, ARM
235 @item -mfpu=@var{floating-point-format}
237 This option specifies the floating point format to assemble for. The
238 assembler will issue an error message if an attempt is made to assemble
239 an instruction which will not execute on the target floating point unit.
240 The following format options are recognized:
260 @code{vfpv3-d16-fp16},
275 @code{neon-fp-armv8},
276 @code{crypto-neon-fp-armv8}.
278 @code{neon-fp-armv8-1},
280 In addition to determining which instructions are assembled, this option
281 also affects the way in which the @code{.double} assembler directive behaves
282 when assembling little-endian code.
284 The default is dependent on the processor selected. For Architecture 5 or
285 later, the default is to assembler for VFP instructions; for earlier
286 architectures the default is to assemble for FPA instructions.
288 @cindex @code{-mthumb} command line option, ARM
290 This option specifies that the assembler should start assembling Thumb
291 instructions; that is, it should behave as though the file starts with a
292 @code{.code 16} directive.
294 @cindex @code{-mthumb-interwork} command line option, ARM
295 @item -mthumb-interwork
296 This option specifies that the output generated by the assembler should
297 be marked as supporting interworking.
299 @cindex @code{-mimplicit-it} command line option, ARM
300 @item -mimplicit-it=never
301 @itemx -mimplicit-it=always
302 @itemx -mimplicit-it=arm
303 @itemx -mimplicit-it=thumb
304 The @code{-mimplicit-it} option controls the behavior of the assembler when
305 conditional instructions are not enclosed in IT blocks.
306 There are four possible behaviors.
307 If @code{never} is specified, such constructs cause a warning in ARM
308 code and an error in Thumb-2 code.
309 If @code{always} is specified, such constructs are accepted in both
310 ARM and Thumb-2 code, where the IT instruction is added implicitly.
311 If @code{arm} is specified, such constructs are accepted in ARM code
312 and cause an error in Thumb-2 code.
313 If @code{thumb} is specified, such constructs cause a warning in ARM
314 code and are accepted in Thumb-2 code. If you omit this option, the
315 behavior is equivalent to @code{-mimplicit-it=arm}.
317 @cindex @code{-mapcs-26} command line option, ARM
318 @cindex @code{-mapcs-32} command line option, ARM
321 These options specify that the output generated by the assembler should
322 be marked as supporting the indicated version of the Arm Procedure.
325 @cindex @code{-matpcs} command line option, ARM
327 This option specifies that the output generated by the assembler should
328 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
329 enabled this option will cause the assembler to create an empty
330 debugging section in the object file called .arm.atpcs. Debuggers can
331 use this to determine the ABI being used by.
333 @cindex @code{-mapcs-float} command line option, ARM
335 This indicates the floating point variant of the APCS should be
336 used. In this variant floating point arguments are passed in FP
337 registers rather than integer registers.
339 @cindex @code{-mapcs-reentrant} command line option, ARM
340 @item -mapcs-reentrant
341 This indicates that the reentrant variant of the APCS should be used.
342 This variant supports position independent code.
344 @cindex @code{-mfloat-abi=} command line option, ARM
345 @item -mfloat-abi=@var{abi}
346 This option specifies that the output generated by the assembler should be
347 marked as using specified floating point ABI.
348 The following values are recognized:
354 @cindex @code{-eabi=} command line option, ARM
355 @item -meabi=@var{ver}
356 This option specifies which EABI version the produced object files should
358 The following values are recognized:
364 @cindex @code{-EB} command line option, ARM
366 This option specifies that the output generated by the assembler should
367 be marked as being encoded for a big-endian processor.
369 Note: If a program is being built for a system with big-endian data
370 and little-endian instructions then it should be assembled with the
371 @option{-EB} option, (all of it, code and data) and then linked with
372 the @option{--be8} option. This will reverse the endianness of the
373 instructions back to little-endian, but leave the data as big-endian.
375 @cindex @code{-EL} command line option, ARM
377 This option specifies that the output generated by the assembler should
378 be marked as being encoded for a little-endian processor.
380 @cindex @code{-k} command line option, ARM
381 @cindex PIC code generation for ARM
383 This option specifies that the output of the assembler should be marked
384 as position-independent code (PIC).
386 @cindex @code{--fix-v4bx} command line option, ARM
388 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
389 the linker option of the same name.
391 @cindex @code{-mwarn-deprecated} command line option, ARM
392 @item -mwarn-deprecated
393 @itemx -mno-warn-deprecated
394 Enable or disable warnings about using deprecated options or
395 features. The default is to warn.
397 @cindex @code{-mccs} command line option, ARM
399 Turns on CodeComposer Studio assembly syntax compatibility mode.
401 @cindex @code{-mwarn-syms} command line option, ARM
403 @itemx -mno-warn-syms
404 Enable or disable warnings about symbols that match the names of ARM
405 instructions. The default is to warn.
413 * ARM-Instruction-Set:: Instruction Set
414 * ARM-Chars:: Special Characters
415 * ARM-Regs:: Register Names
416 * ARM-Relocations:: Relocations
417 * ARM-Neon-Alignment:: NEON Alignment Specifiers
420 @node ARM-Instruction-Set
421 @subsection Instruction Set Syntax
422 Two slightly different syntaxes are support for ARM and THUMB
423 instructions. The default, @code{divided}, uses the old style where
424 ARM and THUMB instructions had their own, separate syntaxes. The new,
425 @code{unified} syntax, which can be selected via the @code{.syntax}
426 directive, and has the following main features:
430 Immediate operands do not require a @code{#} prefix.
433 The @code{IT} instruction may appear, and if it does it is validated
434 against subsequent conditional affixes. In ARM mode it does not
435 generate machine code, in THUMB mode it does.
438 For ARM instructions the conditional affixes always appear at the end
439 of the instruction. For THUMB instructions conditional affixes can be
440 used, but only inside the scope of an @code{IT} instruction.
443 All of the instructions new to the V6T2 architecture (and later) are
444 available. (Only a few such instructions can be written in the
445 @code{divided} syntax).
448 The @code{.N} and @code{.W} suffixes are recognized and honored.
451 All instructions set the flags if and only if they have an @code{s}
456 @subsection Special Characters
458 @cindex line comment character, ARM
459 @cindex ARM line comment character
460 The presence of a @samp{@@} anywhere on a line indicates the start of
461 a comment that extends to the end of that line.
463 If a @samp{#} appears as the first character of a line then the whole
464 line is treated as a comment, but in this case the line could also be
465 a logical line number directive (@pxref{Comments}) or a preprocessor
466 control command (@pxref{Preprocessing}).
468 @cindex line separator, ARM
469 @cindex statement separator, ARM
470 @cindex ARM line separator
471 The @samp{;} character can be used instead of a newline to separate
474 @cindex immediate character, ARM
475 @cindex ARM immediate character
476 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
478 @cindex identifiers, ARM
479 @cindex ARM identifiers
480 *TODO* Explain about /data modifier on symbols.
483 @subsection Register Names
485 @cindex ARM register names
486 @cindex register names, ARM
487 *TODO* Explain about ARM register naming, and the predefined names.
489 @node ARM-Relocations
490 @subsection ARM relocation generation
492 @cindex data relocations, ARM
493 @cindex ARM data relocations
494 Specific data relocations can be generated by putting the relocation name
495 in parentheses after the symbol name. For example:
501 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
503 The following relocations are supported:
519 For compatibility with older toolchains the assembler also accepts
520 @code{(PLT)} after branch targets. On legacy targets this will
521 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
522 targets it will encode either the @samp{R_ARM_CALL} or
523 @samp{R_ARM_JUMP24} relocation, as appropriate.
525 @cindex MOVW and MOVT relocations, ARM
526 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
527 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
528 respectively. For example to load the 32-bit address of foo into r0:
531 MOVW r0, #:lower16:foo
532 MOVT r0, #:upper16:foo
535 @node ARM-Neon-Alignment
536 @subsection NEON Alignment Specifiers
538 @cindex alignment for NEON instructions
539 Some NEON load/store instructions allow an optional address
541 The ARM documentation specifies that this is indicated by
542 @samp{@@ @var{align}}. However GAS already interprets
543 the @samp{@@} character as a "line comment" start,
544 so @samp{: @var{align}} is used instead. For example:
547 vld1.8 @{q0@}, [r0, :128]
550 @node ARM Floating Point
551 @section Floating Point
553 @cindex floating point, ARM (@sc{ieee})
554 @cindex ARM floating point (@sc{ieee})
555 The ARM family uses @sc{ieee} floating-point numbers.
558 @section ARM Machine Directives
560 @cindex machine directives, ARM
561 @cindex ARM machine directives
564 @c AAAAAAAAAAAAAAAAAAAAAAAAA
566 @cindex @code{.2byte} directive, ARM
567 @cindex @code{.4byte} directive, ARM
568 @cindex @code{.8byte} directive, ARM
569 @item .2byte @var{expression} [, @var{expression}]*
570 @itemx .4byte @var{expression} [, @var{expression}]*
571 @itemx .8byte @var{expression} [, @var{expression}]*
572 These directives write 2, 4 or 8 byte values to the output section.
574 @cindex @code{.align} directive, ARM
575 @item .align @var{expression} [, @var{expression}]
576 This is the generic @var{.align} directive. For the ARM however if the
577 first argument is zero (ie no alignment is needed) the assembler will
578 behave as if the argument had been 2 (ie pad to the next four byte
579 boundary). This is for compatibility with ARM's own assembler.
581 @cindex @code{.arch} directive, ARM
582 @item .arch @var{name}
583 Select the target architecture. Valid values for @var{name} are the same as
584 for the @option{-march} commandline option.
586 Specifying @code{.arch} clears any previously selected architecture
589 @cindex @code{.arch_extension} directive, ARM
590 @item .arch_extension @var{name}
591 Add or remove an architecture extension to the target architecture. Valid
592 values for @var{name} are the same as those accepted as architectural
593 extensions by the @option{-mcpu} commandline option.
595 @code{.arch_extension} may be used multiple times to add or remove extensions
596 incrementally to the architecture being compiled for.
598 @cindex @code{.arm} directive, ARM
600 This performs the same action as @var{.code 32}.
602 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
604 @cindex @code{.bss} directive, ARM
606 This directive switches to the @code{.bss} section.
608 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
610 @cindex @code{.cantunwind} directive, ARM
612 Prevents unwinding through the current function. No personality routine
613 or exception table data is required or permitted.
615 @cindex @code{.code} directive, ARM
616 @item .code @code{[16|32]}
617 This directive selects the instruction set being generated. The value 16
618 selects Thumb, with the value 32 selecting ARM.
620 @cindex @code{.cpu} directive, ARM
621 @item .cpu @var{name}
622 Select the target processor. Valid values for @var{name} are the same as
623 for the @option{-mcpu} commandline option.
625 Specifying @code{.cpu} clears any previously selected architecture
628 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
630 @cindex @code{.dn} and @code{.qn} directives, ARM
631 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
632 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
634 The @code{dn} and @code{qn} directives are used to create typed
635 and/or indexed register aliases for use in Advanced SIMD Extension
636 (Neon) instructions. The former should be used to create aliases
637 of double-precision registers, and the latter to create aliases of
638 quad-precision registers.
640 If these directives are used to create typed aliases, those aliases can
641 be used in Neon instructions instead of writing types after the mnemonic
642 or after each operand. For example:
651 This is equivalent to writing the following:
657 Aliases created using @code{dn} or @code{qn} can be destroyed using
660 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
662 @cindex @code{.eabi_attribute} directive, ARM
663 @item .eabi_attribute @var{tag}, @var{value}
664 Set the EABI object attribute @var{tag} to @var{value}.
666 The @var{tag} is either an attribute number, or one of the following:
667 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
668 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
669 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
670 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
671 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
672 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
673 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
674 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
675 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
676 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
677 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
678 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
679 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
680 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
681 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
682 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
683 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
684 @code{Tag_conformance}, @code{Tag_T2EE_use},
685 @code{Tag_Virtualization_use}
687 The @var{value} is either a @code{number}, @code{"string"}, or
688 @code{number, "string"} depending on the tag.
690 Note - the following legacy values are also accepted by @var{tag}:
691 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
692 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
694 @cindex @code{.even} directive, ARM
696 This directive aligns to an even-numbered address.
698 @cindex @code{.extend} directive, ARM
699 @cindex @code{.ldouble} directive, ARM
700 @item .extend @var{expression} [, @var{expression}]*
701 @itemx .ldouble @var{expression} [, @var{expression}]*
702 These directives write 12byte long double floating-point values to the
703 output section. These are not compatible with current ARM processors
706 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
709 @cindex @code{.fnend} directive, ARM
711 Marks the end of a function with an unwind table entry. The unwind index
712 table entry is created when this directive is processed.
714 If no personality routine has been specified then standard personality
715 routine 0 or 1 will be used, depending on the number of unwind opcodes
719 @cindex @code{.fnstart} directive, ARM
721 Marks the start of a function with an unwind table entry.
723 @cindex @code{.force_thumb} directive, ARM
725 This directive forces the selection of Thumb instructions, even if the
726 target processor does not support those instructions
728 @cindex @code{.fpu} directive, ARM
729 @item .fpu @var{name}
730 Select the floating-point unit to assemble for. Valid values for @var{name}
731 are the same as for the @option{-mfpu} commandline option.
733 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
734 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
736 @cindex @code{.handlerdata} directive, ARM
738 Marks the end of the current function, and the start of the exception table
739 entry for that function. Anything between this directive and the
740 @code{.fnend} directive will be added to the exception table entry.
742 Must be preceded by a @code{.personality} or @code{.personalityindex}
745 @c IIIIIIIIIIIIIIIIIIIIIIIIII
747 @cindex @code{.inst} directive, ARM
748 @item .inst @var{opcode} [ , @dots{} ]
749 @itemx .inst.n @var{opcode} [ , @dots{} ]
750 @itemx .inst.w @var{opcode} [ , @dots{} ]
751 Generates the instruction corresponding to the numerical value @var{opcode}.
752 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
753 specified explicitly, overriding the normal encoding rules.
755 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
756 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
757 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
759 @item .ldouble @var{expression} [, @var{expression}]*
762 @cindex @code{.ltorg} directive, ARM
764 This directive causes the current contents of the literal pool to be
765 dumped into the current section (which is assumed to be the .text
766 section) at the current location (aligned to a word boundary).
767 @code{GAS} maintains a separate literal pool for each section and each
768 sub-section. The @code{.ltorg} directive will only affect the literal
769 pool of the current section and sub-section. At the end of assembly
770 all remaining, un-empty literal pools will automatically be dumped.
772 Note - older versions of @code{GAS} would dump the current literal
773 pool any time a section change occurred. This is no longer done, since
774 it prevents accurate control of the placement of literal pools.
776 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
778 @cindex @code{.movsp} directive, ARM
779 @item .movsp @var{reg} [, #@var{offset}]
780 Tell the unwinder that @var{reg} contains an offset from the current
781 stack pointer. If @var{offset} is not specified then it is assumed to be
784 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
785 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
787 @cindex @code{.object_arch} directive, ARM
788 @item .object_arch @var{name}
789 Override the architecture recorded in the EABI object attribute section.
790 Valid values for @var{name} are the same as for the @code{.arch} directive.
791 Typically this is useful when code uses runtime detection of CPU features.
793 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
795 @cindex @code{.packed} directive, ARM
796 @item .packed @var{expression} [, @var{expression}]*
797 This directive writes 12-byte packed floating-point values to the
798 output section. These are not compatible with current ARM processors
802 @cindex @code{.pad} directive, ARM
803 @item .pad #@var{count}
804 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
805 A positive value indicates the function prologue allocated stack space by
806 decrementing the stack pointer.
808 @cindex @code{.personality} directive, ARM
809 @item .personality @var{name}
810 Sets the personality routine for the current function to @var{name}.
812 @cindex @code{.personalityindex} directive, ARM
813 @item .personalityindex @var{index}
814 Sets the personality routine for the current function to the EABI standard
815 routine number @var{index}
817 @cindex @code{.pool} directive, ARM
819 This is a synonym for .ltorg.
821 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
822 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
824 @cindex @code{.req} directive, ARM
825 @item @var{name} .req @var{register name}
826 This creates an alias for @var{register name} called @var{name}. For
833 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
836 @cindex @code{.save} directive, ARM
837 @item .save @var{reglist}
838 Generate unwinder annotations to restore the registers in @var{reglist}.
839 The format of @var{reglist} is the same as the corresponding store-multiple
843 @exdent @emph{core registers}
844 .save @{r4, r5, r6, lr@}
845 stmfd sp!, @{r4, r5, r6, lr@}
846 @exdent @emph{FPA registers}
849 @exdent @emph{VFP registers}
850 .save @{d8, d9, d10@}
851 fstmdx sp!, @{d8, d9, d10@}
852 @exdent @emph{iWMMXt registers}
854 wstrd wr11, [sp, #-8]!
855 wstrd wr10, [sp, #-8]!
858 wstrd wr11, [sp, #-8]!
860 wstrd wr10, [sp, #-8]!
864 @cindex @code{.setfp} directive, ARM
865 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
866 Make all unwinder annotations relative to a frame pointer. Without this
867 the unwinder will use offsets from the stack pointer.
869 The syntax of this directive is the same as the @code{add} or @code{mov}
870 instruction used to set the frame pointer. @var{spreg} must be either
871 @code{sp} or mentioned in a previous @code{.movsp} directive.
881 @cindex @code{.secrel32} directive, ARM
882 @item .secrel32 @var{expression} [, @var{expression}]*
883 This directive emits relocations that evaluate to the section-relative
884 offset of each expression's symbol. This directive is only supported
887 @cindex @code{.syntax} directive, ARM
888 @item .syntax [@code{unified} | @code{divided}]
889 This directive sets the Instruction Set Syntax as described in the
890 @ref{ARM-Instruction-Set} section.
892 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
894 @cindex @code{.thumb} directive, ARM
896 This performs the same action as @var{.code 16}.
898 @cindex @code{.thumb_func} directive, ARM
900 This directive specifies that the following symbol is the name of a
901 Thumb encoded function. This information is necessary in order to allow
902 the assembler and linker to generate correct code for interworking
903 between Arm and Thumb instructions and should be used even if
904 interworking is not going to be performed. The presence of this
905 directive also implies @code{.thumb}
907 This directive is not neccessary when generating EABI objects. On these
908 targets the encoding is implicit when generating Thumb code.
910 @cindex @code{.thumb_set} directive, ARM
912 This performs the equivalent of a @code{.set} directive in that it
913 creates a symbol which is an alias for another symbol (possibly not yet
914 defined). This directive also has the added property in that it marks
915 the aliased symbol as being a thumb function entry point, in the same
916 way that the @code{.thumb_func} directive does.
918 @cindex @code{.tlsdescseq} directive, ARM
919 @item .tlsdescseq @var{tls-variable}
920 This directive is used to annotate parts of an inlined TLS descriptor
921 trampoline. Normally the trampoline is provided by the linker, and
922 this directive is not needed.
924 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
926 @cindex @code{.unreq} directive, ARM
927 @item .unreq @var{alias-name}
928 This undefines a register alias which was previously defined using the
929 @code{req}, @code{dn} or @code{qn} directives. For example:
936 An error occurs if the name is undefined. Note - this pseudo op can
937 be used to delete builtin in register name aliases (eg 'r0'). This
938 should only be done if it is really necessary.
940 @cindex @code{.unwind_raw} directive, ARM
941 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
942 Insert one of more arbitary unwind opcode bytes, which are known to adjust
943 the stack pointer by @var{offset} bytes.
945 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
948 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
950 @cindex @code{.vsave} directive, ARM
951 @item .vsave @var{vfp-reglist}
952 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
953 using FLDMD. Also works for VFPv3 registers
954 that are to be restored using VLDM.
955 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
959 @exdent @emph{VFP registers}
960 .vsave @{d8, d9, d10@}
961 fstmdd sp!, @{d8, d9, d10@}
962 @exdent @emph{VFPv3 registers}
963 .vsave @{d15, d16, d17@}
964 vstm sp!, @{d15, d16, d17@}
967 Since FLDMX and FSTMX are now deprecated, this directive should be
968 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
970 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
971 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
972 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
973 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
981 @cindex opcodes for ARM
982 @code{@value{AS}} implements all the standard ARM opcodes. It also
983 implements several pseudo opcodes, including several synthetic load
988 @cindex @code{NOP} pseudo op, ARM
994 This pseudo op will always evaluate to a legal ARM instruction that does
995 nothing. Currently it will evaluate to MOV r0, r0.
997 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1000 ldr <register> , = <expression>
1003 If expression evaluates to a numeric constant then a MOV or MVN
1004 instruction will be used in place of the LDR instruction, if the
1005 constant can be generated by either of these instructions. Otherwise
1006 the constant will be placed into the nearest literal pool (if it not
1007 already there) and a PC relative LDR instruction will be generated.
1009 @cindex @code{ADR reg,<label>} pseudo op, ARM
1012 adr <register> <label>
1015 This instruction will load the address of @var{label} into the indicated
1016 register. The instruction will evaluate to a PC relative ADD or SUB
1017 instruction depending upon where the label is located. If the label is
1018 out of range, or if it is not defined in the same file (and section) as
1019 the ADR instruction, then an error will be generated. This instruction
1020 will not make use of the literal pool.
1022 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1025 adrl <register> <label>
1028 This instruction will load the address of @var{label} into the indicated
1029 register. The instruction will evaluate to one or two PC relative ADD
1030 or SUB instructions depending upon where the label is located. If a
1031 second instruction is not needed a NOP instruction will be generated in
1032 its place, so that this instruction is always 8 bytes long.
1034 If the label is out of range, or if it is not defined in the same file
1035 (and section) as the ADRL instruction, then an error will be generated.
1036 This instruction will not make use of the literal pool.
1040 For information on the ARM or Thumb instruction sets, see @cite{ARM
1041 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1044 @node ARM Mapping Symbols
1045 @section Mapping Symbols
1047 The ARM ELF specification requires that special symbols be inserted
1048 into object files to mark certain features:
1054 At the start of a region of code containing ARM instructions.
1058 At the start of a region of code containing THUMB instructions.
1062 At the start of a region of data.
1066 The assembler will automatically insert these symbols for you - there
1067 is no need to code them yourself. Support for tagging symbols ($b,
1068 $f, $p and $m) which is also mentioned in the current ARM ELF
1069 specification is not implemented. This is because they have been
1070 dropped from the new EABI and so tools cannot rely upon their
1073 @node ARM Unwinding Tutorial
1076 The ABI for the ARM Architecture specifies a standard format for
1077 exception unwind information. This information is used when an
1078 exception is thrown to determine where control should be transferred.
1079 In particular, the unwind information is used to determine which
1080 function called the function that threw the exception, and which
1081 function called that one, and so forth. This information is also used
1082 to restore the values of callee-saved registers in the function
1083 catching the exception.
1085 If you are writing functions in assembly code, and those functions
1086 call other functions that throw exceptions, you must use assembly
1087 pseudo ops to ensure that appropriate exception unwind information is
1088 generated. Otherwise, if one of the functions called by your assembly
1089 code throws an exception, the run-time library will be unable to
1090 unwind the stack through your assembly code and your program will not
1093 To illustrate the use of these pseudo ops, we will examine the code
1094 that G++ generates for the following C++ input:
1097 void callee (int *);
1108 This example does not show how to throw or catch an exception from
1109 assembly code. That is a much more complex operation and should
1110 always be done in a high-level language, such as C++, that directly
1111 supports exceptions.
1113 The code generated by one particular version of G++ when compiling the
1120 @ Function supports interworking.
1121 @ args = 0, pretend = 0, frame = 8
1122 @ frame_needed = 1, uses_anonymous_args = 0
1144 Of course, the sequence of instructions varies based on the options
1145 you pass to GCC and on the version of GCC in use. The exact
1146 instructions are not important since we are focusing on the pseudo ops
1147 that are used to generate unwind information.
1149 An important assumption made by the unwinder is that the stack frame
1150 does not change during the body of the function. In particular, since
1151 we assume that the assembly code does not itself throw an exception,
1152 the only point where an exception can be thrown is from a call, such
1153 as the @code{bl} instruction above. At each call site, the same saved
1154 registers (including @code{lr}, which indicates the return address)
1155 must be located in the same locations relative to the frame pointer.
1157 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1158 op appears immediately before the first instruction of the function
1159 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1160 op appears immediately after the last instruction of the function.
1161 These pseudo ops specify the range of the function.
1163 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1164 @code{.pad}) matters; their exact locations are irrelevant. In the
1165 example above, the compiler emits the pseudo ops with particular
1166 instructions. That makes it easier to understand the code, but it is
1167 not required for correctness. It would work just as well to emit all
1168 of the pseudo ops other than @code{.fnend} in the same order, but
1169 immediately after @code{.fnstart}.
1171 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1172 indicates registers that have been saved to the stack so that they can
1173 be restored before the function returns. The argument to the
1174 @code{.save} pseudo op is a list of registers to save. If a register
1175 is ``callee-saved'' (as specified by the ABI) and is modified by the
1176 function you are writing, then your code must save the value before it
1177 is modified and restore the original value before the function
1178 returns. If an exception is thrown, the run-time library restores the
1179 values of these registers from their locations on the stack before
1180 returning control to the exception handler. (Of course, if an
1181 exception is not thrown, the function that contains the @code{.save}
1182 pseudo op restores these registers in the function epilogue, as is
1183 done with the @code{ldmfd} instruction above.)
1185 You do not have to save callee-saved registers at the very beginning
1186 of the function and you do not need to use the @code{.save} pseudo op
1187 immediately following the point at which the registers are saved.
1188 However, if you modify a callee-saved register, you must save it on
1189 the stack before modifying it and before calling any functions which
1190 might throw an exception. And, you must use the @code{.save} pseudo
1191 op to indicate that you have done so.
1193 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1194 modification of the stack pointer that does not save any registers.
1195 The argument is the number of bytes (in decimal) that are subtracted
1196 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1197 subtracting from the stack pointer increases the size of the stack.)
1199 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1200 indicates the register that contains the frame pointer. The first
1201 argument is the register that is set, which is typically @code{fp}.
1202 The second argument indicates the register from which the frame
1203 pointer takes its value. The third argument, if present, is the value
1204 (in decimal) added to the register specified by the second argument to
1205 compute the value of the frame pointer. You should not modify the
1206 frame pointer in the body of the function.
1208 If you do not use a frame pointer, then you should not use the
1209 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1210 should avoid modifying the stack pointer outside of the function
1211 prologue. Otherwise, the run-time library will be unable to find
1212 saved registers when it is unwinding the stack.
1214 The pseudo ops described above are sufficient for writing assembly
1215 code that calls functions which may throw exceptions. If you need to
1216 know more about the object-file format used to represent unwind
1217 information, you may consult the @cite{Exception Handling ABI for the
1218 ARM Architecture} available from @uref{http://infocenter.arm.com}.