1 @c Copyright (C) 1996-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
134 @code{cortex-m0plus},
137 @code{marvell-whitney},
140 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
141 @code{i80200} (Intel XScale processor)
142 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
145 The special name @code{all} may be used to allow the
146 assembler to accept instructions valid for any ARM processor.
148 In addition to the basic instruction set, the assembler can be told to
149 accept various extension mnemonics that extend the processor using the
150 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
151 is equivalent to specifying @code{-mcpu=ep9312}.
153 Multiple extensions may be specified, separated by a @code{+}. The
154 extensions should be specified in ascending alphabetical order.
156 Some extensions may be restricted to particular architectures; this is
157 documented in the list of extensions below.
159 Extension mnemonics may also be removed from those the assembler accepts.
160 This is done be prepending @code{no} to the option that adds the extension.
161 Extensions that are removed should be listed after all extensions which have
162 been added, again in ascending alphabetical order. For example,
163 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
166 The following extensions are currently supported:
168 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
169 @code{fp} (Floating Point Extensions for v8-A architecture),
170 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
175 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
177 @code{os} (Operating System for v6M architecture),
178 @code{sec} (Security Extensions for v6K and v7-A architectures),
179 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
180 @code{virt} (Virtualization Extensions for v7-A architecture, implies
182 @code{pan} (Priviliged Access Never Extensions for v8-A architecture)
186 @cindex @code{-march=} command line option, ARM
187 @item -march=@var{architecture}[+@var{extension}@dots{}]
188 This option specifies the target architecture. The assembler will issue
189 an error message if an attempt is made to assemble an instruction which
190 will not execute on the target architecture. The following architecture
191 names are recognized:
225 If both @code{-mcpu} and
226 @code{-march} are specified, the assembler will use
227 the setting for @code{-mcpu}.
229 The architecture option can be extended with the same instruction set
230 extension options as the @code{-mcpu} option.
232 @cindex @code{-mfpu=} command line option, ARM
233 @item -mfpu=@var{floating-point-format}
235 This option specifies the floating point format to assemble for. The
236 assembler will issue an error message if an attempt is made to assemble
237 an instruction which will not execute on the target floating point unit.
238 The following format options are recognized:
258 @code{vfpv3-d16-fp16},
273 @code{neon-fp-armv8},
275 @code{crypto-neon-fp-armv8}.
277 In addition to determining which instructions are assembled, this option
278 also affects the way in which the @code{.double} assembler directive behaves
279 when assembling little-endian code.
281 The default is dependent on the processor selected. For Architecture 5 or
282 later, the default is to assembler for VFP instructions; for earlier
283 architectures the default is to assemble for FPA instructions.
285 @cindex @code{-mthumb} command line option, ARM
287 This option specifies that the assembler should start assembling Thumb
288 instructions; that is, it should behave as though the file starts with a
289 @code{.code 16} directive.
291 @cindex @code{-mthumb-interwork} command line option, ARM
292 @item -mthumb-interwork
293 This option specifies that the output generated by the assembler should
294 be marked as supporting interworking.
296 @cindex @code{-mimplicit-it} command line option, ARM
297 @item -mimplicit-it=never
298 @itemx -mimplicit-it=always
299 @itemx -mimplicit-it=arm
300 @itemx -mimplicit-it=thumb
301 The @code{-mimplicit-it} option controls the behavior of the assembler when
302 conditional instructions are not enclosed in IT blocks.
303 There are four possible behaviors.
304 If @code{never} is specified, such constructs cause a warning in ARM
305 code and an error in Thumb-2 code.
306 If @code{always} is specified, such constructs are accepted in both
307 ARM and Thumb-2 code, where the IT instruction is added implicitly.
308 If @code{arm} is specified, such constructs are accepted in ARM code
309 and cause an error in Thumb-2 code.
310 If @code{thumb} is specified, such constructs cause a warning in ARM
311 code and are accepted in Thumb-2 code. If you omit this option, the
312 behavior is equivalent to @code{-mimplicit-it=arm}.
314 @cindex @code{-mapcs-26} command line option, ARM
315 @cindex @code{-mapcs-32} command line option, ARM
318 These options specify that the output generated by the assembler should
319 be marked as supporting the indicated version of the Arm Procedure.
322 @cindex @code{-matpcs} command line option, ARM
324 This option specifies that the output generated by the assembler should
325 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
326 enabled this option will cause the assembler to create an empty
327 debugging section in the object file called .arm.atpcs. Debuggers can
328 use this to determine the ABI being used by.
330 @cindex @code{-mapcs-float} command line option, ARM
332 This indicates the floating point variant of the APCS should be
333 used. In this variant floating point arguments are passed in FP
334 registers rather than integer registers.
336 @cindex @code{-mapcs-reentrant} command line option, ARM
337 @item -mapcs-reentrant
338 This indicates that the reentrant variant of the APCS should be used.
339 This variant supports position independent code.
341 @cindex @code{-mfloat-abi=} command line option, ARM
342 @item -mfloat-abi=@var{abi}
343 This option specifies that the output generated by the assembler should be
344 marked as using specified floating point ABI.
345 The following values are recognized:
351 @cindex @code{-eabi=} command line option, ARM
352 @item -meabi=@var{ver}
353 This option specifies which EABI version the produced object files should
355 The following values are recognized:
361 @cindex @code{-EB} command line option, ARM
363 This option specifies that the output generated by the assembler should
364 be marked as being encoded for a big-endian processor.
366 Note: If a program is being built for a system with big-endian data
367 and little-endian instructions then it should be assembled with the
368 @option{-EB} option, (all of it, code and data) and then linked with
369 the @option{--be8} option. This will reverse the endianness of the
370 instructions back to little-endian, but leave the data as big-endian.
372 @cindex @code{-EL} command line option, ARM
374 This option specifies that the output generated by the assembler should
375 be marked as being encoded for a little-endian processor.
377 @cindex @code{-k} command line option, ARM
378 @cindex PIC code generation for ARM
380 This option specifies that the output of the assembler should be marked
381 as position-independent code (PIC).
383 @cindex @code{--fix-v4bx} command line option, ARM
385 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
386 the linker option of the same name.
388 @cindex @code{-mwarn-deprecated} command line option, ARM
389 @item -mwarn-deprecated
390 @itemx -mno-warn-deprecated
391 Enable or disable warnings about using deprecated options or
392 features. The default is to warn.
394 @cindex @code{-mccs} command line option, ARM
396 Turns on CodeComposer Studio assembly syntax compatibility mode.
398 @cindex @code{-mwarn-syms} command line option, ARM
400 @itemx -mno-warn-syms
401 Enable or disable warnings about symbols that match the names of ARM
402 instructions. The default is to warn.
410 * ARM-Instruction-Set:: Instruction Set
411 * ARM-Chars:: Special Characters
412 * ARM-Regs:: Register Names
413 * ARM-Relocations:: Relocations
414 * ARM-Neon-Alignment:: NEON Alignment Specifiers
417 @node ARM-Instruction-Set
418 @subsection Instruction Set Syntax
419 Two slightly different syntaxes are support for ARM and THUMB
420 instructions. The default, @code{divided}, uses the old style where
421 ARM and THUMB instructions had their own, separate syntaxes. The new,
422 @code{unified} syntax, which can be selected via the @code{.syntax}
423 directive, and has the following main features:
427 Immediate operands do not require a @code{#} prefix.
430 The @code{IT} instruction may appear, and if it does it is validated
431 against subsequent conditional affixes. In ARM mode it does not
432 generate machine code, in THUMB mode it does.
435 For ARM instructions the conditional affixes always appear at the end
436 of the instruction. For THUMB instructions conditional affixes can be
437 used, but only inside the scope of an @code{IT} instruction.
440 All of the instructions new to the V6T2 architecture (and later) are
441 available. (Only a few such instructions can be written in the
442 @code{divided} syntax).
445 The @code{.N} and @code{.W} suffixes are recognized and honored.
448 All instructions set the flags if and only if they have an @code{s}
453 @subsection Special Characters
455 @cindex line comment character, ARM
456 @cindex ARM line comment character
457 The presence of a @samp{@@} anywhere on a line indicates the start of
458 a comment that extends to the end of that line.
460 If a @samp{#} appears as the first character of a line then the whole
461 line is treated as a comment, but in this case the line could also be
462 a logical line number directive (@pxref{Comments}) or a preprocessor
463 control command (@pxref{Preprocessing}).
465 @cindex line separator, ARM
466 @cindex statement separator, ARM
467 @cindex ARM line separator
468 The @samp{;} character can be used instead of a newline to separate
471 @cindex immediate character, ARM
472 @cindex ARM immediate character
473 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
475 @cindex identifiers, ARM
476 @cindex ARM identifiers
477 *TODO* Explain about /data modifier on symbols.
480 @subsection Register Names
482 @cindex ARM register names
483 @cindex register names, ARM
484 *TODO* Explain about ARM register naming, and the predefined names.
486 @node ARM-Relocations
487 @subsection ARM relocation generation
489 @cindex data relocations, ARM
490 @cindex ARM data relocations
491 Specific data relocations can be generated by putting the relocation name
492 in parentheses after the symbol name. For example:
498 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
500 The following relocations are supported:
516 For compatibility with older toolchains the assembler also accepts
517 @code{(PLT)} after branch targets. On legacy targets this will
518 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
519 targets it will encode either the @samp{R_ARM_CALL} or
520 @samp{R_ARM_JUMP24} relocation, as appropriate.
522 @cindex MOVW and MOVT relocations, ARM
523 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
524 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
525 respectively. For example to load the 32-bit address of foo into r0:
528 MOVW r0, #:lower16:foo
529 MOVT r0, #:upper16:foo
532 @node ARM-Neon-Alignment
533 @subsection NEON Alignment Specifiers
535 @cindex alignment for NEON instructions
536 Some NEON load/store instructions allow an optional address
538 The ARM documentation specifies that this is indicated by
539 @samp{@@ @var{align}}. However GAS already interprets
540 the @samp{@@} character as a "line comment" start,
541 so @samp{: @var{align}} is used instead. For example:
544 vld1.8 @{q0@}, [r0, :128]
547 @node ARM Floating Point
548 @section Floating Point
550 @cindex floating point, ARM (@sc{ieee})
551 @cindex ARM floating point (@sc{ieee})
552 The ARM family uses @sc{ieee} floating-point numbers.
555 @section ARM Machine Directives
557 @cindex machine directives, ARM
558 @cindex ARM machine directives
561 @c AAAAAAAAAAAAAAAAAAAAAAAAA
563 @cindex @code{.2byte} directive, ARM
564 @cindex @code{.4byte} directive, ARM
565 @cindex @code{.8byte} directive, ARM
566 @item .2byte @var{expression} [, @var{expression}]*
567 @itemx .4byte @var{expression} [, @var{expression}]*
568 @itemx .8byte @var{expression} [, @var{expression}]*
569 These directives write 2, 4 or 8 byte values to the output section.
571 @cindex @code{.align} directive, ARM
572 @item .align @var{expression} [, @var{expression}]
573 This is the generic @var{.align} directive. For the ARM however if the
574 first argument is zero (ie no alignment is needed) the assembler will
575 behave as if the argument had been 2 (ie pad to the next four byte
576 boundary). This is for compatibility with ARM's own assembler.
578 @cindex @code{.arch} directive, ARM
579 @item .arch @var{name}
580 Select the target architecture. Valid values for @var{name} are the same as
581 for the @option{-march} commandline option.
583 Specifying @code{.arch} clears any previously selected architecture
586 @cindex @code{.arch_extension} directive, ARM
587 @item .arch_extension @var{name}
588 Add or remove an architecture extension to the target architecture. Valid
589 values for @var{name} are the same as those accepted as architectural
590 extensions by the @option{-mcpu} commandline option.
592 @code{.arch_extension} may be used multiple times to add or remove extensions
593 incrementally to the architecture being compiled for.
595 @cindex @code{.arm} directive, ARM
597 This performs the same action as @var{.code 32}.
599 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
601 @cindex @code{.bss} directive, ARM
603 This directive switches to the @code{.bss} section.
605 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
607 @cindex @code{.cantunwind} directive, ARM
609 Prevents unwinding through the current function. No personality routine
610 or exception table data is required or permitted.
612 @cindex @code{.code} directive, ARM
613 @item .code @code{[16|32]}
614 This directive selects the instruction set being generated. The value 16
615 selects Thumb, with the value 32 selecting ARM.
617 @cindex @code{.cpu} directive, ARM
618 @item .cpu @var{name}
619 Select the target processor. Valid values for @var{name} are the same as
620 for the @option{-mcpu} commandline option.
622 Specifying @code{.cpu} clears any previously selected architecture
625 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
627 @cindex @code{.dn} and @code{.qn} directives, ARM
628 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
629 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
631 The @code{dn} and @code{qn} directives are used to create typed
632 and/or indexed register aliases for use in Advanced SIMD Extension
633 (Neon) instructions. The former should be used to create aliases
634 of double-precision registers, and the latter to create aliases of
635 quad-precision registers.
637 If these directives are used to create typed aliases, those aliases can
638 be used in Neon instructions instead of writing types after the mnemonic
639 or after each operand. For example:
648 This is equivalent to writing the following:
654 Aliases created using @code{dn} or @code{qn} can be destroyed using
657 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
659 @cindex @code{.eabi_attribute} directive, ARM
660 @item .eabi_attribute @var{tag}, @var{value}
661 Set the EABI object attribute @var{tag} to @var{value}.
663 The @var{tag} is either an attribute number, or one of the following:
664 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
665 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
666 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
667 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
668 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
669 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
670 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
671 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
672 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
673 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
674 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
675 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
676 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
677 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
678 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
679 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
680 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
681 @code{Tag_conformance}, @code{Tag_T2EE_use},
682 @code{Tag_Virtualization_use}
684 The @var{value} is either a @code{number}, @code{"string"}, or
685 @code{number, "string"} depending on the tag.
687 Note - the following legacy values are also accepted by @var{tag}:
688 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
689 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
691 @cindex @code{.even} directive, ARM
693 This directive aligns to an even-numbered address.
695 @cindex @code{.extend} directive, ARM
696 @cindex @code{.ldouble} directive, ARM
697 @item .extend @var{expression} [, @var{expression}]*
698 @itemx .ldouble @var{expression} [, @var{expression}]*
699 These directives write 12byte long double floating-point values to the
700 output section. These are not compatible with current ARM processors
703 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
706 @cindex @code{.fnend} directive, ARM
708 Marks the end of a function with an unwind table entry. The unwind index
709 table entry is created when this directive is processed.
711 If no personality routine has been specified then standard personality
712 routine 0 or 1 will be used, depending on the number of unwind opcodes
716 @cindex @code{.fnstart} directive, ARM
718 Marks the start of a function with an unwind table entry.
720 @cindex @code{.force_thumb} directive, ARM
722 This directive forces the selection of Thumb instructions, even if the
723 target processor does not support those instructions
725 @cindex @code{.fpu} directive, ARM
726 @item .fpu @var{name}
727 Select the floating-point unit to assemble for. Valid values for @var{name}
728 are the same as for the @option{-mfpu} commandline option.
730 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
731 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
733 @cindex @code{.handlerdata} directive, ARM
735 Marks the end of the current function, and the start of the exception table
736 entry for that function. Anything between this directive and the
737 @code{.fnend} directive will be added to the exception table entry.
739 Must be preceded by a @code{.personality} or @code{.personalityindex}
742 @c IIIIIIIIIIIIIIIIIIIIIIIIII
744 @cindex @code{.inst} directive, ARM
745 @item .inst @var{opcode} [ , @dots{} ]
746 @itemx .inst.n @var{opcode} [ , @dots{} ]
747 @itemx .inst.w @var{opcode} [ , @dots{} ]
748 Generates the instruction corresponding to the numerical value @var{opcode}.
749 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
750 specified explicitly, overriding the normal encoding rules.
752 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
753 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
754 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
756 @item .ldouble @var{expression} [, @var{expression}]*
759 @cindex @code{.ltorg} directive, ARM
761 This directive causes the current contents of the literal pool to be
762 dumped into the current section (which is assumed to be the .text
763 section) at the current location (aligned to a word boundary).
764 @code{GAS} maintains a separate literal pool for each section and each
765 sub-section. The @code{.ltorg} directive will only affect the literal
766 pool of the current section and sub-section. At the end of assembly
767 all remaining, un-empty literal pools will automatically be dumped.
769 Note - older versions of @code{GAS} would dump the current literal
770 pool any time a section change occurred. This is no longer done, since
771 it prevents accurate control of the placement of literal pools.
773 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
775 @cindex @code{.movsp} directive, ARM
776 @item .movsp @var{reg} [, #@var{offset}]
777 Tell the unwinder that @var{reg} contains an offset from the current
778 stack pointer. If @var{offset} is not specified then it is assumed to be
781 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
782 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
784 @cindex @code{.object_arch} directive, ARM
785 @item .object_arch @var{name}
786 Override the architecture recorded in the EABI object attribute section.
787 Valid values for @var{name} are the same as for the @code{.arch} directive.
788 Typically this is useful when code uses runtime detection of CPU features.
790 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
792 @cindex @code{.packed} directive, ARM
793 @item .packed @var{expression} [, @var{expression}]*
794 This directive writes 12-byte packed floating-point values to the
795 output section. These are not compatible with current ARM processors
799 @cindex @code{.pad} directive, ARM
800 @item .pad #@var{count}
801 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
802 A positive value indicates the function prologue allocated stack space by
803 decrementing the stack pointer.
805 @cindex @code{.personality} directive, ARM
806 @item .personality @var{name}
807 Sets the personality routine for the current function to @var{name}.
809 @cindex @code{.personalityindex} directive, ARM
810 @item .personalityindex @var{index}
811 Sets the personality routine for the current function to the EABI standard
812 routine number @var{index}
814 @cindex @code{.pool} directive, ARM
816 This is a synonym for .ltorg.
818 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
819 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
821 @cindex @code{.req} directive, ARM
822 @item @var{name} .req @var{register name}
823 This creates an alias for @var{register name} called @var{name}. For
830 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
833 @cindex @code{.save} directive, ARM
834 @item .save @var{reglist}
835 Generate unwinder annotations to restore the registers in @var{reglist}.
836 The format of @var{reglist} is the same as the corresponding store-multiple
840 @exdent @emph{core registers}
841 .save @{r4, r5, r6, lr@}
842 stmfd sp!, @{r4, r5, r6, lr@}
843 @exdent @emph{FPA registers}
846 @exdent @emph{VFP registers}
847 .save @{d8, d9, d10@}
848 fstmdx sp!, @{d8, d9, d10@}
849 @exdent @emph{iWMMXt registers}
851 wstrd wr11, [sp, #-8]!
852 wstrd wr10, [sp, #-8]!
855 wstrd wr11, [sp, #-8]!
857 wstrd wr10, [sp, #-8]!
861 @cindex @code{.setfp} directive, ARM
862 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
863 Make all unwinder annotations relative to a frame pointer. Without this
864 the unwinder will use offsets from the stack pointer.
866 The syntax of this directive is the same as the @code{add} or @code{mov}
867 instruction used to set the frame pointer. @var{spreg} must be either
868 @code{sp} or mentioned in a previous @code{.movsp} directive.
878 @cindex @code{.secrel32} directive, ARM
879 @item .secrel32 @var{expression} [, @var{expression}]*
880 This directive emits relocations that evaluate to the section-relative
881 offset of each expression's symbol. This directive is only supported
884 @cindex @code{.syntax} directive, ARM
885 @item .syntax [@code{unified} | @code{divided}]
886 This directive sets the Instruction Set Syntax as described in the
887 @ref{ARM-Instruction-Set} section.
889 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
891 @cindex @code{.thumb} directive, ARM
893 This performs the same action as @var{.code 16}.
895 @cindex @code{.thumb_func} directive, ARM
897 This directive specifies that the following symbol is the name of a
898 Thumb encoded function. This information is necessary in order to allow
899 the assembler and linker to generate correct code for interworking
900 between Arm and Thumb instructions and should be used even if
901 interworking is not going to be performed. The presence of this
902 directive also implies @code{.thumb}
904 This directive is not neccessary when generating EABI objects. On these
905 targets the encoding is implicit when generating Thumb code.
907 @cindex @code{.thumb_set} directive, ARM
909 This performs the equivalent of a @code{.set} directive in that it
910 creates a symbol which is an alias for another symbol (possibly not yet
911 defined). This directive also has the added property in that it marks
912 the aliased symbol as being a thumb function entry point, in the same
913 way that the @code{.thumb_func} directive does.
915 @cindex @code{.tlsdescseq} directive, ARM
916 @item .tlsdescseq @var{tls-variable}
917 This directive is used to annotate parts of an inlined TLS descriptor
918 trampoline. Normally the trampoline is provided by the linker, and
919 this directive is not needed.
921 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
923 @cindex @code{.unreq} directive, ARM
924 @item .unreq @var{alias-name}
925 This undefines a register alias which was previously defined using the
926 @code{req}, @code{dn} or @code{qn} directives. For example:
933 An error occurs if the name is undefined. Note - this pseudo op can
934 be used to delete builtin in register name aliases (eg 'r0'). This
935 should only be done if it is really necessary.
937 @cindex @code{.unwind_raw} directive, ARM
938 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
939 Insert one of more arbitary unwind opcode bytes, which are known to adjust
940 the stack pointer by @var{offset} bytes.
942 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
945 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
947 @cindex @code{.vsave} directive, ARM
948 @item .vsave @var{vfp-reglist}
949 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
950 using FLDMD. Also works for VFPv3 registers
951 that are to be restored using VLDM.
952 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
956 @exdent @emph{VFP registers}
957 .vsave @{d8, d9, d10@}
958 fstmdd sp!, @{d8, d9, d10@}
959 @exdent @emph{VFPv3 registers}
960 .vsave @{d15, d16, d17@}
961 vstm sp!, @{d15, d16, d17@}
964 Since FLDMX and FSTMX are now deprecated, this directive should be
965 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
967 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
968 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
969 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
970 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
978 @cindex opcodes for ARM
979 @code{@value{AS}} implements all the standard ARM opcodes. It also
980 implements several pseudo opcodes, including several synthetic load
985 @cindex @code{NOP} pseudo op, ARM
991 This pseudo op will always evaluate to a legal ARM instruction that does
992 nothing. Currently it will evaluate to MOV r0, r0.
994 @cindex @code{LDR reg,=<label>} pseudo op, ARM
997 ldr <register> , = <expression>
1000 If expression evaluates to a numeric constant then a MOV or MVN
1001 instruction will be used in place of the LDR instruction, if the
1002 constant can be generated by either of these instructions. Otherwise
1003 the constant will be placed into the nearest literal pool (if it not
1004 already there) and a PC relative LDR instruction will be generated.
1006 @cindex @code{ADR reg,<label>} pseudo op, ARM
1009 adr <register> <label>
1012 This instruction will load the address of @var{label} into the indicated
1013 register. The instruction will evaluate to a PC relative ADD or SUB
1014 instruction depending upon where the label is located. If the label is
1015 out of range, or if it is not defined in the same file (and section) as
1016 the ADR instruction, then an error will be generated. This instruction
1017 will not make use of the literal pool.
1019 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1022 adrl <register> <label>
1025 This instruction will load the address of @var{label} into the indicated
1026 register. The instruction will evaluate to one or two PC relative ADD
1027 or SUB instructions depending upon where the label is located. If a
1028 second instruction is not needed a NOP instruction will be generated in
1029 its place, so that this instruction is always 8 bytes long.
1031 If the label is out of range, or if it is not defined in the same file
1032 (and section) as the ADRL instruction, then an error will be generated.
1033 This instruction will not make use of the literal pool.
1037 For information on the ARM or Thumb instruction sets, see @cite{ARM
1038 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1041 @node ARM Mapping Symbols
1042 @section Mapping Symbols
1044 The ARM ELF specification requires that special symbols be inserted
1045 into object files to mark certain features:
1051 At the start of a region of code containing ARM instructions.
1055 At the start of a region of code containing THUMB instructions.
1059 At the start of a region of data.
1063 The assembler will automatically insert these symbols for you - there
1064 is no need to code them yourself. Support for tagging symbols ($b,
1065 $f, $p and $m) which is also mentioned in the current ARM ELF
1066 specification is not implemented. This is because they have been
1067 dropped from the new EABI and so tools cannot rely upon their
1070 @node ARM Unwinding Tutorial
1073 The ABI for the ARM Architecture specifies a standard format for
1074 exception unwind information. This information is used when an
1075 exception is thrown to determine where control should be transferred.
1076 In particular, the unwind information is used to determine which
1077 function called the function that threw the exception, and which
1078 function called that one, and so forth. This information is also used
1079 to restore the values of callee-saved registers in the function
1080 catching the exception.
1082 If you are writing functions in assembly code, and those functions
1083 call other functions that throw exceptions, you must use assembly
1084 pseudo ops to ensure that appropriate exception unwind information is
1085 generated. Otherwise, if one of the functions called by your assembly
1086 code throws an exception, the run-time library will be unable to
1087 unwind the stack through your assembly code and your program will not
1090 To illustrate the use of these pseudo ops, we will examine the code
1091 that G++ generates for the following C++ input:
1094 void callee (int *);
1105 This example does not show how to throw or catch an exception from
1106 assembly code. That is a much more complex operation and should
1107 always be done in a high-level language, such as C++, that directly
1108 supports exceptions.
1110 The code generated by one particular version of G++ when compiling the
1117 @ Function supports interworking.
1118 @ args = 0, pretend = 0, frame = 8
1119 @ frame_needed = 1, uses_anonymous_args = 0
1141 Of course, the sequence of instructions varies based on the options
1142 you pass to GCC and on the version of GCC in use. The exact
1143 instructions are not important since we are focusing on the pseudo ops
1144 that are used to generate unwind information.
1146 An important assumption made by the unwinder is that the stack frame
1147 does not change during the body of the function. In particular, since
1148 we assume that the assembly code does not itself throw an exception,
1149 the only point where an exception can be thrown is from a call, such
1150 as the @code{bl} instruction above. At each call site, the same saved
1151 registers (including @code{lr}, which indicates the return address)
1152 must be located in the same locations relative to the frame pointer.
1154 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1155 op appears immediately before the first instruction of the function
1156 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1157 op appears immediately after the last instruction of the function.
1158 These pseudo ops specify the range of the function.
1160 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1161 @code{.pad}) matters; their exact locations are irrelevant. In the
1162 example above, the compiler emits the pseudo ops with particular
1163 instructions. That makes it easier to understand the code, but it is
1164 not required for correctness. It would work just as well to emit all
1165 of the pseudo ops other than @code{.fnend} in the same order, but
1166 immediately after @code{.fnstart}.
1168 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1169 indicates registers that have been saved to the stack so that they can
1170 be restored before the function returns. The argument to the
1171 @code{.save} pseudo op is a list of registers to save. If a register
1172 is ``callee-saved'' (as specified by the ABI) and is modified by the
1173 function you are writing, then your code must save the value before it
1174 is modified and restore the original value before the function
1175 returns. If an exception is thrown, the run-time library restores the
1176 values of these registers from their locations on the stack before
1177 returning control to the exception handler. (Of course, if an
1178 exception is not thrown, the function that contains the @code{.save}
1179 pseudo op restores these registers in the function epilogue, as is
1180 done with the @code{ldmfd} instruction above.)
1182 You do not have to save callee-saved registers at the very beginning
1183 of the function and you do not need to use the @code{.save} pseudo op
1184 immediately following the point at which the registers are saved.
1185 However, if you modify a callee-saved register, you must save it on
1186 the stack before modifying it and before calling any functions which
1187 might throw an exception. And, you must use the @code{.save} pseudo
1188 op to indicate that you have done so.
1190 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1191 modification of the stack pointer that does not save any registers.
1192 The argument is the number of bytes (in decimal) that are subtracted
1193 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1194 subtracting from the stack pointer increases the size of the stack.)
1196 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1197 indicates the register that contains the frame pointer. The first
1198 argument is the register that is set, which is typically @code{fp}.
1199 The second argument indicates the register from which the frame
1200 pointer takes its value. The third argument, if present, is the value
1201 (in decimal) added to the register specified by the second argument to
1202 compute the value of the frame pointer. You should not modify the
1203 frame pointer in the body of the function.
1205 If you do not use a frame pointer, then you should not use the
1206 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1207 should avoid modifying the stack pointer outside of the function
1208 prologue. Otherwise, the run-time library will be unable to find
1209 saved registers when it is unwinding the stack.
1211 The pseudo ops described above are sufficient for writing assembly
1212 code that calls functions which may throw exceptions. If you need to
1213 know more about the object-file format used to represent unwind
1214 information, you may consult the @cite{Exception Handling ABI for the
1215 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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