1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2008
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
119 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
120 @code{i80200} (Intel XScale processor)
121 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
124 The special name @code{all} may be used to allow the
125 assembler to accept instructions valid for any ARM processor.
127 In addition to the basic instruction set, the assembler can be told to
128 accept various extension mnemonics that extend the processor using the
129 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
130 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
131 are currently supported:
137 @cindex @code{-march=} command line option, ARM
138 @item -march=@var{architecture}[+@var{extension}@dots{}]
139 This option specifies the target architecture. The assembler will issue
140 an error message if an attempt is made to assemble an instruction which
141 will not execute on the target architecture. The following architecture
142 names are recognized:
170 If both @code{-mcpu} and
171 @code{-march} are specified, the assembler will use
172 the setting for @code{-mcpu}.
174 The architecture option can be extended with the same instruction set
175 extension options as the @code{-mcpu} option.
177 @cindex @code{-mfpu=} command line option, ARM
178 @item -mfpu=@var{floating-point-format}
180 This option specifies the floating point format to assemble for. The
181 assembler will issue an error message if an attempt is made to assemble
182 an instruction which will not execute on the target floating point unit.
183 The following format options are recognized:
209 In addition to determining which instructions are assembled, this option
210 also affects the way in which the @code{.double} assembler directive behaves
211 when assembling little-endian code.
213 The default is dependent on the processor selected. For Architecture 5 or
214 later, the default is to assembler for VFP instructions; for earlier
215 architectures the default is to assemble for FPA instructions.
217 @cindex @code{-mthumb} command line option, ARM
219 This option specifies that the assembler should start assembling Thumb
220 instructions; that is, it should behave as though the file starts with a
221 @code{.code 16} directive.
223 @cindex @code{-mthumb-interwork} command line option, ARM
224 @item -mthumb-interwork
225 This option specifies that the output generated by the assembler should
226 be marked as supporting interworking.
228 @cindex @code{-mapcs} command line option, ARM
229 @item -mapcs @code{[26|32]}
230 This option specifies that the output generated by the assembler should
231 be marked as supporting the indicated version of the Arm Procedure.
234 @cindex @code{-matpcs} command line option, ARM
236 This option specifies that the output generated by the assembler should
237 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
238 enabled this option will cause the assembler to create an empty
239 debugging section in the object file called .arm.atpcs. Debuggers can
240 use this to determine the ABI being used by.
242 @cindex @code{-mapcs-float} command line option, ARM
244 This indicates the floating point variant of the APCS should be
245 used. In this variant floating point arguments are passed in FP
246 registers rather than integer registers.
248 @cindex @code{-mapcs-reentrant} command line option, ARM
249 @item -mapcs-reentrant
250 This indicates that the reentrant variant of the APCS should be used.
251 This variant supports position independent code.
253 @cindex @code{-mfloat-abi=} command line option, ARM
254 @item -mfloat-abi=@var{abi}
255 This option specifies that the output generated by the assembler should be
256 marked as using specified floating point ABI.
257 The following values are recognized:
263 @cindex @code{-eabi=} command line option, ARM
264 @item -meabi=@var{ver}
265 This option specifies which EABI version the produced object files should
267 The following values are recognized:
273 @cindex @code{-EB} command line option, ARM
275 This option specifies that the output generated by the assembler should
276 be marked as being encoded for a big-endian processor.
278 @cindex @code{-EL} command line option, ARM
280 This option specifies that the output generated by the assembler should
281 be marked as being encoded for a little-endian processor.
283 @cindex @code{-k} command line option, ARM
284 @cindex PIC code generation for ARM
286 This option specifies that the output of the assembler should be marked
287 as position-independent code (PIC).
289 @cindex @code{--fix-v4bx} command line option, ARM
291 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
292 the linker option of the same name.
300 * ARM-Chars:: Special Characters
301 * ARM-Regs:: Register Names
302 * ARM-Relocations:: Relocations
306 @subsection Special Characters
308 @cindex line comment character, ARM
309 @cindex ARM line comment character
310 The presence of a @samp{@@} on a line indicates the start of a comment
311 that extends to the end of the current line. If a @samp{#} appears as
312 the first character of a line, the whole line is treated as a comment.
314 @cindex line separator, ARM
315 @cindex statement separator, ARM
316 @cindex ARM line separator
317 The @samp{;} character can be used instead of a newline to separate
320 @cindex immediate character, ARM
321 @cindex ARM immediate character
322 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
324 @cindex identifiers, ARM
325 @cindex ARM identifiers
326 *TODO* Explain about /data modifier on symbols.
329 @subsection Register Names
331 @cindex ARM register names
332 @cindex register names, ARM
333 *TODO* Explain about ARM register naming, and the predefined names.
335 @node ARM Floating Point
336 @section Floating Point
338 @cindex floating point, ARM (@sc{ieee})
339 @cindex ARM floating point (@sc{ieee})
340 The ARM family uses @sc{ieee} floating-point numbers.
342 @node ARM-Relocations
343 @subsection ARM relocation generation
345 @cindex data relocations, ARM
346 @cindex ARM data relocations
347 Specific data relocations can be generated by putting the relocation name
348 in parentheses after the symbol name. For example:
354 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
356 The following relocations are supported:
369 For compatibility with older toolchains the assembler also accepts
370 @code{(PLT)} after branch targets. This will generate the deprecated
371 @samp{R_ARM_PLT32} relocation.
373 @cindex MOVW and MOVT relocations, ARM
374 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
375 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
376 respectively. For example to load the 32-bit address of foo into r0:
379 MOVW r0, #:lower16:foo
380 MOVT r0, #:upper16:foo
384 @section ARM Machine Directives
386 @cindex machine directives, ARM
387 @cindex ARM machine directives
390 @cindex @code{align} directive, ARM
391 @item .align @var{expression} [, @var{expression}]
392 This is the generic @var{.align} directive. For the ARM however if the
393 first argument is zero (ie no alignment is needed) the assembler will
394 behave as if the argument had been 2 (ie pad to the next four byte
395 boundary). This is for compatibility with ARM's own assembler.
397 @cindex @code{req} directive, ARM
398 @item @var{name} .req @var{register name}
399 This creates an alias for @var{register name} called @var{name}. For
406 @cindex @code{unreq} directive, ARM
407 @item .unreq @var{alias-name}
408 This undefines a register alias which was previously defined using the
409 @code{req}, @code{dn} or @code{qn} directives. For example:
416 An error occurs if the name is undefined. Note - this pseudo op can
417 be used to delete builtin in register name aliases (eg 'r0'). This
418 should only be done if it is really necessary.
420 @cindex @code{dn} and @code{qn} directives, ARM
421 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
422 @item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
424 The @code{dn} and @code{qn} directives are used to create typed
425 and/or indexed register aliases for use in Advanced SIMD Extension
426 (Neon) instructions. The former should be used to create aliases
427 of double-precision registers, and the latter to create aliases of
428 quad-precision registers.
430 If these directives are used to create typed aliases, those aliases can
431 be used in Neon instructions instead of writing types after the mnemonic
432 or after each operand. For example:
441 This is equivalent to writing the following:
447 Aliases created using @code{dn} or @code{qn} can be destroyed using
450 @cindex @code{code} directive, ARM
451 @item .code @code{[16|32]}
452 This directive selects the instruction set being generated. The value 16
453 selects Thumb, with the value 32 selecting ARM.
455 @cindex @code{thumb} directive, ARM
457 This performs the same action as @var{.code 16}.
459 @cindex @code{arm} directive, ARM
461 This performs the same action as @var{.code 32}.
463 @cindex @code{force_thumb} directive, ARM
465 This directive forces the selection of Thumb instructions, even if the
466 target processor does not support those instructions
468 @cindex @code{thumb_func} directive, ARM
470 This directive specifies that the following symbol is the name of a
471 Thumb encoded function. This information is necessary in order to allow
472 the assembler and linker to generate correct code for interworking
473 between Arm and Thumb instructions and should be used even if
474 interworking is not going to be performed. The presence of this
475 directive also implies @code{.thumb}
477 This directive is not neccessary when generating EABI objects. On these
478 targets the encoding is implicit when generating Thumb code.
480 @cindex @code{thumb_set} directive, ARM
482 This performs the equivalent of a @code{.set} directive in that it
483 creates a symbol which is an alias for another symbol (possibly not yet
484 defined). This directive also has the added property in that it marks
485 the aliased symbol as being a thumb function entry point, in the same
486 way that the @code{.thumb_func} directive does.
488 @cindex @code{.ltorg} directive, ARM
490 This directive causes the current contents of the literal pool to be
491 dumped into the current section (which is assumed to be the .text
492 section) at the current location (aligned to a word boundary).
493 @code{GAS} maintains a separate literal pool for each section and each
494 sub-section. The @code{.ltorg} directive will only affect the literal
495 pool of the current section and sub-section. At the end of assembly
496 all remaining, un-empty literal pools will automatically be dumped.
498 Note - older versions of @code{GAS} would dump the current literal
499 pool any time a section change occurred. This is no longer done, since
500 it prevents accurate control of the placement of literal pools.
502 @cindex @code{.pool} directive, ARM
504 This is a synonym for .ltorg.
507 @cindex @code{.fnstart} directive, ARM
509 Marks the start of a function with an unwind table entry.
512 @cindex @code{.fnend} directive, ARM
514 Marks the end of a function with an unwind table entry. The unwind index
515 table entry is created when this directive is processed.
517 If no personality routine has been specified then standard personality
518 routine 0 or 1 will be used, depending on the number of unwind opcodes
521 @cindex @code{.cantunwind} directive, ARM
523 Prevents unwinding through the current function. No personality routine
524 or exception table data is required or permitted.
526 @cindex @code{.personality} directive, ARM
527 @item .personality @var{name}
528 Sets the personality routine for the current function to @var{name}.
530 @cindex @code{.personalityindex} directive, ARM
531 @item .personalityindex @var{index}
532 Sets the personality routine for the current function to the EABI standard
533 routine number @var{index}
535 @cindex @code{.handlerdata} directive, ARM
537 Marks the end of the current function, and the start of the exception table
538 entry for that function. Anything between this directive and the
539 @code{.fnend} directive will be added to the exception table entry.
541 Must be preceded by a @code{.personality} or @code{.personalityindex}
545 @cindex @code{.save} directive, ARM
546 @item .save @var{reglist}
547 Generate unwinder annotations to restore the registers in @var{reglist}.
548 The format of @var{reglist} is the same as the corresponding store-multiple
552 @exdent @emph{core registers}
553 .save @{r4, r5, r6, lr@}
554 stmfd sp!, @{r4, r5, r6, lr@}
555 @exdent @emph{FPA registers}
558 @exdent @emph{VFP registers}
559 .save @{d8, d9, d10@}
560 fstmdx sp!, @{d8, d9, d10@}
561 @exdent @emph{iWMMXt registers}
563 wstrd wr11, [sp, #-8]!
564 wstrd wr10, [sp, #-8]!
567 wstrd wr11, [sp, #-8]!
569 wstrd wr10, [sp, #-8]!
572 @cindex @code{.vsave} directive, ARM
573 @item .vsave @var{vfp-reglist}
574 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
575 using FLDMD. Also works for VFPv3 registers
576 that are to be restored using VLDM.
577 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
581 @exdent @emph{VFP registers}
582 .vsave @{d8, d9, d10@}
583 fstmdd sp!, @{d8, d9, d10@}
584 @exdent @emph{VFPv3 registers}
585 .vsave @{d15, d16, d17@}
586 vstm sp!, @{d15, d16, d17@}
589 Since FLDMX and FSTMX are now deprecated, this directive should be
590 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
593 @cindex @code{.pad} directive, ARM
594 @item .pad #@var{count}
595 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
596 A positive value indicates the function prologue allocated stack space by
597 decrementing the stack pointer.
600 @cindex @code{.movsp} directive, ARM
601 @item .movsp @var{reg} [, #@var{offset}]
602 Tell the unwinder that @var{reg} contains an offset from the current
603 stack pointer. If @var{offset} is not specified then it is assumed to be
607 @cindex @code{.setfp} directive, ARM
608 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
609 Make all unwinder annotations relaive to a frame pointer. Without this
610 the unwinder will use offsets from the stack pointer.
612 The syntax of this directive is the same as the @code{sub} or @code{mov}
613 instruction used to set the frame pointer. @var{spreg} must be either
614 @code{sp} or mentioned in a previous @code{.movsp} directive.
624 @cindex @code{.unwind_raw} directive, ARM
625 @item .raw @var{offset}, @var{byte1}, @dots{}
626 Insert one of more arbitary unwind opcode bytes, which are known to adjust
627 the stack pointer by @var{offset} bytes.
629 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
632 @cindex @code{.cpu} directive, ARM
633 @item .cpu @var{name}
634 Select the target processor. Valid values for @var{name} are the same as
635 for the @option{-mcpu} commandline option.
637 @cindex @code{.arch} directive, ARM
638 @item .arch @var{name}
639 Select the target architecture. Valid values for @var{name} are the same as
640 for the @option{-march} commandline option.
642 @cindex @code{.object_arch} directive, ARM
643 @item .object_arch @var{name}
644 Override the architecture recorded in the EABI object attribute section.
645 Valid values for @var{name} are the same as for the @code{.arch} directive.
646 Typically this is useful when code uses runtime detection of CPU features.
648 @cindex @code{.fpu} directive, ARM
649 @item .fpu @var{name}
650 Select the floating point unit to assemble for. Valid values for @var{name}
651 are the same as for the @option{-mfpu} commandline option.
653 @cindex @code{.eabi_attribute} directive, ARM
654 @item .eabi_attribute @var{tag}, @var{value}
655 Set the EABI object attribute @var{tag} to @var{value}.
657 The @var{tag} is either an attribute number, or one of the following:
658 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
659 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
660 @code{Tag_THUMB_ISA_use}, @code{Tag_VFP_arch}, @code{Tag_WMMX_arch},
661 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
662 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
663 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
664 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
665 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
666 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
667 @code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved},
668 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
669 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
670 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
671 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
672 @code{Tag_VFP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
673 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
674 @code{Tag_conformance}, @code{Tag_T2EE_use},
675 @code{Tag_Virtualization_use}, @code{Tag_MPextension_use}
677 The @var{value} is either a @code{number}, @code{"string"}, or
678 @code{number, "string"} depending on the tag.
686 @cindex opcodes for ARM
687 @code{@value{AS}} implements all the standard ARM opcodes. It also
688 implements several pseudo opcodes, including several synthetic load
693 @cindex @code{NOP} pseudo op, ARM
699 This pseudo op will always evaluate to a legal ARM instruction that does
700 nothing. Currently it will evaluate to MOV r0, r0.
702 @cindex @code{LDR reg,=<label>} pseudo op, ARM
705 ldr <register> , = <expression>
708 If expression evaluates to a numeric constant then a MOV or MVN
709 instruction will be used in place of the LDR instruction, if the
710 constant can be generated by either of these instructions. Otherwise
711 the constant will be placed into the nearest literal pool (if it not
712 already there) and a PC relative LDR instruction will be generated.
714 @cindex @code{ADR reg,<label>} pseudo op, ARM
717 adr <register> <label>
720 This instruction will load the address of @var{label} into the indicated
721 register. The instruction will evaluate to a PC relative ADD or SUB
722 instruction depending upon where the label is located. If the label is
723 out of range, or if it is not defined in the same file (and section) as
724 the ADR instruction, then an error will be generated. This instruction
725 will not make use of the literal pool.
727 @cindex @code{ADRL reg,<label>} pseudo op, ARM
730 adrl <register> <label>
733 This instruction will load the address of @var{label} into the indicated
734 register. The instruction will evaluate to one or two PC relative ADD
735 or SUB instructions depending upon where the label is located. If a
736 second instruction is not needed a NOP instruction will be generated in
737 its place, so that this instruction is always 8 bytes long.
739 If the label is out of range, or if it is not defined in the same file
740 (and section) as the ADRL instruction, then an error will be generated.
741 This instruction will not make use of the literal pool.
745 For information on the ARM or Thumb instruction sets, see @cite{ARM
746 Software Development Toolkit Reference Manual}, Advanced RISC Machines
749 @node ARM Mapping Symbols
750 @section Mapping Symbols
752 The ARM ELF specification requires that special symbols be inserted
753 into object files to mark certain features:
759 At the start of a region of code containing ARM instructions.
763 At the start of a region of code containing THUMB instructions.
767 At the start of a region of data.
771 The assembler will automatically insert these symbols for you - there
772 is no need to code them yourself. Support for tagging symbols ($b,
773 $f, $p and $m) which is also mentioned in the current ARM ELF
774 specification is not implemented. This is because they have been
775 dropped from the new EABI and so tools cannot rely upon their
778 @node ARM Unwinding Tutorial
781 The ABI for the ARM Architecture specifies a standard format for
782 exception unwind information. This information is used when an
783 exception is thrown to determine where control should be transferred.
784 In particular, the unwind information is used to determine which
785 function called the function that threw the exception, and which
786 function called that one, and so forth. This information is also used
787 to restore the values of callee-saved registers in the function
788 catching the exception.
790 If you are writing functions in assembly code, and those functions
791 call other functions that throw exceptions, you must use assembly
792 pseudo ops to ensure that appropriate exception unwind information is
793 generated. Otherwise, if one of the functions called by your assembly
794 code throws an exception, the run-time library will be unable to
795 unwind the stack through your assembly code and your program will not
798 To illustrate the use of these pseudo ops, we will examine the code
799 that G++ generates for the following C++ input:
813 This example does not show how to throw or catch an exception from
814 assembly code. That is a much more complex operation and should
815 always be done in a high-level language, such as C++, that directly
818 The code generated by one particular version of G++ when compiling the
825 @ Function supports interworking.
826 @ args = 0, pretend = 0, frame = 8
827 @ frame_needed = 1, uses_anonymous_args = 0
849 Of course, the sequence of instructions varies based on the options
850 you pass to GCC and on the version of GCC in use. The exact
851 instructions are not important since we are focusing on the pseudo ops
852 that are used to generate unwind information.
854 An important assumption made by the unwinder is that the stack frame
855 does not change during the body of the function. In particular, since
856 we assume that the assembly code does not itself throw an exception,
857 the only point where an exception can be thrown is from a call, such
858 as the @code{bl} instruction above. At each call site, the same saved
859 registers (including @code{lr}, which indicates the return address)
860 must be located in the same locations relative to the frame pointer.
862 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
863 op appears immediately before the first instruction of the function
864 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
865 op appears immediately after the last instruction of the function.
866 These pseudo ops specify the range of the function.
868 Only the order of the other pseudos ops (e.g., @code{.setfp} or
869 @code{.pad}) matters; their exact locations are irrelevant. In the
870 example above, the compiler emits the pseudo ops with particular
871 instructions. That makes it easier to understand the code, but it is
872 not required for correctness. It would work just as well to emit all
873 of the pseudo ops other than @code{.fnend} in the same order, but
874 immediately after @code{.fnstart}.
876 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
877 indicates registers that have been saved to the stack so that they can
878 be restored before the function returns. The argument to the
879 @code{.save} pseudo op is a list of registers to save. If a register
880 is ``callee-saved'' (as specified by the ABI) and is modified by the
881 function you are writing, then your code must save the value before it
882 is modified and restore the original value before the function
883 returns. If an exception is thrown, the run-time library restores the
884 values of these registers from their locations on the stack before
885 returning control to the exception handler. (Of course, if an
886 exception is not thrown, the function that contains the @code{.save}
887 pseudo op restores these registers in the function epilogue, as is
888 done with the @code{ldmfd} instruction above.)
890 You do not have to save callee-saved registers at the very beginning
891 of the function and you do not need to use the @code{.save} pseudo op
892 immediately following the point at which the registers are saved.
893 However, if you modify a callee-saved register, you must save it on
894 the stack before modifying it and before calling any functions which
895 might throw an exception. And, you must use the @code{.save} pseudo
896 op to indicate that you have done so.
898 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
899 modification of the stack pointer that does not save any registers.
900 The argument is the number of bytes (in decimal) that are subtracted
901 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
902 subtracting from the stack pointer increases the size of the stack.)
904 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
905 indicates the register that contains the frame pointer. The first
906 argument is the register that is set, which is typically @code{fp}.
907 The second argument indicates the register from which the frame
908 pointer takes its value. The third argument, if present, is the value
909 (in decimal) added to the register specified by the second argument to
910 compute the value of the frame pointer. You should not modify the
911 frame pointer in the body of the function.
913 If you do not use a frame pointer, then you should not use the
914 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
915 should avoid modifying the stack pointer outside of the function
916 prologue. Otherwise, the run-time library will be unable to find
917 saved registers when it is unwinding the stack.
919 The pseudo ops described above are sufficient for writing assembly
920 code that calls functions which may throw exceptions. If you need to
921 know more about the object-file format used to represent unwind
922 information, you may consult the @cite{Exception Handling ABI for the
923 ARM Architecture} available from @uref{http://infocenter.arm.com}.