1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
125 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
126 @code{i80200} (Intel XScale processor)
127 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
130 The special name @code{all} may be used to allow the
131 assembler to accept instructions valid for any ARM processor.
133 In addition to the basic instruction set, the assembler can be told to
134 accept various extension mnemonics that extend the processor using the
135 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
136 is equivalent to specifying @code{-mcpu=ep9312}.
138 Multiple extensions may be specified, separated by a @code{+}. The
139 extensions should be specified in ascending alphabetical order.
141 Some extensions may be restricted to particular architectures; this is
142 documented in the list of extensions below.
144 Extension mnemonics may also be removed from those the assembler accepts.
145 This is done be prepending @code{no} to the option that adds the extension.
146 Extensions that are removed should be listed after all extensions which have
147 been added, again in ascending alphabetical order. For example,
148 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
151 The following extensions are currently supported:
152 @code{idiv}, (Integer Divide Extensions for v7-A architecture),
156 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
157 @code{os} (Operating System for v6M architecture),
158 @code{sec} (Security Extensions for v6K and v7-A architectures),
162 @cindex @code{-march=} command line option, ARM
163 @item -march=@var{architecture}[+@var{extension}@dots{}]
164 This option specifies the target architecture. The assembler will issue
165 an error message if an attempt is made to assemble an instruction which
166 will not execute on the target architecture. The following architecture
167 names are recognized:
198 If both @code{-mcpu} and
199 @code{-march} are specified, the assembler will use
200 the setting for @code{-mcpu}.
202 The architecture option can be extended with the same instruction set
203 extension options as the @code{-mcpu} option.
205 @cindex @code{-mfpu=} command line option, ARM
206 @item -mfpu=@var{floating-point-format}
208 This option specifies the floating point format to assemble for. The
209 assembler will issue an error message if an attempt is made to assemble
210 an instruction which will not execute on the target floating point unit.
211 The following format options are recognized:
231 @code{vfpv3-d16-fp16},
245 In addition to determining which instructions are assembled, this option
246 also affects the way in which the @code{.double} assembler directive behaves
247 when assembling little-endian code.
249 The default is dependent on the processor selected. For Architecture 5 or
250 later, the default is to assembler for VFP instructions; for earlier
251 architectures the default is to assemble for FPA instructions.
253 @cindex @code{-mthumb} command line option, ARM
255 This option specifies that the assembler should start assembling Thumb
256 instructions; that is, it should behave as though the file starts with a
257 @code{.code 16} directive.
259 @cindex @code{-mthumb-interwork} command line option, ARM
260 @item -mthumb-interwork
261 This option specifies that the output generated by the assembler should
262 be marked as supporting interworking.
264 @cindex @code{-mimplicit-it} command line option, ARM
265 @item -mimplicit-it=never
266 @itemx -mimplicit-it=always
267 @itemx -mimplicit-it=arm
268 @itemx -mimplicit-it=thumb
269 The @code{-mimplicit-it} option controls the behavior of the assembler when
270 conditional instructions are not enclosed in IT blocks.
271 There are four possible behaviors.
272 If @code{never} is specified, such constructs cause a warning in ARM
273 code and an error in Thumb-2 code.
274 If @code{always} is specified, such constructs are accepted in both
275 ARM and Thumb-2 code, where the IT instruction is added implicitly.
276 If @code{arm} is specified, such constructs are accepted in ARM code
277 and cause an error in Thumb-2 code.
278 If @code{thumb} is specified, such constructs cause a warning in ARM
279 code and are accepted in Thumb-2 code. If you omit this option, the
280 behavior is equivalent to @code{-mimplicit-it=arm}.
282 @cindex @code{-mapcs-26} command line option, ARM
283 @cindex @code{-mapcs-32} command line option, ARM
286 These options specify that the output generated by the assembler should
287 be marked as supporting the indicated version of the Arm Procedure.
290 @cindex @code{-matpcs} command line option, ARM
292 This option specifies that the output generated by the assembler should
293 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
294 enabled this option will cause the assembler to create an empty
295 debugging section in the object file called .arm.atpcs. Debuggers can
296 use this to determine the ABI being used by.
298 @cindex @code{-mapcs-float} command line option, ARM
300 This indicates the floating point variant of the APCS should be
301 used. In this variant floating point arguments are passed in FP
302 registers rather than integer registers.
304 @cindex @code{-mapcs-reentrant} command line option, ARM
305 @item -mapcs-reentrant
306 This indicates that the reentrant variant of the APCS should be used.
307 This variant supports position independent code.
309 @cindex @code{-mfloat-abi=} command line option, ARM
310 @item -mfloat-abi=@var{abi}
311 This option specifies that the output generated by the assembler should be
312 marked as using specified floating point ABI.
313 The following values are recognized:
319 @cindex @code{-eabi=} command line option, ARM
320 @item -meabi=@var{ver}
321 This option specifies which EABI version the produced object files should
323 The following values are recognized:
329 @cindex @code{-EB} command line option, ARM
331 This option specifies that the output generated by the assembler should
332 be marked as being encoded for a big-endian processor.
334 @cindex @code{-EL} command line option, ARM
336 This option specifies that the output generated by the assembler should
337 be marked as being encoded for a little-endian processor.
339 @cindex @code{-k} command line option, ARM
340 @cindex PIC code generation for ARM
342 This option specifies that the output of the assembler should be marked
343 as position-independent code (PIC).
345 @cindex @code{--fix-v4bx} command line option, ARM
347 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
348 the linker option of the same name.
350 @cindex @code{-mwarn-deprecated} command line option, ARM
351 @item -mwarn-deprecated
352 @itemx -mno-warn-deprecated
353 Enable or disable warnings about using deprecated options or
354 features. The default is to warn.
362 * ARM-Instruction-Set:: Instruction Set
363 * ARM-Chars:: Special Characters
364 * ARM-Regs:: Register Names
365 * ARM-Relocations:: Relocations
366 * ARM-Neon-Alignment:: NEON Alignment Specifiers
369 @node ARM-Instruction-Set
370 @subsection Instruction Set Syntax
371 Two slightly different syntaxes are support for ARM and THUMB
372 instructions. The default, @code{divided}, uses the old style where
373 ARM and THUMB instructions had their own, separate syntaxes. The new,
374 @code{unified} syntax, which can be selected via the @code{.syntax}
375 directive, and has the following main features:
379 Immediate operands do not require a @code{#} prefix.
382 The @code{IT} instruction may appear, and if it does it is validated
383 against subsequent conditional affixes. In ARM mode it does not
384 generate machine code, in THUMB mode it does.
387 For ARM instructions the conditional affixes always appear at the end
388 of the instruction. For THUMB instructions conditional affixes can be
389 used, but only inside the scope of an @code{IT} instruction.
392 All of the instructions new to the V6T2 architecture (and later) are
393 available. (Only a few such instructions can be written in the
394 @code{divided} syntax).
397 The @code{.N} and @code{.W} suffixes are recognized and honored.
400 All instructions set the flags if and only if they have an @code{s}
405 @subsection Special Characters
407 @cindex line comment character, ARM
408 @cindex ARM line comment character
409 The presence of a @samp{@@} on a line indicates the start of a comment
410 that extends to the end of the current line. If a @samp{#} appears as
411 the first character of a line, the whole line is treated as a comment.
413 @cindex line separator, ARM
414 @cindex statement separator, ARM
415 @cindex ARM line separator
416 The @samp{;} character can be used instead of a newline to separate
419 @cindex immediate character, ARM
420 @cindex ARM immediate character
421 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
423 @cindex identifiers, ARM
424 @cindex ARM identifiers
425 *TODO* Explain about /data modifier on symbols.
428 @subsection Register Names
430 @cindex ARM register names
431 @cindex register names, ARM
432 *TODO* Explain about ARM register naming, and the predefined names.
434 @node ARM-Neon-Alignment
435 @subsection NEON Alignment Specifiers
437 @cindex alignment for NEON instructions
438 Some NEON load/store instructions allow an optional address
440 The ARM documentation specifies that this is indicated by
441 @samp{@@ @var{align}}. However GAS already interprets
442 the @samp{@@} character as a "line comment" start,
443 so @samp{: @var{align}} is used instead. For example:
446 vld1.8 @{q0@}, [r0, :128]
449 @node ARM Floating Point
450 @section Floating Point
452 @cindex floating point, ARM (@sc{ieee})
453 @cindex ARM floating point (@sc{ieee})
454 The ARM family uses @sc{ieee} floating-point numbers.
456 @node ARM-Relocations
457 @subsection ARM relocation generation
459 @cindex data relocations, ARM
460 @cindex ARM data relocations
461 Specific data relocations can be generated by putting the relocation name
462 in parentheses after the symbol name. For example:
468 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
470 The following relocations are supported:
484 For compatibility with older toolchains the assembler also accepts
485 @code{(PLT)} after branch targets. This will generate the deprecated
486 @samp{R_ARM_PLT32} relocation.
488 @cindex MOVW and MOVT relocations, ARM
489 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
490 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
491 respectively. For example to load the 32-bit address of foo into r0:
494 MOVW r0, #:lower16:foo
495 MOVT r0, #:upper16:foo
499 @section ARM Machine Directives
501 @cindex machine directives, ARM
502 @cindex ARM machine directives
505 @c AAAAAAAAAAAAAAAAAAAAAAAAA
507 @cindex @code{.2byte} directive, ARM
508 @cindex @code{.4byte} directive, ARM
509 @cindex @code{.8byte} directive, ARM
510 @item .2byte @var{expression} [, @var{expression}]*
511 @itemx .4byte @var{expression} [, @var{expression}]*
512 @itemx .8byte @var{expression} [, @var{expression}]*
513 These directives write 2, 4 or 8 byte values to the output section.
515 @cindex @code{.align} directive, ARM
516 @item .align @var{expression} [, @var{expression}]
517 This is the generic @var{.align} directive. For the ARM however if the
518 first argument is zero (ie no alignment is needed) the assembler will
519 behave as if the argument had been 2 (ie pad to the next four byte
520 boundary). This is for compatibility with ARM's own assembler.
522 @cindex @code{.arch} directive, ARM
523 @item .arch @var{name}
524 Select the target architecture. Valid values for @var{name} are the same as
525 for the @option{-march} commandline option.
527 Specifying @code{.arch} clears any previously selected architecture
530 @cindex @code{.arch_extension} directive, ARM
531 @item .arch_extension @var{name}
532 Add or remove an architecture extension to the target architecture. Valid
533 values for @var{name} are the same as those accepted as architectural
534 extensions by the @option{-mcpu} commandline option.
536 @code{.arch_extension} may be used multiple times to add or remove extensions
537 incrementally to the architecture being compiled for.
539 @cindex @code{.arm} directive, ARM
541 This performs the same action as @var{.code 32}.
544 @cindex @code{.pad} directive, ARM
545 @item .pad #@var{count}
546 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
547 A positive value indicates the function prologue allocated stack space by
548 decrementing the stack pointer.
550 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
552 @cindex @code{.bss} directive, ARM
554 This directive switches to the @code{.bss} section.
556 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
558 @cindex @code{.cantunwind} directive, ARM
560 Prevents unwinding through the current function. No personality routine
561 or exception table data is required or permitted.
563 @cindex @code{.code} directive, ARM
564 @item .code @code{[16|32]}
565 This directive selects the instruction set being generated. The value 16
566 selects Thumb, with the value 32 selecting ARM.
568 @cindex @code{.cpu} directive, ARM
569 @item .cpu @var{name}
570 Select the target processor. Valid values for @var{name} are the same as
571 for the @option{-mcpu} commandline option.
573 Specifying @code{.cpu} clears any previously selected architecture
576 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
578 @cindex @code{.dn} and @code{.qn} directives, ARM
579 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
580 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
582 The @code{dn} and @code{qn} directives are used to create typed
583 and/or indexed register aliases for use in Advanced SIMD Extension
584 (Neon) instructions. The former should be used to create aliases
585 of double-precision registers, and the latter to create aliases of
586 quad-precision registers.
588 If these directives are used to create typed aliases, those aliases can
589 be used in Neon instructions instead of writing types after the mnemonic
590 or after each operand. For example:
599 This is equivalent to writing the following:
605 Aliases created using @code{dn} or @code{qn} can be destroyed using
608 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
610 @cindex @code{.eabi_attribute} directive, ARM
611 @item .eabi_attribute @var{tag}, @var{value}
612 Set the EABI object attribute @var{tag} to @var{value}.
614 The @var{tag} is either an attribute number, or one of the following:
615 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
616 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
617 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
618 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
619 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
620 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
621 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
622 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
623 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
624 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
625 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
626 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
627 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
628 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
629 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
630 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
631 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
632 @code{Tag_conformance}, @code{Tag_T2EE_use},
633 @code{Tag_Virtualization_use}
635 The @var{value} is either a @code{number}, @code{"string"}, or
636 @code{number, "string"} depending on the tag.
638 Note - the following legacy values are also accepted by @var{tag}:
639 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
640 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
642 @cindex @code{.even} directive, ARM
644 This directive aligns to an even-numbered address.
646 @cindex @code{.extend} directive, ARM
647 @cindex @code{.ldouble} directive, ARM
648 @item .extend @var{expression} [, @var{expression}]*
649 @itemx .ldouble @var{expression} [, @var{expression}]*
650 These directives write 12byte long double floating-point values to the
651 output section. These are not compatible with current ARM processors
654 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
657 @cindex @code{.fnend} directive, ARM
659 Marks the end of a function with an unwind table entry. The unwind index
660 table entry is created when this directive is processed.
662 If no personality routine has been specified then standard personality
663 routine 0 or 1 will be used, depending on the number of unwind opcodes
667 @cindex @code{.fnstart} directive, ARM
669 Marks the start of a function with an unwind table entry.
671 @cindex @code{.force_thumb} directive, ARM
673 This directive forces the selection of Thumb instructions, even if the
674 target processor does not support those instructions
676 @cindex @code{.fpu} directive, ARM
677 @item .fpu @var{name}
678 Select the floating-point unit to assemble for. Valid values for @var{name}
679 are the same as for the @option{-mfpu} commandline option.
681 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
682 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
684 @cindex @code{.handlerdata} directive, ARM
686 Marks the end of the current function, and the start of the exception table
687 entry for that function. Anything between this directive and the
688 @code{.fnend} directive will be added to the exception table entry.
690 Must be preceded by a @code{.personality} or @code{.personalityindex}
693 @c IIIIIIIIIIIIIIIIIIIIIIIIII
695 @cindex @code{.inst} directive, ARM
696 @item .inst @var{opcode} [ , @dots{} ]
697 @itemx .inst.n @var{opcode} [ , @dots{} ]
698 @itemx .inst.w @var{opcode} [ , @dots{} ]
699 Generates the instruction corresponding to the numerical value @var{opcode}.
700 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
701 specified explicitly, overriding the normal encoding rules.
703 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
704 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
705 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
707 @item .ldouble @var{expression} [, @var{expression}]*
710 @cindex @code{.ltorg} directive, ARM
712 This directive causes the current contents of the literal pool to be
713 dumped into the current section (which is assumed to be the .text
714 section) at the current location (aligned to a word boundary).
715 @code{GAS} maintains a separate literal pool for each section and each
716 sub-section. The @code{.ltorg} directive will only affect the literal
717 pool of the current section and sub-section. At the end of assembly
718 all remaining, un-empty literal pools will automatically be dumped.
720 Note - older versions of @code{GAS} would dump the current literal
721 pool any time a section change occurred. This is no longer done, since
722 it prevents accurate control of the placement of literal pools.
724 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
726 @cindex @code{.movsp} directive, ARM
727 @item .movsp @var{reg} [, #@var{offset}]
728 Tell the unwinder that @var{reg} contains an offset from the current
729 stack pointer. If @var{offset} is not specified then it is assumed to be
732 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
733 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
735 @cindex @code{.object_arch} directive, ARM
736 @item .object_arch @var{name}
737 Override the architecture recorded in the EABI object attribute section.
738 Valid values for @var{name} are the same as for the @code{.arch} directive.
739 Typically this is useful when code uses runtime detection of CPU features.
741 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
743 @cindex @code{.packed} directive, ARM
744 @item .packed @var{expression} [, @var{expression}]*
745 This directive writes 12-byte packed floating-point values to the
746 output section. These are not compatible with current ARM processors
749 @cindex @code{.pad} directive, ARM
750 @item .pad #@var{count}
751 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
752 A positive value indicates the function prologue allocated stack space by
753 decrementing the stack pointer.
755 @cindex @code{.personality} directive, ARM
756 @item .personality @var{name}
757 Sets the personality routine for the current function to @var{name}.
759 @cindex @code{.personalityindex} directive, ARM
760 @item .personalityindex @var{index}
761 Sets the personality routine for the current function to the EABI standard
762 routine number @var{index}
764 @cindex @code{.pool} directive, ARM
766 This is a synonym for .ltorg.
768 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
769 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
771 @cindex @code{.req} directive, ARM
772 @item @var{name} .req @var{register name}
773 This creates an alias for @var{register name} called @var{name}. For
780 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
783 @cindex @code{.save} directive, ARM
784 @item .save @var{reglist}
785 Generate unwinder annotations to restore the registers in @var{reglist}.
786 The format of @var{reglist} is the same as the corresponding store-multiple
790 @exdent @emph{core registers}
791 .save @{r4, r5, r6, lr@}
792 stmfd sp!, @{r4, r5, r6, lr@}
793 @exdent @emph{FPA registers}
796 @exdent @emph{VFP registers}
797 .save @{d8, d9, d10@}
798 fstmdx sp!, @{d8, d9, d10@}
799 @exdent @emph{iWMMXt registers}
801 wstrd wr11, [sp, #-8]!
802 wstrd wr10, [sp, #-8]!
805 wstrd wr11, [sp, #-8]!
807 wstrd wr10, [sp, #-8]!
811 @cindex @code{.setfp} directive, ARM
812 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
813 Make all unwinder annotations relative to a frame pointer. Without this
814 the unwinder will use offsets from the stack pointer.
816 The syntax of this directive is the same as the @code{add} or @code{mov}
817 instruction used to set the frame pointer. @var{spreg} must be either
818 @code{sp} or mentioned in a previous @code{.movsp} directive.
828 @cindex @code{.secrel32} directive, ARM
829 @item .secrel32 @var{expression} [, @var{expression}]*
830 This directive emits relocations that evaluate to the section-relative
831 offset of each expression's symbol. This directive is only supported
834 @cindex @code{.syntax} directive, ARM
835 @item .syntax [@code{unified} | @code{divided}]
836 This directive sets the Instruction Set Syntax as described in the
837 @ref{ARM-Instruction-Set} section.
839 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
841 @cindex @code{.thumb} directive, ARM
843 This performs the same action as @var{.code 16}.
845 @cindex @code{.thumb_func} directive, ARM
847 This directive specifies that the following symbol is the name of a
848 Thumb encoded function. This information is necessary in order to allow
849 the assembler and linker to generate correct code for interworking
850 between Arm and Thumb instructions and should be used even if
851 interworking is not going to be performed. The presence of this
852 directive also implies @code{.thumb}
854 This directive is not neccessary when generating EABI objects. On these
855 targets the encoding is implicit when generating Thumb code.
857 @cindex @code{.thumb_set} directive, ARM
859 This performs the equivalent of a @code{.set} directive in that it
860 creates a symbol which is an alias for another symbol (possibly not yet
861 defined). This directive also has the added property in that it marks
862 the aliased symbol as being a thumb function entry point, in the same
863 way that the @code{.thumb_func} directive does.
865 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
867 @cindex @code{.unreq} directive, ARM
868 @item .unreq @var{alias-name}
869 This undefines a register alias which was previously defined using the
870 @code{req}, @code{dn} or @code{qn} directives. For example:
877 An error occurs if the name is undefined. Note - this pseudo op can
878 be used to delete builtin in register name aliases (eg 'r0'). This
879 should only be done if it is really necessary.
881 @cindex @code{.unwind_raw} directive, ARM
882 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
883 Insert one of more arbitary unwind opcode bytes, which are known to adjust
884 the stack pointer by @var{offset} bytes.
886 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
889 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
891 @cindex @code{.vsave} directive, ARM
892 @item .vsave @var{vfp-reglist}
893 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
894 using FLDMD. Also works for VFPv3 registers
895 that are to be restored using VLDM.
896 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
900 @exdent @emph{VFP registers}
901 .vsave @{d8, d9, d10@}
902 fstmdd sp!, @{d8, d9, d10@}
903 @exdent @emph{VFPv3 registers}
904 .vsave @{d15, d16, d17@}
905 vstm sp!, @{d15, d16, d17@}
908 Since FLDMX and FSTMX are now deprecated, this directive should be
909 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
911 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
912 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
913 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
914 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
922 @cindex opcodes for ARM
923 @code{@value{AS}} implements all the standard ARM opcodes. It also
924 implements several pseudo opcodes, including several synthetic load
929 @cindex @code{NOP} pseudo op, ARM
935 This pseudo op will always evaluate to a legal ARM instruction that does
936 nothing. Currently it will evaluate to MOV r0, r0.
938 @cindex @code{LDR reg,=<label>} pseudo op, ARM
941 ldr <register> , = <expression>
944 If expression evaluates to a numeric constant then a MOV or MVN
945 instruction will be used in place of the LDR instruction, if the
946 constant can be generated by either of these instructions. Otherwise
947 the constant will be placed into the nearest literal pool (if it not
948 already there) and a PC relative LDR instruction will be generated.
950 @cindex @code{ADR reg,<label>} pseudo op, ARM
953 adr <register> <label>
956 This instruction will load the address of @var{label} into the indicated
957 register. The instruction will evaluate to a PC relative ADD or SUB
958 instruction depending upon where the label is located. If the label is
959 out of range, or if it is not defined in the same file (and section) as
960 the ADR instruction, then an error will be generated. This instruction
961 will not make use of the literal pool.
963 @cindex @code{ADRL reg,<label>} pseudo op, ARM
966 adrl <register> <label>
969 This instruction will load the address of @var{label} into the indicated
970 register. The instruction will evaluate to one or two PC relative ADD
971 or SUB instructions depending upon where the label is located. If a
972 second instruction is not needed a NOP instruction will be generated in
973 its place, so that this instruction is always 8 bytes long.
975 If the label is out of range, or if it is not defined in the same file
976 (and section) as the ADRL instruction, then an error will be generated.
977 This instruction will not make use of the literal pool.
981 For information on the ARM or Thumb instruction sets, see @cite{ARM
982 Software Development Toolkit Reference Manual}, Advanced RISC Machines
985 @node ARM Mapping Symbols
986 @section Mapping Symbols
988 The ARM ELF specification requires that special symbols be inserted
989 into object files to mark certain features:
995 At the start of a region of code containing ARM instructions.
999 At the start of a region of code containing THUMB instructions.
1003 At the start of a region of data.
1007 The assembler will automatically insert these symbols for you - there
1008 is no need to code them yourself. Support for tagging symbols ($b,
1009 $f, $p and $m) which is also mentioned in the current ARM ELF
1010 specification is not implemented. This is because they have been
1011 dropped from the new EABI and so tools cannot rely upon their
1014 @node ARM Unwinding Tutorial
1017 The ABI for the ARM Architecture specifies a standard format for
1018 exception unwind information. This information is used when an
1019 exception is thrown to determine where control should be transferred.
1020 In particular, the unwind information is used to determine which
1021 function called the function that threw the exception, and which
1022 function called that one, and so forth. This information is also used
1023 to restore the values of callee-saved registers in the function
1024 catching the exception.
1026 If you are writing functions in assembly code, and those functions
1027 call other functions that throw exceptions, you must use assembly
1028 pseudo ops to ensure that appropriate exception unwind information is
1029 generated. Otherwise, if one of the functions called by your assembly
1030 code throws an exception, the run-time library will be unable to
1031 unwind the stack through your assembly code and your program will not
1034 To illustrate the use of these pseudo ops, we will examine the code
1035 that G++ generates for the following C++ input:
1038 void callee (int *);
1049 This example does not show how to throw or catch an exception from
1050 assembly code. That is a much more complex operation and should
1051 always be done in a high-level language, such as C++, that directly
1052 supports exceptions.
1054 The code generated by one particular version of G++ when compiling the
1061 @ Function supports interworking.
1062 @ args = 0, pretend = 0, frame = 8
1063 @ frame_needed = 1, uses_anonymous_args = 0
1085 Of course, the sequence of instructions varies based on the options
1086 you pass to GCC and on the version of GCC in use. The exact
1087 instructions are not important since we are focusing on the pseudo ops
1088 that are used to generate unwind information.
1090 An important assumption made by the unwinder is that the stack frame
1091 does not change during the body of the function. In particular, since
1092 we assume that the assembly code does not itself throw an exception,
1093 the only point where an exception can be thrown is from a call, such
1094 as the @code{bl} instruction above. At each call site, the same saved
1095 registers (including @code{lr}, which indicates the return address)
1096 must be located in the same locations relative to the frame pointer.
1098 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1099 op appears immediately before the first instruction of the function
1100 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1101 op appears immediately after the last instruction of the function.
1102 These pseudo ops specify the range of the function.
1104 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1105 @code{.pad}) matters; their exact locations are irrelevant. In the
1106 example above, the compiler emits the pseudo ops with particular
1107 instructions. That makes it easier to understand the code, but it is
1108 not required for correctness. It would work just as well to emit all
1109 of the pseudo ops other than @code{.fnend} in the same order, but
1110 immediately after @code{.fnstart}.
1112 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1113 indicates registers that have been saved to the stack so that they can
1114 be restored before the function returns. The argument to the
1115 @code{.save} pseudo op is a list of registers to save. If a register
1116 is ``callee-saved'' (as specified by the ABI) and is modified by the
1117 function you are writing, then your code must save the value before it
1118 is modified and restore the original value before the function
1119 returns. If an exception is thrown, the run-time library restores the
1120 values of these registers from their locations on the stack before
1121 returning control to the exception handler. (Of course, if an
1122 exception is not thrown, the function that contains the @code{.save}
1123 pseudo op restores these registers in the function epilogue, as is
1124 done with the @code{ldmfd} instruction above.)
1126 You do not have to save callee-saved registers at the very beginning
1127 of the function and you do not need to use the @code{.save} pseudo op
1128 immediately following the point at which the registers are saved.
1129 However, if you modify a callee-saved register, you must save it on
1130 the stack before modifying it and before calling any functions which
1131 might throw an exception. And, you must use the @code{.save} pseudo
1132 op to indicate that you have done so.
1134 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1135 modification of the stack pointer that does not save any registers.
1136 The argument is the number of bytes (in decimal) that are subtracted
1137 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1138 subtracting from the stack pointer increases the size of the stack.)
1140 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1141 indicates the register that contains the frame pointer. The first
1142 argument is the register that is set, which is typically @code{fp}.
1143 The second argument indicates the register from which the frame
1144 pointer takes its value. The third argument, if present, is the value
1145 (in decimal) added to the register specified by the second argument to
1146 compute the value of the frame pointer. You should not modify the
1147 frame pointer in the body of the function.
1149 If you do not use a frame pointer, then you should not use the
1150 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1151 should avoid modifying the stack pointer outside of the function
1152 prologue. Otherwise, the run-time library will be unable to find
1153 saved registers when it is unwinding the stack.
1155 The pseudo ops described above are sufficient for writing assembly
1156 code that calls functions which may throw exceptions. If you need to
1157 know more about the object-file format used to represent unwind
1158 information, you may consult the @cite{Exception Handling ABI for the
1159 ARM Architecture} available from @uref{http://infocenter.arm.com}.