1 @c Copyright (C) 1991-2018 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78 byte nop (0x90) is explicitly specified as the fill byte for alignment.
80 @cindex @samp{--divide} option, i386
82 On SVR4-derived platforms, the character @samp{/} is treated as a comment
83 character, which means that it cannot be used in expressions. The
84 @samp{--divide} option turns @samp{/} into a normal character. This does
85 not disable @samp{/} at the beginning of a line starting a comment, or
86 affect using @samp{#} for starting a comment.
88 @cindex @samp{-march=} option, i386
89 @cindex @samp{-march=} option, x86-64
90 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91 This option specifies the target processor. The assembler will
92 issue an error message if an attempt is made to assemble an instruction
93 which will not execute on the target processor. The following
94 processor names are recognized:
132 In addition to the basic instruction set, the assembler can be told to
133 accept various extension mnemonics. For example,
134 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
135 @var{vmx}. The following extensions are currently supported:
191 @code{avx512_4fmaps},
192 @code{avx512_4vnniw},
193 @code{avx512_vpopcntdq},
196 @code{avx512_bitalg},
206 @code{noavx512_4fmaps},
207 @code{noavx512_4vnniw},
208 @code{noavx512_vpopcntdq},
209 @code{noavx512_vbmi2},
210 @code{noavx512_vnni},
211 @code{noavx512_bitalg},
252 Note that rather than extending a basic instruction set, the extension
253 mnemonics starting with @code{no} revoke the respective functionality.
255 When the @code{.arch} directive is used with @option{-march}, the
256 @code{.arch} directive will take precedent.
258 @cindex @samp{-mtune=} option, i386
259 @cindex @samp{-mtune=} option, x86-64
260 @item -mtune=@var{CPU}
261 This option specifies a processor to optimize for. When used in
262 conjunction with the @option{-march} option, only instructions
263 of the processor specified by the @option{-march} option will be
266 Valid @var{CPU} values are identical to the processor list of
267 @option{-march=@var{CPU}}.
269 @cindex @samp{-msse2avx} option, i386
270 @cindex @samp{-msse2avx} option, x86-64
272 This option specifies that the assembler should encode SSE instructions
275 @cindex @samp{-msse-check=} option, i386
276 @cindex @samp{-msse-check=} option, x86-64
277 @item -msse-check=@var{none}
278 @itemx -msse-check=@var{warning}
279 @itemx -msse-check=@var{error}
280 These options control if the assembler should check SSE instructions.
281 @option{-msse-check=@var{none}} will make the assembler not to check SSE
282 instructions, which is the default. @option{-msse-check=@var{warning}}
283 will make the assembler issue a warning for any SSE instruction.
284 @option{-msse-check=@var{error}} will make the assembler issue an error
285 for any SSE instruction.
287 @cindex @samp{-mavxscalar=} option, i386
288 @cindex @samp{-mavxscalar=} option, x86-64
289 @item -mavxscalar=@var{128}
290 @itemx -mavxscalar=@var{256}
291 These options control how the assembler should encode scalar AVX
292 instructions. @option{-mavxscalar=@var{128}} will encode scalar
293 AVX instructions with 128bit vector length, which is the default.
294 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
295 with 256bit vector length.
297 @cindex @samp{-mevexlig=} option, i386
298 @cindex @samp{-mevexlig=} option, x86-64
299 @item -mevexlig=@var{128}
300 @itemx -mevexlig=@var{256}
301 @itemx -mevexlig=@var{512}
302 These options control how the assembler should encode length-ignored
303 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
304 EVEX instructions with 128bit vector length, which is the default.
305 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
306 encode LIG EVEX instructions with 256bit and 512bit vector length,
309 @cindex @samp{-mevexwig=} option, i386
310 @cindex @samp{-mevexwig=} option, x86-64
311 @item -mevexwig=@var{0}
312 @itemx -mevexwig=@var{1}
313 These options control how the assembler should encode w-ignored (WIG)
314 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
315 EVEX instructions with evex.w = 0, which is the default.
316 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
319 @cindex @samp{-mmnemonic=} option, i386
320 @cindex @samp{-mmnemonic=} option, x86-64
321 @item -mmnemonic=@var{att}
322 @itemx -mmnemonic=@var{intel}
323 This option specifies instruction mnemonic for matching instructions.
324 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
327 @cindex @samp{-msyntax=} option, i386
328 @cindex @samp{-msyntax=} option, x86-64
329 @item -msyntax=@var{att}
330 @itemx -msyntax=@var{intel}
331 This option specifies instruction syntax when processing instructions.
332 The @code{.att_syntax} and @code{.intel_syntax} directives will
335 @cindex @samp{-mnaked-reg} option, i386
336 @cindex @samp{-mnaked-reg} option, x86-64
338 This option specifies that registers don't require a @samp{%} prefix.
339 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
341 @cindex @samp{-madd-bnd-prefix} option, i386
342 @cindex @samp{-madd-bnd-prefix} option, x86-64
343 @item -madd-bnd-prefix
344 This option forces the assembler to add BND prefix to all branches, even
345 if such prefix was not explicitly specified in the source code.
347 @cindex @samp{-mshared} option, i386
348 @cindex @samp{-mshared} option, x86-64
350 On ELF target, the assembler normally optimizes out non-PLT relocations
351 against defined non-weak global branch targets with default visibility.
352 The @samp{-mshared} option tells the assembler to generate code which
353 may go into a shared library where all non-weak global branch targets
354 with default visibility can be preempted. The resulting code is
355 slightly bigger. This option only affects the handling of branch
358 @cindex @samp{-mbig-obj} option, x86-64
360 On x86-64 PE/COFF target this option forces the use of big object file
361 format, which allows more than 32768 sections.
363 @cindex @samp{-momit-lock-prefix=} option, i386
364 @cindex @samp{-momit-lock-prefix=} option, x86-64
365 @item -momit-lock-prefix=@var{no}
366 @itemx -momit-lock-prefix=@var{yes}
367 These options control how the assembler should encode lock prefix.
368 This option is intended as a workaround for processors, that fail on
369 lock prefix. This option can only be safely used with single-core,
370 single-thread computers
371 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
372 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
373 which is the default.
375 @cindex @samp{-mfence-as-lock-add=} option, i386
376 @cindex @samp{-mfence-as-lock-add=} option, x86-64
377 @item -mfence-as-lock-add=@var{no}
378 @itemx -mfence-as-lock-add=@var{yes}
379 These options control how the assembler should encode lfence, mfence and
381 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
382 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
383 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
384 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
385 sfence as usual, which is the default.
387 @cindex @samp{-mrelax-relocations=} option, i386
388 @cindex @samp{-mrelax-relocations=} option, x86-64
389 @item -mrelax-relocations=@var{no}
390 @itemx -mrelax-relocations=@var{yes}
391 These options control whether the assembler should generate relax
392 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
393 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
394 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
395 @option{-mrelax-relocations=@var{no}} will not generate relax
396 relocations. The default can be controlled by a configure option
397 @option{--enable-x86-relax-relocations}.
399 @cindex @samp{-mevexrcig=} option, i386
400 @cindex @samp{-mevexrcig=} option, x86-64
401 @item -mevexrcig=@var{rne}
402 @itemx -mevexrcig=@var{rd}
403 @itemx -mevexrcig=@var{ru}
404 @itemx -mevexrcig=@var{rz}
405 These options control how the assembler should encode SAE-only
406 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
407 of EVEX instruction with 00, which is the default.
408 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
409 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
410 with 01, 10 and 11 RC bits, respectively.
412 @cindex @samp{-mamd64} option, x86-64
413 @cindex @samp{-mintel64} option, x86-64
416 This option specifies that the assembler should accept only AMD64 or
417 Intel64 ISA in 64-bit mode. The default is to accept both.
419 @cindex @samp{-O0} option, i386
420 @cindex @samp{-O0} option, x86-64
421 @cindex @samp{-O} option, i386
422 @cindex @samp{-O} option, x86-64
423 @cindex @samp{-O1} option, i386
424 @cindex @samp{-O1} option, x86-64
425 @cindex @samp{-O2} option, i386
426 @cindex @samp{-O2} option, x86-64
427 @cindex @samp{-Os} option, i386
428 @cindex @samp{-Os} option, x86-64
429 @item -O0 | -O | -O1 | -O2 | -Os
430 Optimize instruction encoding with smaller instruction size. @samp{-O}
431 and @samp{-O1} encode 64-bit register load instructions with 64-bit
432 immediate as 32-bit register load instructions with 31-bit or 32-bits
433 immediates and encode 64-bit register clearing instructions with 32-bit
434 register clearing instructions. @samp{-O2} includes @samp{-O1}
435 optimization plus encodes 256-bit and 512-bit vector register clearing
436 instructions with 128-bit vector register clearing instructions.
437 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
438 and 64-bit register tests with immediate as 8-bit register test with
439 immediate. @samp{-O0} turns off this optimization.
444 @node i386-Directives
445 @section x86 specific Directives
447 @cindex machine directives, x86
448 @cindex x86 machine directives
451 @cindex @code{lcomm} directive, COFF
452 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
453 Reserve @var{length} (an absolute expression) bytes for a local common
454 denoted by @var{symbol}. The section and value of @var{symbol} are
455 those of the new local common. The addresses are allocated in the bss
456 section, so that at run-time the bytes start off zeroed. Since
457 @var{symbol} is not declared global, it is normally not visible to
458 @code{@value{LD}}. The optional third parameter, @var{alignment},
459 specifies the desired alignment of the symbol in the bss section.
461 This directive is only available for COFF based x86 targets.
463 @cindex @code{largecomm} directive, ELF
464 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
465 This directive behaves in the same way as the @code{comm} directive
466 except that the data is placed into the @var{.lbss} section instead of
467 the @var{.bss} section @ref{Comm}.
469 The directive is intended to be used for data which requires a large
470 amount of space, and it is only available for ELF based x86_64
473 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
478 @section i386 Syntactical Considerations
480 * i386-Variations:: AT&T Syntax versus Intel Syntax
481 * i386-Chars:: Special Characters
484 @node i386-Variations
485 @subsection AT&T Syntax versus Intel Syntax
487 @cindex i386 intel_syntax pseudo op
488 @cindex intel_syntax pseudo op, i386
489 @cindex i386 att_syntax pseudo op
490 @cindex att_syntax pseudo op, i386
491 @cindex i386 syntax compatibility
492 @cindex syntax compatibility, i386
493 @cindex x86-64 intel_syntax pseudo op
494 @cindex intel_syntax pseudo op, x86-64
495 @cindex x86-64 att_syntax pseudo op
496 @cindex att_syntax pseudo op, x86-64
497 @cindex x86-64 syntax compatibility
498 @cindex syntax compatibility, x86-64
500 @code{@value{AS}} now supports assembly using Intel assembler syntax.
501 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
502 back to the usual AT&T mode for compatibility with the output of
503 @code{@value{GCC}}. Either of these directives may have an optional
504 argument, @code{prefix}, or @code{noprefix} specifying whether registers
505 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
506 different from Intel syntax. We mention these differences because
507 almost all 80386 documents use Intel syntax. Notable differences
508 between the two syntaxes are:
510 @cindex immediate operands, i386
511 @cindex i386 immediate operands
512 @cindex register operands, i386
513 @cindex i386 register operands
514 @cindex jump/call operands, i386
515 @cindex i386 jump/call operands
516 @cindex operand delimiters, i386
518 @cindex immediate operands, x86-64
519 @cindex x86-64 immediate operands
520 @cindex register operands, x86-64
521 @cindex x86-64 register operands
522 @cindex jump/call operands, x86-64
523 @cindex x86-64 jump/call operands
524 @cindex operand delimiters, x86-64
527 AT&T immediate operands are preceded by @samp{$}; Intel immediate
528 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
529 AT&T register operands are preceded by @samp{%}; Intel register operands
530 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
531 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
533 @cindex i386 source, destination operands
534 @cindex source, destination operands; i386
535 @cindex x86-64 source, destination operands
536 @cindex source, destination operands; x86-64
538 AT&T and Intel syntax use the opposite order for source and destination
539 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
540 @samp{source, dest} convention is maintained for compatibility with
541 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
542 instructions with 2 immediate operands, such as the @samp{enter}
543 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
545 @cindex mnemonic suffixes, i386
546 @cindex sizes operands, i386
547 @cindex i386 size suffixes
548 @cindex mnemonic suffixes, x86-64
549 @cindex sizes operands, x86-64
550 @cindex x86-64 size suffixes
552 In AT&T syntax the size of memory operands is determined from the last
553 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
554 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
555 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
556 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
557 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
558 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
561 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
562 instruction with the 64-bit displacement or immediate operand.
564 @cindex return instructions, i386
565 @cindex i386 jump, call, return
566 @cindex return instructions, x86-64
567 @cindex x86-64 jump, call, return
569 Immediate form long jumps and calls are
570 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
572 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
574 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
575 @samp{ret far @var{stack-adjust}}.
577 @cindex sections, i386
578 @cindex i386 sections
579 @cindex sections, x86-64
580 @cindex x86-64 sections
582 The AT&T assembler does not provide support for multiple section
583 programs. Unix style systems expect all programs to be single sections.
587 @subsection Special Characters
589 @cindex line comment character, i386
590 @cindex i386 line comment character
591 The presence of a @samp{#} appearing anywhere on a line indicates the
592 start of a comment that extends to the end of that line.
594 If a @samp{#} appears as the first character of a line then the whole
595 line is treated as a comment, but in this case the line can also be a
596 logical line number directive (@pxref{Comments}) or a preprocessor
597 control command (@pxref{Preprocessing}).
599 If the @option{--divide} command line option has not been specified
600 then the @samp{/} character appearing anywhere on a line also
601 introduces a line comment.
603 @cindex line separator, i386
604 @cindex statement separator, i386
605 @cindex i386 line separator
606 The @samp{;} character can be used to separate statements on the same
610 @section i386-Mnemonics
611 @subsection Instruction Naming
613 @cindex i386 instruction naming
614 @cindex instruction naming, i386
615 @cindex x86-64 instruction naming
616 @cindex instruction naming, x86-64
618 Instruction mnemonics are suffixed with one character modifiers which
619 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
620 and @samp{q} specify byte, word, long and quadruple word operands. If
621 no suffix is specified by an instruction then @code{@value{AS}} tries to
622 fill in the missing suffix based on the destination register operand
623 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
624 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
625 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
626 assembler which assumes that a missing mnemonic suffix implies long
627 operand size. (This incompatibility does not affect compiler output
628 since compilers always explicitly specify the mnemonic suffix.)
630 Almost all instructions have the same names in AT&T and Intel format.
631 There are a few exceptions. The sign extend and zero extend
632 instructions need two sizes to specify them. They need a size to
633 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
634 is accomplished by using two instruction mnemonic suffixes in AT&T
635 syntax. Base names for sign extend and zero extend are
636 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
637 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
638 are tacked on to this base name, the @emph{from} suffix before the
639 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
640 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
641 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
642 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
643 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
646 @cindex encoding options, i386
647 @cindex encoding options, x86-64
649 Different encoding options can be specified via pseudo prefixes:
653 @samp{@{disp8@}} -- prefer 8-bit displacement.
656 @samp{@{disp32@}} -- prefer 32-bit displacement.
659 @samp{@{load@}} -- prefer load-form instruction.
662 @samp{@{store@}} -- prefer store-form instruction.
665 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
668 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
671 @samp{@{evex@}} -- encode with EVEX prefix.
674 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
675 instructions (x86-64 only). Note that this differs from the @samp{rex}
676 prefix which generates REX prefix unconditionally.
679 @samp{@{nooptimize@}} -- disable instruction size optimization.
682 @cindex conversion instructions, i386
683 @cindex i386 conversion instructions
684 @cindex conversion instructions, x86-64
685 @cindex x86-64 conversion instructions
686 The Intel-syntax conversion instructions
690 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
693 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
696 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
699 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
702 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
706 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
707 @samp{%rdx:%rax} (x86-64 only),
711 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
712 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
715 @cindex jump instructions, i386
716 @cindex call instructions, i386
717 @cindex jump instructions, x86-64
718 @cindex call instructions, x86-64
719 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
720 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
723 @subsection AT&T Mnemonic versus Intel Mnemonic
725 @cindex i386 mnemonic compatibility
726 @cindex mnemonic compatibility, i386
728 @code{@value{AS}} supports assembly using Intel mnemonic.
729 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
730 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
731 syntax for compatibility with the output of @code{@value{GCC}}.
732 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
733 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
734 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
735 assembler with different mnemonics from those in Intel IA32 specification.
736 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
739 @section Register Naming
741 @cindex i386 registers
742 @cindex registers, i386
743 @cindex x86-64 registers
744 @cindex registers, x86-64
745 Register operands are always prefixed with @samp{%}. The 80386 registers
750 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
751 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
752 frame pointer), and @samp{%esp} (the stack pointer).
755 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
756 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
759 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
760 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
761 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
762 @samp{%cx}, and @samp{%dx})
765 the 6 section registers @samp{%cs} (code section), @samp{%ds}
766 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
770 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
771 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
774 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
775 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
778 the 2 test registers @samp{%tr6} and @samp{%tr7}.
781 the 8 floating point register stack @samp{%st} or equivalently
782 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
783 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
784 These registers are overloaded by 8 MMX registers @samp{%mm0},
785 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
786 @samp{%mm6} and @samp{%mm7}.
789 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
790 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
793 The AMD x86-64 architecture extends the register set by:
797 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
798 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
799 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
803 the 8 extended registers @samp{%r8}--@samp{%r15}.
806 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
809 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
812 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
815 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
818 the 8 debug registers: @samp{%db8}--@samp{%db15}.
821 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
824 With the AVX extensions more registers were made available:
829 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
830 available in 32-bit mode). The bottom 128 bits are overlaid with the
831 @samp{xmm0}--@samp{xmm15} registers.
835 The AVX2 extensions made in 64-bit mode more registers available:
840 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
841 registers @samp{%ymm16}--@samp{%ymm31}.
845 The AVX512 extensions added the following registers:
850 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
851 available in 32-bit mode). The bottom 128 bits are overlaid with the
852 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
853 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
856 the 8 mask registers @samp{%k0}--@samp{%k7}.
861 @section Instruction Prefixes
863 @cindex i386 instruction prefixes
864 @cindex instruction prefixes, i386
865 @cindex prefixes, i386
866 Instruction prefixes are used to modify the following instruction. They
867 are used to repeat string instructions, to provide section overrides, to
868 perform bus lock operations, and to change operand and address sizes.
869 (Most instructions that normally operate on 32-bit operands will use
870 16-bit operands if the instruction has an ``operand size'' prefix.)
871 Instruction prefixes are best written on the same line as the instruction
872 they act upon. For example, the @samp{scas} (scan string) instruction is
876 repne scas %es:(%edi),%al
879 You may also place prefixes on the lines immediately preceding the
880 instruction, but this circumvents checks that @code{@value{AS}} does
881 with prefixes, and will not work with all prefixes.
883 Here is a list of instruction prefixes:
885 @cindex section override prefixes, i386
888 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
889 @samp{fs}, @samp{gs}. These are automatically added by specifying
890 using the @var{section}:@var{memory-operand} form for memory references.
892 @cindex size prefixes, i386
894 Operand/Address size prefixes @samp{data16} and @samp{addr16}
895 change 32-bit operands/addresses into 16-bit operands/addresses,
896 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
897 @code{.code16} section) into 32-bit operands/addresses. These prefixes
898 @emph{must} appear on the same line of code as the instruction they
899 modify. For example, in a 16-bit @code{.code16} section, you might
906 @cindex bus lock prefixes, i386
907 @cindex inhibiting interrupts, i386
909 The bus lock prefix @samp{lock} inhibits interrupts during execution of
910 the instruction it precedes. (This is only valid with certain
911 instructions; see a 80386 manual for details).
913 @cindex coprocessor wait, i386
915 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
916 complete the current instruction. This should never be needed for the
917 80386/80387 combination.
919 @cindex repeat prefixes, i386
921 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
922 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
923 times if the current address size is 16-bits).
924 @cindex REX prefixes, i386
926 The @samp{rex} family of prefixes is used by x86-64 to encode
927 extensions to i386 instruction set. The @samp{rex} prefix has four
928 bits --- an operand size overwrite (@code{64}) used to change operand size
929 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
932 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
933 instruction emits @samp{rex} prefix with all the bits set. By omitting
934 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
935 prefixes as well. Normally, there is no need to write the prefixes
936 explicitly, since gas will automatically generate them based on the
937 instruction operands.
941 @section Memory References
943 @cindex i386 memory references
944 @cindex memory references, i386
945 @cindex x86-64 memory references
946 @cindex memory references, x86-64
947 An Intel syntax indirect memory reference of the form
950 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
954 is translated into the AT&T syntax
957 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
961 where @var{base} and @var{index} are the optional 32-bit base and
962 index registers, @var{disp} is the optional displacement, and
963 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
964 to calculate the address of the operand. If no @var{scale} is
965 specified, @var{scale} is taken to be 1. @var{section} specifies the
966 optional section register for the memory operand, and may override the
967 default section register (see a 80386 manual for section register
968 defaults). Note that section overrides in AT&T syntax @emph{must}
969 be preceded by a @samp{%}. If you specify a section override which
970 coincides with the default section register, @code{@value{AS}} does @emph{not}
971 output any section register override prefixes to assemble the given
972 instruction. Thus, section overrides can be specified to emphasize which
973 section register is used for a given memory operand.
975 Here are some examples of Intel and AT&T style memory references:
978 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
979 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
980 missing, and the default section is used (@samp{%ss} for addressing with
981 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
983 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
984 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
985 @samp{foo}. All other fields are missing. The section register here
986 defaults to @samp{%ds}.
988 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
989 This uses the value pointed to by @samp{foo} as a memory operand.
990 Note that @var{base} and @var{index} are both missing, but there is only
991 @emph{one} @samp{,}. This is a syntactic exception.
993 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
994 This selects the contents of the variable @samp{foo} with section
995 register @var{section} being @samp{%gs}.
998 Absolute (as opposed to PC relative) call and jump operands must be
999 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1000 always chooses PC relative addressing for jump/call labels.
1002 Any instruction that has a memory operand, but no register operand,
1003 @emph{must} specify its size (byte, word, long, or quadruple) with an
1004 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1007 The x86-64 architecture adds an RIP (instruction pointer relative)
1008 addressing. This addressing mode is specified by using @samp{rip} as a
1009 base register. Only constant offsets are valid. For example:
1012 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1013 Points to the address 1234 bytes past the end of the current
1016 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1017 Points to the @code{symbol} in RIP relative way, this is shorter than
1018 the default absolute addressing.
1021 Other addressing modes remain unchanged in x86-64 architecture, except
1022 registers used are 64-bit instead of 32-bit.
1025 @section Handling of Jump Instructions
1027 @cindex jump optimization, i386
1028 @cindex i386 jump optimization
1029 @cindex jump optimization, x86-64
1030 @cindex x86-64 jump optimization
1031 Jump instructions are always optimized to use the smallest possible
1032 displacements. This is accomplished by using byte (8-bit) displacement
1033 jumps whenever the target is sufficiently close. If a byte displacement
1034 is insufficient a long displacement is used. We do not support
1035 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1036 instruction with the @samp{data16} instruction prefix), since the 80386
1037 insists upon masking @samp{%eip} to 16 bits after the word displacement
1038 is added. (See also @pxref{i386-Arch})
1040 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1041 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1042 displacements, so that if you use these instructions (@code{@value{GCC}} does
1043 not use them) you may get an error message (and incorrect code). The AT&T
1044 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1055 @section Floating Point
1057 @cindex i386 floating point
1058 @cindex floating point, i386
1059 @cindex x86-64 floating point
1060 @cindex floating point, x86-64
1061 All 80387 floating point types except packed BCD are supported.
1062 (BCD support may be added without much difficulty). These data
1063 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1064 double (64-bit), and extended (80-bit) precision floating point.
1065 Each supported type has an instruction mnemonic suffix and a constructor
1066 associated with it. Instruction mnemonic suffixes specify the operand's
1067 data type. Constructors build these data types into memory.
1069 @cindex @code{float} directive, i386
1070 @cindex @code{single} directive, i386
1071 @cindex @code{double} directive, i386
1072 @cindex @code{tfloat} directive, i386
1073 @cindex @code{float} directive, x86-64
1074 @cindex @code{single} directive, x86-64
1075 @cindex @code{double} directive, x86-64
1076 @cindex @code{tfloat} directive, x86-64
1079 Floating point constructors are @samp{.float} or @samp{.single},
1080 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1081 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1082 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1083 only supports this format via the @samp{fldt} (load 80-bit real to stack
1084 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1086 @cindex @code{word} directive, i386
1087 @cindex @code{long} directive, i386
1088 @cindex @code{int} directive, i386
1089 @cindex @code{quad} directive, i386
1090 @cindex @code{word} directive, x86-64
1091 @cindex @code{long} directive, x86-64
1092 @cindex @code{int} directive, x86-64
1093 @cindex @code{quad} directive, x86-64
1095 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1096 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1097 corresponding instruction mnemonic suffixes are @samp{s} (single),
1098 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1099 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1100 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1101 stack) instructions.
1104 Register to register operations should not use instruction mnemonic suffixes.
1105 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1106 wrote @samp{fst %st, %st(1)}, since all register to register operations
1107 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1108 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1109 then stores the result in the 4 byte location @samp{mem})
1112 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1115 @cindex 3DNow!, i386
1118 @cindex 3DNow!, x86-64
1119 @cindex SIMD, x86-64
1121 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1122 instructions for integer data), available on Intel's Pentium MMX
1123 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1124 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1125 instruction set (SIMD instructions for 32-bit floating point data)
1126 available on AMD's K6-2 processor and possibly others in the future.
1128 Currently, @code{@value{AS}} does not support Intel's floating point
1131 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1132 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1133 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1134 floating point values. The MMX registers cannot be used at the same time
1135 as the floating point stack.
1137 See Intel and AMD documentation, keeping in mind that the operand order in
1138 instructions is reversed from the Intel syntax.
1141 @section AMD's Lightweight Profiling Instructions
1146 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1147 instruction set, available on AMD's Family 15h (Orochi) processors.
1149 LWP enables applications to collect and manage performance data, and
1150 react to performance events. The collection of performance data
1151 requires no context switches. LWP runs in the context of a thread and
1152 so several counters can be used independently across multiple threads.
1153 LWP can be used in both 64-bit and legacy 32-bit modes.
1155 For detailed information on the LWP instruction set, see the
1156 @cite{AMD Lightweight Profiling Specification} available at
1157 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1160 @section Bit Manipulation Instructions
1165 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1167 BMI instructions provide several instructions implementing individual
1168 bit manipulation operations such as isolation, masking, setting, or
1171 @c Need to add a specification citation here when available.
1174 @section AMD's Trailing Bit Manipulation Instructions
1179 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1180 instruction set, available on AMD's BDVER2 processors (Trinity and
1183 TBM instructions provide instructions implementing individual bit
1184 manipulation operations such as isolating, masking, setting, resetting,
1185 complementing, and operations on trailing zeros and ones.
1187 @c Need to add a specification citation here when available.
1190 @section Writing 16-bit Code
1192 @cindex i386 16-bit code
1193 @cindex 16-bit code, i386
1194 @cindex real-mode code, i386
1195 @cindex @code{code16gcc} directive, i386
1196 @cindex @code{code16} directive, i386
1197 @cindex @code{code32} directive, i386
1198 @cindex @code{code64} directive, i386
1199 @cindex @code{code64} directive, x86-64
1200 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1201 or 64-bit x86-64 code depending on the default configuration,
1202 it also supports writing code to run in real mode or in 16-bit protected
1203 mode code segments. To do this, put a @samp{.code16} or
1204 @samp{.code16gcc} directive before the assembly language instructions to
1205 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1206 32-bit code with the @samp{.code32} directive or 64-bit code with the
1207 @samp{.code64} directive.
1209 @samp{.code16gcc} provides experimental support for generating 16-bit
1210 code from gcc, and differs from @samp{.code16} in that @samp{call},
1211 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1212 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1213 default to 32-bit size. This is so that the stack pointer is
1214 manipulated in the same way over function calls, allowing access to
1215 function parameters at the same stack offsets as in 32-bit mode.
1216 @samp{.code16gcc} also automatically adds address size prefixes where
1217 necessary to use the 32-bit addressing modes that gcc generates.
1219 The code which @code{@value{AS}} generates in 16-bit mode will not
1220 necessarily run on a 16-bit pre-80386 processor. To write code that
1221 runs on such a processor, you must refrain from using @emph{any} 32-bit
1222 constructs which require @code{@value{AS}} to output address or operand
1225 Note that writing 16-bit code instructions by explicitly specifying a
1226 prefix or an instruction mnemonic suffix within a 32-bit code section
1227 generates different machine instructions than those generated for a
1228 16-bit code segment. In a 32-bit code section, the following code
1229 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1230 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1236 The same code in a 16-bit code section would generate the machine
1237 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1238 is correct since the processor default operand size is assumed to be 16
1239 bits in a 16-bit code section.
1242 @section Specifying CPU Architecture
1244 @cindex arch directive, i386
1245 @cindex i386 arch directive
1246 @cindex arch directive, x86-64
1247 @cindex x86-64 arch directive
1249 @code{@value{AS}} may be told to assemble for a particular CPU
1250 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1251 directive enables a warning when gas detects an instruction that is not
1252 supported on the CPU specified. The choices for @var{cpu_type} are:
1254 @multitable @columnfractions .20 .20 .20 .20
1255 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1256 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1257 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1258 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1259 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1260 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1261 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1262 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1263 @item @samp{btver2} @samp{generic32} @tab @samp{generic64}
1264 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1265 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1266 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1267 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1268 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1269 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1270 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1271 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1272 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1273 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1274 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1275 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1276 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1277 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1278 @item @samp{.avx512_bitalg}
1279 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1280 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1281 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1282 @item @samp{.movdiri} @tab @samp{.movdir64b}
1283 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1284 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1285 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1286 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1289 Apart from the warning, there are only two other effects on
1290 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1291 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1292 will automatically use a two byte opcode sequence. The larger three
1293 byte opcode sequence is used on the 486 (and when no architecture is
1294 specified) because it executes faster on the 486. Note that you can
1295 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1296 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1297 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1298 conditional jumps will be promoted when necessary to a two instruction
1299 sequence consisting of a conditional jump of the opposite sense around
1300 an unconditional jump to the target.
1302 Following the CPU architecture (but not a sub-architecture, which are those
1303 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1304 control automatic promotion of conditional jumps. @samp{jumps} is the
1305 default, and enables jump promotion; All external jumps will be of the long
1306 variety, and file-local jumps will be promoted as necessary.
1307 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1308 byte offset jumps, and warns about file-local conditional jumps that
1309 @code{@value{AS}} promotes.
1310 Unconditional jumps are treated as for @samp{jumps}.
1319 @section AT&T Syntax bugs
1321 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1322 assemblers, generate floating point instructions with reversed source
1323 and destination registers in certain cases. Unfortunately, gcc and
1324 possibly many other programs use this reversed syntax, so we're stuck
1333 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1334 than the expected @samp{%st(3) - %st}. This happens with all the
1335 non-commutative arithmetic floating point operations with two register
1336 operands where the source register is @samp{%st} and the destination
1337 register is @samp{%st(i)}.
1342 @cindex i386 @code{mul}, @code{imul} instructions
1343 @cindex @code{mul} instruction, i386
1344 @cindex @code{imul} instruction, i386
1345 @cindex @code{mul} instruction, x86-64
1346 @cindex @code{imul} instruction, x86-64
1347 There is some trickery concerning the @samp{mul} and @samp{imul}
1348 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1349 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1350 for @samp{imul}) can be output only in the one operand form. Thus,
1351 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1352 the expanding multiply would clobber the @samp{%edx} register, and this
1353 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1354 64-bit product in @samp{%edx:%eax}.
1356 We have added a two operand form of @samp{imul} when the first operand
1357 is an immediate mode expression and the second operand is a register.
1358 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1359 example, can be done with @samp{imul $69, %eax} rather than @samp{imul