1 @c Copyright (C) 1991-2020 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-ISA:: AMD64 ISA vs. Intel64 ISA
41 * i386-Bugs:: AT&T Syntax bugs
48 @cindex options for i386
49 @cindex options for x86-64
51 @cindex x86-64 options
53 The i386 version of @code{@value{AS}} has a few machine
58 @cindex @samp{--32} option, i386
59 @cindex @samp{--32} option, x86-64
60 @cindex @samp{--x32} option, i386
61 @cindex @samp{--x32} option, x86-64
62 @cindex @samp{--64} option, i386
63 @cindex @samp{--64} option, x86-64
64 @item --32 | --x32 | --64
65 Select the word size, either 32 bits or 64 bits. @samp{--32}
66 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
67 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
70 These options are only available with the ELF object file format, and
71 require that the necessary BFD support has been included (on a 32-bit
72 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
73 usage and use x86-64 as target platform).
76 By default, x86 GAS replaces multiple nop instructions used for
77 alignment within code sections with multi-byte nop instructions such
78 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
79 byte nop (0x90) is explicitly specified as the fill byte for alignment.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
133 In addition to the basic instruction set, the assembler can be told to
134 accept various extension mnemonics. For example,
135 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
136 @var{vmx}. The following extensions are currently supported:
205 @code{avx512_4fmaps},
206 @code{avx512_4vnniw},
207 @code{avx512_vpopcntdq},
210 @code{avx512_bitalg},
211 @code{avx512_vp2intersect},
222 @code{noavx512_4fmaps},
223 @code{noavx512_4vnniw},
224 @code{noavx512_vpopcntdq},
225 @code{noavx512_vbmi2},
226 @code{noavx512_vnni},
227 @code{noavx512_bitalg},
228 @code{noavx512_vp2intersect},
229 @code{noavx512_bf16},
282 Note that rather than extending a basic instruction set, the extension
283 mnemonics starting with @code{no} revoke the respective functionality.
285 When the @code{.arch} directive is used with @option{-march}, the
286 @code{.arch} directive will take precedent.
288 @cindex @samp{-mtune=} option, i386
289 @cindex @samp{-mtune=} option, x86-64
290 @item -mtune=@var{CPU}
291 This option specifies a processor to optimize for. When used in
292 conjunction with the @option{-march} option, only instructions
293 of the processor specified by the @option{-march} option will be
296 Valid @var{CPU} values are identical to the processor list of
297 @option{-march=@var{CPU}}.
299 @cindex @samp{-msse2avx} option, i386
300 @cindex @samp{-msse2avx} option, x86-64
302 This option specifies that the assembler should encode SSE instructions
305 @cindex @samp{-msse-check=} option, i386
306 @cindex @samp{-msse-check=} option, x86-64
307 @item -msse-check=@var{none}
308 @itemx -msse-check=@var{warning}
309 @itemx -msse-check=@var{error}
310 These options control if the assembler should check SSE instructions.
311 @option{-msse-check=@var{none}} will make the assembler not to check SSE
312 instructions, which is the default. @option{-msse-check=@var{warning}}
313 will make the assembler issue a warning for any SSE instruction.
314 @option{-msse-check=@var{error}} will make the assembler issue an error
315 for any SSE instruction.
317 @cindex @samp{-mavxscalar=} option, i386
318 @cindex @samp{-mavxscalar=} option, x86-64
319 @item -mavxscalar=@var{128}
320 @itemx -mavxscalar=@var{256}
321 These options control how the assembler should encode scalar AVX
322 instructions. @option{-mavxscalar=@var{128}} will encode scalar
323 AVX instructions with 128bit vector length, which is the default.
324 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
325 with 256bit vector length.
327 WARNING: Don't use this for production code - due to CPU errata the
328 resulting code may not work on certain models.
330 @cindex @samp{-mvexwig=} option, i386
331 @cindex @samp{-mvexwig=} option, x86-64
332 @item -mvexwig=@var{0}
333 @itemx -mvexwig=@var{1}
334 These options control how the assembler should encode VEX.W-ignored (WIG)
335 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
336 instructions with vex.w = 0, which is the default.
337 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
340 WARNING: Don't use this for production code - due to CPU errata the
341 resulting code may not work on certain models.
343 @cindex @samp{-mevexlig=} option, i386
344 @cindex @samp{-mevexlig=} option, x86-64
345 @item -mevexlig=@var{128}
346 @itemx -mevexlig=@var{256}
347 @itemx -mevexlig=@var{512}
348 These options control how the assembler should encode length-ignored
349 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
350 EVEX instructions with 128bit vector length, which is the default.
351 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
352 encode LIG EVEX instructions with 256bit and 512bit vector length,
355 @cindex @samp{-mevexwig=} option, i386
356 @cindex @samp{-mevexwig=} option, x86-64
357 @item -mevexwig=@var{0}
358 @itemx -mevexwig=@var{1}
359 These options control how the assembler should encode w-ignored (WIG)
360 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
361 EVEX instructions with evex.w = 0, which is the default.
362 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
365 @cindex @samp{-mmnemonic=} option, i386
366 @cindex @samp{-mmnemonic=} option, x86-64
367 @item -mmnemonic=@var{att}
368 @itemx -mmnemonic=@var{intel}
369 This option specifies instruction mnemonic for matching instructions.
370 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
373 @cindex @samp{-msyntax=} option, i386
374 @cindex @samp{-msyntax=} option, x86-64
375 @item -msyntax=@var{att}
376 @itemx -msyntax=@var{intel}
377 This option specifies instruction syntax when processing instructions.
378 The @code{.att_syntax} and @code{.intel_syntax} directives will
381 @cindex @samp{-mnaked-reg} option, i386
382 @cindex @samp{-mnaked-reg} option, x86-64
384 This option specifies that registers don't require a @samp{%} prefix.
385 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
387 @cindex @samp{-madd-bnd-prefix} option, i386
388 @cindex @samp{-madd-bnd-prefix} option, x86-64
389 @item -madd-bnd-prefix
390 This option forces the assembler to add BND prefix to all branches, even
391 if such prefix was not explicitly specified in the source code.
393 @cindex @samp{-mshared} option, i386
394 @cindex @samp{-mshared} option, x86-64
396 On ELF target, the assembler normally optimizes out non-PLT relocations
397 against defined non-weak global branch targets with default visibility.
398 The @samp{-mshared} option tells the assembler to generate code which
399 may go into a shared library where all non-weak global branch targets
400 with default visibility can be preempted. The resulting code is
401 slightly bigger. This option only affects the handling of branch
404 @cindex @samp{-mbig-obj} option, i386
405 @cindex @samp{-mbig-obj} option, x86-64
407 On PE/COFF target this option forces the use of big object file
408 format, which allows more than 32768 sections.
410 @cindex @samp{-momit-lock-prefix=} option, i386
411 @cindex @samp{-momit-lock-prefix=} option, x86-64
412 @item -momit-lock-prefix=@var{no}
413 @itemx -momit-lock-prefix=@var{yes}
414 These options control how the assembler should encode lock prefix.
415 This option is intended as a workaround for processors, that fail on
416 lock prefix. This option can only be safely used with single-core,
417 single-thread computers
418 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
419 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
420 which is the default.
422 @cindex @samp{-mfence-as-lock-add=} option, i386
423 @cindex @samp{-mfence-as-lock-add=} option, x86-64
424 @item -mfence-as-lock-add=@var{no}
425 @itemx -mfence-as-lock-add=@var{yes}
426 These options control how the assembler should encode lfence, mfence and
428 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
429 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
430 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
431 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
432 sfence as usual, which is the default.
434 @cindex @samp{-mrelax-relocations=} option, i386
435 @cindex @samp{-mrelax-relocations=} option, x86-64
436 @item -mrelax-relocations=@var{no}
437 @itemx -mrelax-relocations=@var{yes}
438 These options control whether the assembler should generate relax
439 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
440 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
441 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
442 @option{-mrelax-relocations=@var{no}} will not generate relax
443 relocations. The default can be controlled by a configure option
444 @option{--enable-x86-relax-relocations}.
446 @cindex @samp{-malign-branch-boundary=} option, i386
447 @cindex @samp{-malign-branch-boundary=} option, x86-64
448 @item -malign-branch-boundary=@var{NUM}
449 This option controls how the assembler should align branches with segment
450 prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or
451 no less than 16. Branches will be aligned within @var{NUM} byte
452 boundary. @option{-malign-branch-boundary=0}, which is the default,
453 doesn't align branches.
455 @cindex @samp{-malign-branch=} option, i386
456 @cindex @samp{-malign-branch=} option, x86-64
457 @item -malign-branch=@var{TYPE}[+@var{TYPE}...]
458 This option specifies types of branches to align. @var{TYPE} is
459 combination of @samp{jcc}, which aligns conditional jumps,
460 @samp{fused}, which aligns fused conditional jumps, @samp{jmp},
461 which aligns unconditional jumps, @samp{call} which aligns calls,
462 @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect
463 jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}.
465 @cindex @samp{-malign-branch-prefix-size=} option, i386
466 @cindex @samp{-malign-branch-prefix-size=} option, x86-64
467 @item -malign-branch-prefix-size=@var{NUM}
468 This option specifies the maximum number of prefixes on an instruction
469 to align branches. @var{NUM} should be between 0 and 5. The default
472 @cindex @samp{-mbranches-within-32B-boundaries} option, i386
473 @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64
474 @item -mbranches-within-32B-boundaries
475 This option aligns conditional jumps, fused conditional jumps and
476 unconditional jumps within 32 byte boundary with up to 5 segment prefixes
477 on an instruction. It is equivalent to
478 @option{-malign-branch-boundary=32}
479 @option{-malign-branch=jcc+fused+jmp}
480 @option{-malign-branch-prefix-size=5}.
481 The default doesn't align branches.
483 @cindex @samp{-mlfence-after-load=} option, i386
484 @cindex @samp{-mlfence-after-load=} option, x86-64
485 @item -mlfence-after-load=@var{no}
486 @itemx -mlfence-after-load=@var{yes}
487 These options control whether the assembler should generate lfence
488 after load instructions. @option{-mlfence-after-load=@var{yes}} will
489 generate lfence. @option{-mlfence-after-load=@var{no}} will not generate
490 lfence, which is the default.
492 @cindex @samp{-mlfence-before-indirect-branch=} option, i386
493 @cindex @samp{-mlfence-before-indirect-branch=} option, x86-64
494 @item -mlfence-before-indirect-branch=@var{none}
495 @item -mlfence-before-indirect-branch=@var{all}
496 @item -mlfence-before-indirect-branch=@var{register}
497 @itemx -mlfence-before-indirect-branch=@var{memory}
498 These options control whether the assembler should generate lfence
499 before indirect near branch instructions.
500 @option{-mlfence-before-indirect-branch=@var{all}} will generate lfence
501 before indirect near branch via register and issue a warning before
502 indirect near branch via memory.
503 It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when
504 there's no explict @option{-mlfence-before-ret=}.
505 @option{-mlfence-before-indirect-branch=@var{register}} will generate
506 lfence before indirect near branch via register.
507 @option{-mlfence-before-indirect-branch=@var{memory}} will issue a
508 warning before indirect near branch via memory.
509 @option{-mlfence-before-indirect-branch=@var{none}} will not generate
510 lfence nor issue warning, which is the default. Note that lfence won't
511 be generated before indirect near branch via register with
512 @option{-mlfence-after-load=@var{yes}} since lfence will be generated
513 after loading branch target register.
515 @cindex @samp{-mlfence-before-ret=} option, i386
516 @cindex @samp{-mlfence-before-ret=} option, x86-64
517 @item -mlfence-before-ret=@var{none}
518 @item -mlfence-before-ret=@var{shl}
519 @item -mlfence-before-ret=@var{or}
520 @item -mlfence-before-ret=@var{yes}
521 @itemx -mlfence-before-ret=@var{not}
522 These options control whether the assembler should generate lfence
523 before ret. @option{-mlfence-before-ret=@var{or}} will generate
524 generate or instruction with lfence.
525 @option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction
526 with lfence. @option{-mlfence-before-ret=@var{not}} will generate not
527 instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not
528 generate lfence, which is the default.
530 @cindex @samp{-mx86-used-note=} option, i386
531 @cindex @samp{-mx86-used-note=} option, x86-64
532 @item -mx86-used-note=@var{no}
533 @itemx -mx86-used-note=@var{yes}
534 These options control whether the assembler should generate
535 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
536 GNU property notes. The default can be controlled by the
537 @option{--enable-x86-used-note} configure option.
539 @cindex @samp{-mevexrcig=} option, i386
540 @cindex @samp{-mevexrcig=} option, x86-64
541 @item -mevexrcig=@var{rne}
542 @itemx -mevexrcig=@var{rd}
543 @itemx -mevexrcig=@var{ru}
544 @itemx -mevexrcig=@var{rz}
545 These options control how the assembler should encode SAE-only
546 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
547 of EVEX instruction with 00, which is the default.
548 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
549 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
550 with 01, 10 and 11 RC bits, respectively.
552 @cindex @samp{-mamd64} option, x86-64
553 @cindex @samp{-mintel64} option, x86-64
556 This option specifies that the assembler should accept only AMD64 or
557 Intel64 ISA in 64-bit mode. The default is to accept common, Intel64
560 @cindex @samp{-O0} option, i386
561 @cindex @samp{-O0} option, x86-64
562 @cindex @samp{-O} option, i386
563 @cindex @samp{-O} option, x86-64
564 @cindex @samp{-O1} option, i386
565 @cindex @samp{-O1} option, x86-64
566 @cindex @samp{-O2} option, i386
567 @cindex @samp{-O2} option, x86-64
568 @cindex @samp{-Os} option, i386
569 @cindex @samp{-Os} option, x86-64
570 @item -O0 | -O | -O1 | -O2 | -Os
571 Optimize instruction encoding with smaller instruction size. @samp{-O}
572 and @samp{-O1} encode 64-bit register load instructions with 64-bit
573 immediate as 32-bit register load instructions with 31-bit or 32-bits
574 immediates, encode 64-bit register clearing instructions with 32-bit
575 register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
576 register clearing instructions with 128-bit VEX vector register
577 clearing instructions, encode 128-bit/256-bit EVEX vector
578 register load/store instructions with VEX vector register load/store
579 instructions, and encode 128-bit/256-bit EVEX packed integer logical
580 instructions with 128-bit/256-bit VEX packed integer logical.
582 @samp{-O2} includes @samp{-O1} optimization plus encodes
583 256-bit/512-bit EVEX vector register clearing instructions with 128-bit
584 EVEX vector register clearing instructions. In 64-bit mode VEX encoded
585 instructions with commutative source operands will also have their
586 source operands swapped if this allows using the 2-byte VEX prefix form
587 instead of the 3-byte one. Certain forms of AND as well as OR with the
588 same (register) operand specified twice will also be changed to TEST.
590 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
591 and 64-bit register tests with immediate as 8-bit register test with
592 immediate. @samp{-O0} turns off this optimization.
597 @node i386-Directives
598 @section x86 specific Directives
600 @cindex machine directives, x86
601 @cindex x86 machine directives
604 @cindex @code{lcomm} directive, COFF
605 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
606 Reserve @var{length} (an absolute expression) bytes for a local common
607 denoted by @var{symbol}. The section and value of @var{symbol} are
608 those of the new local common. The addresses are allocated in the bss
609 section, so that at run-time the bytes start off zeroed. Since
610 @var{symbol} is not declared global, it is normally not visible to
611 @code{@value{LD}}. The optional third parameter, @var{alignment},
612 specifies the desired alignment of the symbol in the bss section.
614 This directive is only available for COFF based x86 targets.
616 @cindex @code{largecomm} directive, ELF
617 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
618 This directive behaves in the same way as the @code{comm} directive
619 except that the data is placed into the @var{.lbss} section instead of
620 the @var{.bss} section @ref{Comm}.
622 The directive is intended to be used for data which requires a large
623 amount of space, and it is only available for ELF based x86_64
626 @cindex @code{value} directive
627 @item .value @var{expression} [, @var{expression}]
628 This directive behaves in the same way as the @code{.short} directive,
629 taking a series of comma separated expressions and storing them as
630 two-byte wide values into the current section.
632 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
637 @section i386 Syntactical Considerations
639 * i386-Variations:: AT&T Syntax versus Intel Syntax
640 * i386-Chars:: Special Characters
643 @node i386-Variations
644 @subsection AT&T Syntax versus Intel Syntax
646 @cindex i386 intel_syntax pseudo op
647 @cindex intel_syntax pseudo op, i386
648 @cindex i386 att_syntax pseudo op
649 @cindex att_syntax pseudo op, i386
650 @cindex i386 syntax compatibility
651 @cindex syntax compatibility, i386
652 @cindex x86-64 intel_syntax pseudo op
653 @cindex intel_syntax pseudo op, x86-64
654 @cindex x86-64 att_syntax pseudo op
655 @cindex att_syntax pseudo op, x86-64
656 @cindex x86-64 syntax compatibility
657 @cindex syntax compatibility, x86-64
659 @code{@value{AS}} now supports assembly using Intel assembler syntax.
660 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
661 back to the usual AT&T mode for compatibility with the output of
662 @code{@value{GCC}}. Either of these directives may have an optional
663 argument, @code{prefix}, or @code{noprefix} specifying whether registers
664 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
665 different from Intel syntax. We mention these differences because
666 almost all 80386 documents use Intel syntax. Notable differences
667 between the two syntaxes are:
669 @cindex immediate operands, i386
670 @cindex i386 immediate operands
671 @cindex register operands, i386
672 @cindex i386 register operands
673 @cindex jump/call operands, i386
674 @cindex i386 jump/call operands
675 @cindex operand delimiters, i386
677 @cindex immediate operands, x86-64
678 @cindex x86-64 immediate operands
679 @cindex register operands, x86-64
680 @cindex x86-64 register operands
681 @cindex jump/call operands, x86-64
682 @cindex x86-64 jump/call operands
683 @cindex operand delimiters, x86-64
686 AT&T immediate operands are preceded by @samp{$}; Intel immediate
687 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
688 AT&T register operands are preceded by @samp{%}; Intel register operands
689 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
690 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
692 @cindex i386 source, destination operands
693 @cindex source, destination operands; i386
694 @cindex x86-64 source, destination operands
695 @cindex source, destination operands; x86-64
697 AT&T and Intel syntax use the opposite order for source and destination
698 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
699 @samp{source, dest} convention is maintained for compatibility with
700 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
701 instructions with 2 immediate operands, such as the @samp{enter}
702 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
704 @cindex mnemonic suffixes, i386
705 @cindex sizes operands, i386
706 @cindex i386 size suffixes
707 @cindex mnemonic suffixes, x86-64
708 @cindex sizes operands, x86-64
709 @cindex x86-64 size suffixes
711 In AT&T syntax the size of memory operands is determined from the last
712 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
713 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
714 (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
715 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
716 (256-bit vector) and zmm (512-bit vector) memory references, only when there's
717 no other way to disambiguate an instruction. Intel syntax accomplishes this by
718 prefixing memory operands (@emph{not} the instruction mnemonics) with
719 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
720 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
721 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
722 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
723 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
725 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
726 instruction with the 64-bit displacement or immediate operand.
728 @cindex return instructions, i386
729 @cindex i386 jump, call, return
730 @cindex return instructions, x86-64
731 @cindex x86-64 jump, call, return
733 Immediate form long jumps and calls are
734 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
736 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
738 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
739 @samp{ret far @var{stack-adjust}}.
741 @cindex sections, i386
742 @cindex i386 sections
743 @cindex sections, x86-64
744 @cindex x86-64 sections
746 The AT&T assembler does not provide support for multiple section
747 programs. Unix style systems expect all programs to be single sections.
751 @subsection Special Characters
753 @cindex line comment character, i386
754 @cindex i386 line comment character
755 The presence of a @samp{#} appearing anywhere on a line indicates the
756 start of a comment that extends to the end of that line.
758 If a @samp{#} appears as the first character of a line then the whole
759 line is treated as a comment, but in this case the line can also be a
760 logical line number directive (@pxref{Comments}) or a preprocessor
761 control command (@pxref{Preprocessing}).
763 If the @option{--divide} command-line option has not been specified
764 then the @samp{/} character appearing anywhere on a line also
765 introduces a line comment.
767 @cindex line separator, i386
768 @cindex statement separator, i386
769 @cindex i386 line separator
770 The @samp{;} character can be used to separate statements on the same
774 @section i386-Mnemonics
775 @subsection Instruction Naming
777 @cindex i386 instruction naming
778 @cindex instruction naming, i386
779 @cindex x86-64 instruction naming
780 @cindex instruction naming, x86-64
782 Instruction mnemonics are suffixed with one character modifiers which
783 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
784 and @samp{q} specify byte, word, long and quadruple word operands. If
785 no suffix is specified by an instruction then @code{@value{AS}} tries to
786 fill in the missing suffix based on the destination register operand
787 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
788 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
789 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
790 assembler which assumes that a missing mnemonic suffix implies long
791 operand size. (This incompatibility does not affect compiler output
792 since compilers always explicitly specify the mnemonic suffix.)
794 When there is no sizing suffix and no (suitable) register operands to
795 deduce the size of memory operands, with a few exceptions and where long
796 operand size is possible in the first place, operand size will default
797 to long in 32- and 64-bit modes. Similarly it will default to short in
798 16-bit mode. Noteworthy exceptions are
802 Instructions with an implicit on-stack operand as well as branches,
803 which default to quad in 64-bit mode.
806 Sign- and zero-extending moves, which default to byte size source
810 Floating point insns with integer operands, which default to short (for
811 perhaps historical reasons).
814 CRC32 with a 64-bit destination, which defaults to a quad source
819 @cindex encoding options, i386
820 @cindex encoding options, x86-64
822 Different encoding options can be specified via pseudo prefixes:
826 @samp{@{disp8@}} -- prefer 8-bit displacement.
829 @samp{@{disp32@}} -- prefer 32-bit displacement.
832 @samp{@{disp16@}} -- prefer 16-bit displacement.
835 @samp{@{load@}} -- prefer load-form instruction.
838 @samp{@{store@}} -- prefer store-form instruction.
841 @samp{@{vex@}} -- encode with VEX prefix.
844 @samp{@{vex3@}} -- encode with 3-byte VEX prefix.
847 @samp{@{evex@}} -- encode with EVEX prefix.
850 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
851 instructions (x86-64 only). Note that this differs from the @samp{rex}
852 prefix which generates REX prefix unconditionally.
855 @samp{@{nooptimize@}} -- disable instruction size optimization.
858 @cindex conversion instructions, i386
859 @cindex i386 conversion instructions
860 @cindex conversion instructions, x86-64
861 @cindex x86-64 conversion instructions
862 The Intel-syntax conversion instructions
866 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
869 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
872 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
875 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
878 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
882 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
883 @samp{%rdx:%rax} (x86-64 only),
887 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
888 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
891 @cindex extension instructions, i386
892 @cindex i386 extension instructions
893 @cindex extension instructions, x86-64
894 @cindex x86-64 extension instructions
895 The Intel-syntax extension instructions
899 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}.
902 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}.
905 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64}
909 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32}
912 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64}
916 @samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64}
920 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}.
923 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}.
926 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64}
930 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32}
933 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64}
938 are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx},
939 @samp{movsbq/movsb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw},
940 @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx},
941 @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx},
942 @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax.
944 @cindex jump instructions, i386
945 @cindex call instructions, i386
946 @cindex jump instructions, x86-64
947 @cindex call instructions, x86-64
948 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
949 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
952 @subsection AT&T Mnemonic versus Intel Mnemonic
954 @cindex i386 mnemonic compatibility
955 @cindex mnemonic compatibility, i386
957 @code{@value{AS}} supports assembly using Intel mnemonic.
958 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
959 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
960 syntax for compatibility with the output of @code{@value{GCC}}.
961 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
962 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
963 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
964 assembler with different mnemonics from those in Intel IA32 specification.
965 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
968 @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination
969 register. @samp{movsxd} should be used to encode 16-bit or 32-bit
970 destination register with both AT&T and Intel mnemonics.
974 @section Register Naming
976 @cindex i386 registers
977 @cindex registers, i386
978 @cindex x86-64 registers
979 @cindex registers, x86-64
980 Register operands are always prefixed with @samp{%}. The 80386 registers
985 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
986 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
987 frame pointer), and @samp{%esp} (the stack pointer).
990 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
991 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
994 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
995 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
996 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
997 @samp{%cx}, and @samp{%dx})
1000 the 6 section registers @samp{%cs} (code section), @samp{%ds}
1001 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
1005 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
1006 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
1009 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
1010 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
1013 the 2 test registers @samp{%tr6} and @samp{%tr7}.
1016 the 8 floating point register stack @samp{%st} or equivalently
1017 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
1018 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
1019 These registers are overloaded by 8 MMX registers @samp{%mm0},
1020 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
1021 @samp{%mm6} and @samp{%mm7}.
1024 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
1025 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
1028 The AMD x86-64 architecture extends the register set by:
1032 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
1033 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
1034 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
1038 the 8 extended registers @samp{%r8}--@samp{%r15}.
1041 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
1044 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
1047 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
1050 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
1053 the 8 debug registers: @samp{%db8}--@samp{%db15}.
1056 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
1059 With the AVX extensions more registers were made available:
1064 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
1065 available in 32-bit mode). The bottom 128 bits are overlaid with the
1066 @samp{xmm0}--@samp{xmm15} registers.
1070 The AVX512 extensions added the following registers:
1075 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
1076 available in 32-bit mode). The bottom 128 bits are overlaid with the
1077 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
1078 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
1081 the 8 mask registers @samp{%k0}--@samp{%k7}.
1086 @section Instruction Prefixes
1088 @cindex i386 instruction prefixes
1089 @cindex instruction prefixes, i386
1090 @cindex prefixes, i386
1091 Instruction prefixes are used to modify the following instruction. They
1092 are used to repeat string instructions, to provide section overrides, to
1093 perform bus lock operations, and to change operand and address sizes.
1094 (Most instructions that normally operate on 32-bit operands will use
1095 16-bit operands if the instruction has an ``operand size'' prefix.)
1096 Instruction prefixes are best written on the same line as the instruction
1097 they act upon. For example, the @samp{scas} (scan string) instruction is
1101 repne scas %es:(%edi),%al
1104 You may also place prefixes on the lines immediately preceding the
1105 instruction, but this circumvents checks that @code{@value{AS}} does
1106 with prefixes, and will not work with all prefixes.
1108 Here is a list of instruction prefixes:
1110 @cindex section override prefixes, i386
1113 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
1114 @samp{fs}, @samp{gs}. These are automatically added by specifying
1115 using the @var{section}:@var{memory-operand} form for memory references.
1117 @cindex size prefixes, i386
1119 Operand/Address size prefixes @samp{data16} and @samp{addr16}
1120 change 32-bit operands/addresses into 16-bit operands/addresses,
1121 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
1122 @code{.code16} section) into 32-bit operands/addresses. These prefixes
1123 @emph{must} appear on the same line of code as the instruction they
1124 modify. For example, in a 16-bit @code{.code16} section, you might
1131 @cindex bus lock prefixes, i386
1132 @cindex inhibiting interrupts, i386
1134 The bus lock prefix @samp{lock} inhibits interrupts during execution of
1135 the instruction it precedes. (This is only valid with certain
1136 instructions; see a 80386 manual for details).
1138 @cindex coprocessor wait, i386
1140 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
1141 complete the current instruction. This should never be needed for the
1142 80386/80387 combination.
1144 @cindex repeat prefixes, i386
1146 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
1147 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
1148 times if the current address size is 16-bits).
1149 @cindex REX prefixes, i386
1151 The @samp{rex} family of prefixes is used by x86-64 to encode
1152 extensions to i386 instruction set. The @samp{rex} prefix has four
1153 bits --- an operand size overwrite (@code{64}) used to change operand size
1154 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
1157 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
1158 instruction emits @samp{rex} prefix with all the bits set. By omitting
1159 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
1160 prefixes as well. Normally, there is no need to write the prefixes
1161 explicitly, since gas will automatically generate them based on the
1162 instruction operands.
1166 @section Memory References
1168 @cindex i386 memory references
1169 @cindex memory references, i386
1170 @cindex x86-64 memory references
1171 @cindex memory references, x86-64
1172 An Intel syntax indirect memory reference of the form
1175 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
1179 is translated into the AT&T syntax
1182 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
1186 where @var{base} and @var{index} are the optional 32-bit base and
1187 index registers, @var{disp} is the optional displacement, and
1188 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
1189 to calculate the address of the operand. If no @var{scale} is
1190 specified, @var{scale} is taken to be 1. @var{section} specifies the
1191 optional section register for the memory operand, and may override the
1192 default section register (see a 80386 manual for section register
1193 defaults). Note that section overrides in AT&T syntax @emph{must}
1194 be preceded by a @samp{%}. If you specify a section override which
1195 coincides with the default section register, @code{@value{AS}} does @emph{not}
1196 output any section register override prefixes to assemble the given
1197 instruction. Thus, section overrides can be specified to emphasize which
1198 section register is used for a given memory operand.
1200 Here are some examples of Intel and AT&T style memory references:
1203 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1204 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1205 missing, and the default section is used (@samp{%ss} for addressing with
1206 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1208 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1209 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1210 @samp{foo}. All other fields are missing. The section register here
1211 defaults to @samp{%ds}.
1213 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1214 This uses the value pointed to by @samp{foo} as a memory operand.
1215 Note that @var{base} and @var{index} are both missing, but there is only
1216 @emph{one} @samp{,}. This is a syntactic exception.
1218 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1219 This selects the contents of the variable @samp{foo} with section
1220 register @var{section} being @samp{%gs}.
1223 Absolute (as opposed to PC relative) call and jump operands must be
1224 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1225 always chooses PC relative addressing for jump/call labels.
1227 Any instruction that has a memory operand, but no register operand,
1228 @emph{must} specify its size (byte, word, long, or quadruple) with an
1229 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1232 The x86-64 architecture adds an RIP (instruction pointer relative)
1233 addressing. This addressing mode is specified by using @samp{rip} as a
1234 base register. Only constant offsets are valid. For example:
1237 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1238 Points to the address 1234 bytes past the end of the current
1241 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1242 Points to the @code{symbol} in RIP relative way, this is shorter than
1243 the default absolute addressing.
1246 Other addressing modes remain unchanged in x86-64 architecture, except
1247 registers used are 64-bit instead of 32-bit.
1250 @section Handling of Jump Instructions
1252 @cindex jump optimization, i386
1253 @cindex i386 jump optimization
1254 @cindex jump optimization, x86-64
1255 @cindex x86-64 jump optimization
1256 Jump instructions are always optimized to use the smallest possible
1257 displacements. This is accomplished by using byte (8-bit) displacement
1258 jumps whenever the target is sufficiently close. If a byte displacement
1259 is insufficient a long displacement is used. We do not support
1260 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1261 instruction with the @samp{data16} instruction prefix), since the 80386
1262 insists upon masking @samp{%eip} to 16 bits after the word displacement
1263 is added. (See also @pxref{i386-Arch})
1265 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1266 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1267 displacements, so that if you use these instructions (@code{@value{GCC}} does
1268 not use them) you may get an error message (and incorrect code). The AT&T
1269 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1280 @section Floating Point
1282 @cindex i386 floating point
1283 @cindex floating point, i386
1284 @cindex x86-64 floating point
1285 @cindex floating point, x86-64
1286 All 80387 floating point types except packed BCD are supported.
1287 (BCD support may be added without much difficulty). These data
1288 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1289 double (64-bit), and extended (80-bit) precision floating point.
1290 Each supported type has an instruction mnemonic suffix and a constructor
1291 associated with it. Instruction mnemonic suffixes specify the operand's
1292 data type. Constructors build these data types into memory.
1294 @cindex @code{float} directive, i386
1295 @cindex @code{single} directive, i386
1296 @cindex @code{double} directive, i386
1297 @cindex @code{tfloat} directive, i386
1298 @cindex @code{float} directive, x86-64
1299 @cindex @code{single} directive, x86-64
1300 @cindex @code{double} directive, x86-64
1301 @cindex @code{tfloat} directive, x86-64
1304 Floating point constructors are @samp{.float} or @samp{.single},
1305 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1306 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1307 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1308 only supports this format via the @samp{fldt} (load 80-bit real to stack
1309 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1311 @cindex @code{word} directive, i386
1312 @cindex @code{long} directive, i386
1313 @cindex @code{int} directive, i386
1314 @cindex @code{quad} directive, i386
1315 @cindex @code{word} directive, x86-64
1316 @cindex @code{long} directive, x86-64
1317 @cindex @code{int} directive, x86-64
1318 @cindex @code{quad} directive, x86-64
1320 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1321 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1322 corresponding instruction mnemonic suffixes are @samp{s} (single),
1323 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1324 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1325 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1326 stack) instructions.
1329 Register to register operations should not use instruction mnemonic suffixes.
1330 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1331 wrote @samp{fst %st, %st(1)}, since all register to register operations
1332 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1333 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1334 then stores the result in the 4 byte location @samp{mem})
1337 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1340 @cindex 3DNow!, i386
1343 @cindex 3DNow!, x86-64
1344 @cindex SIMD, x86-64
1346 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1347 instructions for integer data), available on Intel's Pentium MMX
1348 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1349 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1350 instruction set (SIMD instructions for 32-bit floating point data)
1351 available on AMD's K6-2 processor and possibly others in the future.
1353 Currently, @code{@value{AS}} does not support Intel's floating point
1356 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1357 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1358 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1359 floating point values. The MMX registers cannot be used at the same time
1360 as the floating point stack.
1362 See Intel and AMD documentation, keeping in mind that the operand order in
1363 instructions is reversed from the Intel syntax.
1366 @section AMD's Lightweight Profiling Instructions
1371 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1372 instruction set, available on AMD's Family 15h (Orochi) processors.
1374 LWP enables applications to collect and manage performance data, and
1375 react to performance events. The collection of performance data
1376 requires no context switches. LWP runs in the context of a thread and
1377 so several counters can be used independently across multiple threads.
1378 LWP can be used in both 64-bit and legacy 32-bit modes.
1380 For detailed information on the LWP instruction set, see the
1381 @cite{AMD Lightweight Profiling Specification} available at
1382 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1385 @section Bit Manipulation Instructions
1390 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1392 BMI instructions provide several instructions implementing individual
1393 bit manipulation operations such as isolation, masking, setting, or
1396 @c Need to add a specification citation here when available.
1399 @section AMD's Trailing Bit Manipulation Instructions
1404 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1405 instruction set, available on AMD's BDVER2 processors (Trinity and
1408 TBM instructions provide instructions implementing individual bit
1409 manipulation operations such as isolating, masking, setting, resetting,
1410 complementing, and operations on trailing zeros and ones.
1412 @c Need to add a specification citation here when available.
1415 @section Writing 16-bit Code
1417 @cindex i386 16-bit code
1418 @cindex 16-bit code, i386
1419 @cindex real-mode code, i386
1420 @cindex @code{code16gcc} directive, i386
1421 @cindex @code{code16} directive, i386
1422 @cindex @code{code32} directive, i386
1423 @cindex @code{code64} directive, i386
1424 @cindex @code{code64} directive, x86-64
1425 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1426 or 64-bit x86-64 code depending on the default configuration,
1427 it also supports writing code to run in real mode or in 16-bit protected
1428 mode code segments. To do this, put a @samp{.code16} or
1429 @samp{.code16gcc} directive before the assembly language instructions to
1430 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1431 32-bit code with the @samp{.code32} directive or 64-bit code with the
1432 @samp{.code64} directive.
1434 @samp{.code16gcc} provides experimental support for generating 16-bit
1435 code from gcc, and differs from @samp{.code16} in that @samp{call},
1436 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1437 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1438 default to 32-bit size. This is so that the stack pointer is
1439 manipulated in the same way over function calls, allowing access to
1440 function parameters at the same stack offsets as in 32-bit mode.
1441 @samp{.code16gcc} also automatically adds address size prefixes where
1442 necessary to use the 32-bit addressing modes that gcc generates.
1444 The code which @code{@value{AS}} generates in 16-bit mode will not
1445 necessarily run on a 16-bit pre-80386 processor. To write code that
1446 runs on such a processor, you must refrain from using @emph{any} 32-bit
1447 constructs which require @code{@value{AS}} to output address or operand
1450 Note that writing 16-bit code instructions by explicitly specifying a
1451 prefix or an instruction mnemonic suffix within a 32-bit code section
1452 generates different machine instructions than those generated for a
1453 16-bit code segment. In a 32-bit code section, the following code
1454 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1455 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1461 The same code in a 16-bit code section would generate the machine
1462 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1463 is correct since the processor default operand size is assumed to be 16
1464 bits in a 16-bit code section.
1467 @section Specifying CPU Architecture
1469 @cindex arch directive, i386
1470 @cindex i386 arch directive
1471 @cindex arch directive, x86-64
1472 @cindex x86-64 arch directive
1474 @code{@value{AS}} may be told to assemble for a particular CPU
1475 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1476 directive enables a warning when gas detects an instruction that is not
1477 supported on the CPU specified. The choices for @var{cpu_type} are:
1479 @multitable @columnfractions .20 .20 .20 .20
1480 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1481 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1482 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1483 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1484 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1485 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1486 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1487 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1488 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1489 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1490 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
1491 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1492 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1493 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1494 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1495 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1496 @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
1498 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1499 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1500 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1501 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1502 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1503 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1504 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1505 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1506 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1507 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1508 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1509 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
1510 @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile}
1511 @item @samp{.kl} @tab @samp{.widekl}
1512 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1513 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1514 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1515 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
1516 @item @samp{.mcommit} @tab @samp{.sev_es}
1519 Apart from the warning, there are only two other effects on
1520 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1521 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1522 will automatically use a two byte opcode sequence. The larger three
1523 byte opcode sequence is used on the 486 (and when no architecture is
1524 specified) because it executes faster on the 486. Note that you can
1525 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1526 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1527 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1528 conditional jumps will be promoted when necessary to a two instruction
1529 sequence consisting of a conditional jump of the opposite sense around
1530 an unconditional jump to the target.
1532 Following the CPU architecture (but not a sub-architecture, which are those
1533 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1534 control automatic promotion of conditional jumps. @samp{jumps} is the
1535 default, and enables jump promotion; All external jumps will be of the long
1536 variety, and file-local jumps will be promoted as necessary.
1537 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1538 byte offset jumps, and warns about file-local conditional jumps that
1539 @code{@value{AS}} promotes.
1540 Unconditional jumps are treated as for @samp{jumps}.
1549 @section AMD64 ISA vs. Intel64 ISA
1551 There are some discrepancies between AMD64 and Intel64 ISAs.
1554 @item For @samp{movsxd} with 16-bit destination register, AMD64
1555 supports 32-bit source operand and Intel64 supports 16-bit source
1558 @item For far branches (with explicit memory operand), both ISAs support
1559 32- and 16-bit operand size. Intel64 additionally supports 64-bit
1560 operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax
1561 and with an explicit @samp{tbyte ptr} operand size specifier in Intel
1564 @item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16-
1565 and 32-bit operand size (32- and 48-bit memory operand) in both ISAs,
1566 while Intel64 additionally supports 64-bit operand sise (80-bit memory
1572 @section AT&T Syntax bugs
1574 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1575 assemblers, generate floating point instructions with reversed source
1576 and destination registers in certain cases. Unfortunately, gcc and
1577 possibly many other programs use this reversed syntax, so we're stuck
1586 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1587 than the expected @samp{%st(3) - %st}. This happens with all the
1588 non-commutative arithmetic floating point operations with two register
1589 operands where the source register is @samp{%st} and the destination
1590 register is @samp{%st(i)}.
1595 @cindex i386 @code{mul}, @code{imul} instructions
1596 @cindex @code{mul} instruction, i386
1597 @cindex @code{imul} instruction, i386
1598 @cindex @code{mul} instruction, x86-64
1599 @cindex @code{imul} instruction, x86-64
1600 There is some trickery concerning the @samp{mul} and @samp{imul}
1601 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1602 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1603 for @samp{imul}) can be output only in the one operand form. Thus,
1604 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1605 the expanding multiply would clobber the @samp{%edx} register, and this
1606 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1607 64-bit product in @samp{%edx:%eax}.
1609 We have added a two operand form of @samp{imul} when the first operand
1610 is an immediate mode expression and the second operand is a register.
1611 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1612 example, can be done with @samp{imul $69, %eax} rather than @samp{imul