1 @c Copyright (C) 1991-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics. For example,
132 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
133 @var{vmx}. The following extensions are currently supported:
219 Note that rather than extending a basic instruction set, the extension
220 mnemonics starting with @code{no} revoke the respective functionality.
222 When the @code{.arch} directive is used with @option{-march}, the
223 @code{.arch} directive will take precedent.
225 @cindex @samp{-mtune=} option, i386
226 @cindex @samp{-mtune=} option, x86-64
227 @item -mtune=@var{CPU}
228 This option specifies a processor to optimize for. When used in
229 conjunction with the @option{-march} option, only instructions
230 of the processor specified by the @option{-march} option will be
233 Valid @var{CPU} values are identical to the processor list of
234 @option{-march=@var{CPU}}.
236 @cindex @samp{-msse2avx} option, i386
237 @cindex @samp{-msse2avx} option, x86-64
239 This option specifies that the assembler should encode SSE instructions
242 @cindex @samp{-msse-check=} option, i386
243 @cindex @samp{-msse-check=} option, x86-64
244 @item -msse-check=@var{none}
245 @itemx -msse-check=@var{warning}
246 @itemx -msse-check=@var{error}
247 These options control if the assembler should check SSE instructions.
248 @option{-msse-check=@var{none}} will make the assembler not to check SSE
249 instructions, which is the default. @option{-msse-check=@var{warning}}
250 will make the assembler issue a warning for any SSE instruction.
251 @option{-msse-check=@var{error}} will make the assembler issue an error
252 for any SSE instruction.
254 @cindex @samp{-mavxscalar=} option, i386
255 @cindex @samp{-mavxscalar=} option, x86-64
256 @item -mavxscalar=@var{128}
257 @itemx -mavxscalar=@var{256}
258 These options control how the assembler should encode scalar AVX
259 instructions. @option{-mavxscalar=@var{128}} will encode scalar
260 AVX instructions with 128bit vector length, which is the default.
261 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
262 with 256bit vector length.
264 @cindex @samp{-mevexlig=} option, i386
265 @cindex @samp{-mevexlig=} option, x86-64
266 @item -mevexlig=@var{128}
267 @itemx -mevexlig=@var{256}
268 @itemx -mevexlig=@var{512}
269 These options control how the assembler should encode length-ignored
270 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
271 EVEX instructions with 128bit vector length, which is the default.
272 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
273 encode LIG EVEX instructions with 256bit and 512bit vector length,
276 @cindex @samp{-mevexwig=} option, i386
277 @cindex @samp{-mevexwig=} option, x86-64
278 @item -mevexwig=@var{0}
279 @itemx -mevexwig=@var{1}
280 These options control how the assembler should encode w-ignored (WIG)
281 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
282 EVEX instructions with evex.w = 0, which is the default.
283 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
286 @cindex @samp{-mmnemonic=} option, i386
287 @cindex @samp{-mmnemonic=} option, x86-64
288 @item -mmnemonic=@var{att}
289 @itemx -mmnemonic=@var{intel}
290 This option specifies instruction mnemonic for matching instructions.
291 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
294 @cindex @samp{-msyntax=} option, i386
295 @cindex @samp{-msyntax=} option, x86-64
296 @item -msyntax=@var{att}
297 @itemx -msyntax=@var{intel}
298 This option specifies instruction syntax when processing instructions.
299 The @code{.att_syntax} and @code{.intel_syntax} directives will
302 @cindex @samp{-mnaked-reg} option, i386
303 @cindex @samp{-mnaked-reg} option, x86-64
305 This opetion specifies that registers don't require a @samp{%} prefix.
306 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
308 @cindex @samp{-madd-bnd-prefix} option, i386
309 @cindex @samp{-madd-bnd-prefix} option, x86-64
310 @item -madd-bnd-prefix
311 This option forces the assembler to add BND prefix to all branches, even
312 if such prefix was not explicitly specified in the source code.
314 @cindex @samp{-mshared} option, i386
315 @cindex @samp{-mshared} option, x86-64
317 On ELF target, the assembler normally optimizes out non-PLT relocations
318 against defined non-weak global branch targets with default visibility.
319 The @samp{-mshared} option tells the assembler to generate code which
320 may go into a shared library where all non-weak global branch targets
321 with default visibility can be preempted. The resulting code is
322 slightly bigger. This option only affects the handling of branch
325 @cindex @samp{-mbig-obj} option, x86-64
327 On x86-64 PE/COFF target this option forces the use of big object file
328 format, which allows more than 32768 sections.
330 @cindex @samp{-momit-lock-prefix=} option, i386
331 @cindex @samp{-momit-lock-prefix=} option, x86-64
332 @item -momit-lock-prefix=@var{no}
333 @itemx -momit-lock-prefix=@var{yes}
334 These options control how the assembler should encode lock prefix.
335 This option is intended as a workaround for processors, that fail on
336 lock prefix. This option can only be safely used with single-core,
337 single-thread computers
338 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
339 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
340 which is the default.
342 @cindex @samp{-mfence-as-lock-add=} option, i386
343 @cindex @samp{-mfence-as-lock-add=} option, x86-64
344 @item -mfence-as-lock-add=@var{no}
345 @itemx -mfence-as-lock-add=@var{yes}
346 These options control how the assembler should encode lfence, mfence and
348 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
349 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
350 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
351 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
352 sfence as usual, which is the default.
354 @cindex @samp{-mrelax-relocations=} option, i386
355 @cindex @samp{-mrelax-relocations=} option, x86-64
356 @item -mrelax-relocations=@var{no}
357 @itemx -mrelax-relocations=@var{yes}
358 These options control whether the assembler should generate relax
359 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
360 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
361 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
362 @option{-mrelax-relocations=@var{no}} will not generate relax
363 relocations. The default can be controlled by a configure option
364 @option{--enable-x86-relax-relocations}.
366 @cindex @samp{-mevexrcig=} option, i386
367 @cindex @samp{-mevexrcig=} option, x86-64
368 @item -mevexrcig=@var{rne}
369 @itemx -mevexrcig=@var{rd}
370 @itemx -mevexrcig=@var{ru}
371 @itemx -mevexrcig=@var{rz}
372 These options control how the assembler should encode SAE-only
373 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
374 of EVEX instruction with 00, which is the default.
375 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
376 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
377 with 01, 10 and 11 RC bits, respectively.
379 @cindex @samp{-mamd64} option, x86-64
380 @cindex @samp{-mintel64} option, x86-64
383 This option specifies that the assembler should accept only AMD64 or
384 Intel64 ISA in 64-bit mode. The default is to accept both.
389 @node i386-Directives
390 @section x86 specific Directives
392 @cindex machine directives, x86
393 @cindex x86 machine directives
396 @cindex @code{lcomm} directive, COFF
397 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
398 Reserve @var{length} (an absolute expression) bytes for a local common
399 denoted by @var{symbol}. The section and value of @var{symbol} are
400 those of the new local common. The addresses are allocated in the bss
401 section, so that at run-time the bytes start off zeroed. Since
402 @var{symbol} is not declared global, it is normally not visible to
403 @code{@value{LD}}. The optional third parameter, @var{alignment},
404 specifies the desired alignment of the symbol in the bss section.
406 This directive is only available for COFF based x86 targets.
408 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
414 @section i386 Syntactical Considerations
416 * i386-Variations:: AT&T Syntax versus Intel Syntax
417 * i386-Chars:: Special Characters
420 @node i386-Variations
421 @subsection AT&T Syntax versus Intel Syntax
423 @cindex i386 intel_syntax pseudo op
424 @cindex intel_syntax pseudo op, i386
425 @cindex i386 att_syntax pseudo op
426 @cindex att_syntax pseudo op, i386
427 @cindex i386 syntax compatibility
428 @cindex syntax compatibility, i386
429 @cindex x86-64 intel_syntax pseudo op
430 @cindex intel_syntax pseudo op, x86-64
431 @cindex x86-64 att_syntax pseudo op
432 @cindex att_syntax pseudo op, x86-64
433 @cindex x86-64 syntax compatibility
434 @cindex syntax compatibility, x86-64
436 @code{@value{AS}} now supports assembly using Intel assembler syntax.
437 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
438 back to the usual AT&T mode for compatibility with the output of
439 @code{@value{GCC}}. Either of these directives may have an optional
440 argument, @code{prefix}, or @code{noprefix} specifying whether registers
441 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
442 different from Intel syntax. We mention these differences because
443 almost all 80386 documents use Intel syntax. Notable differences
444 between the two syntaxes are:
446 @cindex immediate operands, i386
447 @cindex i386 immediate operands
448 @cindex register operands, i386
449 @cindex i386 register operands
450 @cindex jump/call operands, i386
451 @cindex i386 jump/call operands
452 @cindex operand delimiters, i386
454 @cindex immediate operands, x86-64
455 @cindex x86-64 immediate operands
456 @cindex register operands, x86-64
457 @cindex x86-64 register operands
458 @cindex jump/call operands, x86-64
459 @cindex x86-64 jump/call operands
460 @cindex operand delimiters, x86-64
463 AT&T immediate operands are preceded by @samp{$}; Intel immediate
464 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
465 AT&T register operands are preceded by @samp{%}; Intel register operands
466 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
467 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
469 @cindex i386 source, destination operands
470 @cindex source, destination operands; i386
471 @cindex x86-64 source, destination operands
472 @cindex source, destination operands; x86-64
474 AT&T and Intel syntax use the opposite order for source and destination
475 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
476 @samp{source, dest} convention is maintained for compatibility with
477 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
478 instructions with 2 immediate operands, such as the @samp{enter}
479 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
481 @cindex mnemonic suffixes, i386
482 @cindex sizes operands, i386
483 @cindex i386 size suffixes
484 @cindex mnemonic suffixes, x86-64
485 @cindex sizes operands, x86-64
486 @cindex x86-64 size suffixes
488 In AT&T syntax the size of memory operands is determined from the last
489 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
490 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
491 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
492 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
493 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
494 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
497 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
498 instruction with the 64-bit displacement or immediate operand.
500 @cindex return instructions, i386
501 @cindex i386 jump, call, return
502 @cindex return instructions, x86-64
503 @cindex x86-64 jump, call, return
505 Immediate form long jumps and calls are
506 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
508 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
510 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
511 @samp{ret far @var{stack-adjust}}.
513 @cindex sections, i386
514 @cindex i386 sections
515 @cindex sections, x86-64
516 @cindex x86-64 sections
518 The AT&T assembler does not provide support for multiple section
519 programs. Unix style systems expect all programs to be single sections.
523 @subsection Special Characters
525 @cindex line comment character, i386
526 @cindex i386 line comment character
527 The presence of a @samp{#} appearing anywhere on a line indicates the
528 start of a comment that extends to the end of that line.
530 If a @samp{#} appears as the first character of a line then the whole
531 line is treated as a comment, but in this case the line can also be a
532 logical line number directive (@pxref{Comments}) or a preprocessor
533 control command (@pxref{Preprocessing}).
535 If the @option{--divide} command line option has not been specified
536 then the @samp{/} character appearing anywhere on a line also
537 introduces a line comment.
539 @cindex line separator, i386
540 @cindex statement separator, i386
541 @cindex i386 line separator
542 The @samp{;} character can be used to separate statements on the same
546 @section i386-Mnemonics
547 @subsection Instruction Naming
549 @cindex i386 instruction naming
550 @cindex instruction naming, i386
551 @cindex x86-64 instruction naming
552 @cindex instruction naming, x86-64
554 Instruction mnemonics are suffixed with one character modifiers which
555 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
556 and @samp{q} specify byte, word, long and quadruple word operands. If
557 no suffix is specified by an instruction then @code{@value{AS}} tries to
558 fill in the missing suffix based on the destination register operand
559 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
560 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
561 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
562 assembler which assumes that a missing mnemonic suffix implies long
563 operand size. (This incompatibility does not affect compiler output
564 since compilers always explicitly specify the mnemonic suffix.)
566 Almost all instructions have the same names in AT&T and Intel format.
567 There are a few exceptions. The sign extend and zero extend
568 instructions need two sizes to specify them. They need a size to
569 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
570 is accomplished by using two instruction mnemonic suffixes in AT&T
571 syntax. Base names for sign extend and zero extend are
572 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
573 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
574 are tacked on to this base name, the @emph{from} suffix before the
575 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
576 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
577 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
578 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
579 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
582 @cindex encoding options, i386
583 @cindex encoding options, x86-64
585 Different encoding options can be specified via optional mnemonic
586 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
587 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
588 prefers 8bit or 32bit displacement in encoding.
590 @cindex conversion instructions, i386
591 @cindex i386 conversion instructions
592 @cindex conversion instructions, x86-64
593 @cindex x86-64 conversion instructions
594 The Intel-syntax conversion instructions
598 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
601 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
604 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
607 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
610 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
614 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
615 @samp{%rdx:%rax} (x86-64 only),
619 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
620 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
623 @cindex jump instructions, i386
624 @cindex call instructions, i386
625 @cindex jump instructions, x86-64
626 @cindex call instructions, x86-64
627 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
628 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
631 @subsection AT&T Mnemonic versus Intel Mnemonic
633 @cindex i386 mnemonic compatibility
634 @cindex mnemonic compatibility, i386
636 @code{@value{AS}} supports assembly using Intel mnemonic.
637 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
638 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
639 syntax for compatibility with the output of @code{@value{GCC}}.
640 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
641 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
642 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
643 assembler with different mnemonics from those in Intel IA32 specification.
644 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
647 @section Register Naming
649 @cindex i386 registers
650 @cindex registers, i386
651 @cindex x86-64 registers
652 @cindex registers, x86-64
653 Register operands are always prefixed with @samp{%}. The 80386 registers
658 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
659 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
660 frame pointer), and @samp{%esp} (the stack pointer).
663 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
664 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
667 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
668 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
669 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
670 @samp{%cx}, and @samp{%dx})
673 the 6 section registers @samp{%cs} (code section), @samp{%ds}
674 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
678 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
679 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
682 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
683 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
686 the 2 test registers @samp{%tr6} and @samp{%tr7}.
689 the 8 floating point register stack @samp{%st} or equivalently
690 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
691 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
692 These registers are overloaded by 8 MMX registers @samp{%mm0},
693 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
694 @samp{%mm6} and @samp{%mm7}.
697 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
698 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
701 The AMD x86-64 architecture extends the register set by:
705 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
706 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
707 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
711 the 8 extended registers @samp{%r8}--@samp{%r15}.
714 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
717 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
720 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
723 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
726 the 8 debug registers: @samp{%db8}--@samp{%db15}.
729 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
732 With the AVX extensions more registers were made available:
737 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
738 available in 32-bit mode). The bottom 128 bits are overlaid with the
739 @samp{xmm0}--@samp{xmm15} registers.
743 The AVX2 extensions made in 64-bit mode more registers available:
748 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
749 registers @samp{%ymm16}--@samp{%ymm31}.
753 The AVX512 extensions added the following registers:
758 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
759 available in 32-bit mode). The bottom 128 bits are overlaid with the
760 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
761 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
764 the 8 mask registers @samp{%k0}--@samp{%k7}.
769 @section Instruction Prefixes
771 @cindex i386 instruction prefixes
772 @cindex instruction prefixes, i386
773 @cindex prefixes, i386
774 Instruction prefixes are used to modify the following instruction. They
775 are used to repeat string instructions, to provide section overrides, to
776 perform bus lock operations, and to change operand and address sizes.
777 (Most instructions that normally operate on 32-bit operands will use
778 16-bit operands if the instruction has an ``operand size'' prefix.)
779 Instruction prefixes are best written on the same line as the instruction
780 they act upon. For example, the @samp{scas} (scan string) instruction is
784 repne scas %es:(%edi),%al
787 You may also place prefixes on the lines immediately preceding the
788 instruction, but this circumvents checks that @code{@value{AS}} does
789 with prefixes, and will not work with all prefixes.
791 Here is a list of instruction prefixes:
793 @cindex section override prefixes, i386
796 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
797 @samp{fs}, @samp{gs}. These are automatically added by specifying
798 using the @var{section}:@var{memory-operand} form for memory references.
800 @cindex size prefixes, i386
802 Operand/Address size prefixes @samp{data16} and @samp{addr16}
803 change 32-bit operands/addresses into 16-bit operands/addresses,
804 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
805 @code{.code16} section) into 32-bit operands/addresses. These prefixes
806 @emph{must} appear on the same line of code as the instruction they
807 modify. For example, in a 16-bit @code{.code16} section, you might
814 @cindex bus lock prefixes, i386
815 @cindex inhibiting interrupts, i386
817 The bus lock prefix @samp{lock} inhibits interrupts during execution of
818 the instruction it precedes. (This is only valid with certain
819 instructions; see a 80386 manual for details).
821 @cindex coprocessor wait, i386
823 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
824 complete the current instruction. This should never be needed for the
825 80386/80387 combination.
827 @cindex repeat prefixes, i386
829 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
830 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
831 times if the current address size is 16-bits).
832 @cindex REX prefixes, i386
834 The @samp{rex} family of prefixes is used by x86-64 to encode
835 extensions to i386 instruction set. The @samp{rex} prefix has four
836 bits --- an operand size overwrite (@code{64}) used to change operand size
837 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
840 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
841 instruction emits @samp{rex} prefix with all the bits set. By omitting
842 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
843 prefixes as well. Normally, there is no need to write the prefixes
844 explicitly, since gas will automatically generate them based on the
845 instruction operands.
849 @section Memory References
851 @cindex i386 memory references
852 @cindex memory references, i386
853 @cindex x86-64 memory references
854 @cindex memory references, x86-64
855 An Intel syntax indirect memory reference of the form
858 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
862 is translated into the AT&T syntax
865 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
869 where @var{base} and @var{index} are the optional 32-bit base and
870 index registers, @var{disp} is the optional displacement, and
871 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
872 to calculate the address of the operand. If no @var{scale} is
873 specified, @var{scale} is taken to be 1. @var{section} specifies the
874 optional section register for the memory operand, and may override the
875 default section register (see a 80386 manual for section register
876 defaults). Note that section overrides in AT&T syntax @emph{must}
877 be preceded by a @samp{%}. If you specify a section override which
878 coincides with the default section register, @code{@value{AS}} does @emph{not}
879 output any section register override prefixes to assemble the given
880 instruction. Thus, section overrides can be specified to emphasize which
881 section register is used for a given memory operand.
883 Here are some examples of Intel and AT&T style memory references:
886 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
887 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
888 missing, and the default section is used (@samp{%ss} for addressing with
889 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
891 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
892 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
893 @samp{foo}. All other fields are missing. The section register here
894 defaults to @samp{%ds}.
896 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
897 This uses the value pointed to by @samp{foo} as a memory operand.
898 Note that @var{base} and @var{index} are both missing, but there is only
899 @emph{one} @samp{,}. This is a syntactic exception.
901 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
902 This selects the contents of the variable @samp{foo} with section
903 register @var{section} being @samp{%gs}.
906 Absolute (as opposed to PC relative) call and jump operands must be
907 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
908 always chooses PC relative addressing for jump/call labels.
910 Any instruction that has a memory operand, but no register operand,
911 @emph{must} specify its size (byte, word, long, or quadruple) with an
912 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
915 The x86-64 architecture adds an RIP (instruction pointer relative)
916 addressing. This addressing mode is specified by using @samp{rip} as a
917 base register. Only constant offsets are valid. For example:
920 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
921 Points to the address 1234 bytes past the end of the current
924 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
925 Points to the @code{symbol} in RIP relative way, this is shorter than
926 the default absolute addressing.
929 Other addressing modes remain unchanged in x86-64 architecture, except
930 registers used are 64-bit instead of 32-bit.
933 @section Handling of Jump Instructions
935 @cindex jump optimization, i386
936 @cindex i386 jump optimization
937 @cindex jump optimization, x86-64
938 @cindex x86-64 jump optimization
939 Jump instructions are always optimized to use the smallest possible
940 displacements. This is accomplished by using byte (8-bit) displacement
941 jumps whenever the target is sufficiently close. If a byte displacement
942 is insufficient a long displacement is used. We do not support
943 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
944 instruction with the @samp{data16} instruction prefix), since the 80386
945 insists upon masking @samp{%eip} to 16 bits after the word displacement
946 is added. (See also @pxref{i386-Arch})
948 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
949 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
950 displacements, so that if you use these instructions (@code{@value{GCC}} does
951 not use them) you may get an error message (and incorrect code). The AT&T
952 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
963 @section Floating Point
965 @cindex i386 floating point
966 @cindex floating point, i386
967 @cindex x86-64 floating point
968 @cindex floating point, x86-64
969 All 80387 floating point types except packed BCD are supported.
970 (BCD support may be added without much difficulty). These data
971 types are 16-, 32-, and 64- bit integers, and single (32-bit),
972 double (64-bit), and extended (80-bit) precision floating point.
973 Each supported type has an instruction mnemonic suffix and a constructor
974 associated with it. Instruction mnemonic suffixes specify the operand's
975 data type. Constructors build these data types into memory.
977 @cindex @code{float} directive, i386
978 @cindex @code{single} directive, i386
979 @cindex @code{double} directive, i386
980 @cindex @code{tfloat} directive, i386
981 @cindex @code{float} directive, x86-64
982 @cindex @code{single} directive, x86-64
983 @cindex @code{double} directive, x86-64
984 @cindex @code{tfloat} directive, x86-64
987 Floating point constructors are @samp{.float} or @samp{.single},
988 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
989 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
990 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
991 only supports this format via the @samp{fldt} (load 80-bit real to stack
992 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
994 @cindex @code{word} directive, i386
995 @cindex @code{long} directive, i386
996 @cindex @code{int} directive, i386
997 @cindex @code{quad} directive, i386
998 @cindex @code{word} directive, x86-64
999 @cindex @code{long} directive, x86-64
1000 @cindex @code{int} directive, x86-64
1001 @cindex @code{quad} directive, x86-64
1003 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1004 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1005 corresponding instruction mnemonic suffixes are @samp{s} (single),
1006 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1007 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1008 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1009 stack) instructions.
1012 Register to register operations should not use instruction mnemonic suffixes.
1013 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1014 wrote @samp{fst %st, %st(1)}, since all register to register operations
1015 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1016 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1017 then stores the result in the 4 byte location @samp{mem})
1020 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1023 @cindex 3DNow!, i386
1026 @cindex 3DNow!, x86-64
1027 @cindex SIMD, x86-64
1029 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1030 instructions for integer data), available on Intel's Pentium MMX
1031 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1032 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1033 instruction set (SIMD instructions for 32-bit floating point data)
1034 available on AMD's K6-2 processor and possibly others in the future.
1036 Currently, @code{@value{AS}} does not support Intel's floating point
1039 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1040 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1041 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1042 floating point values. The MMX registers cannot be used at the same time
1043 as the floating point stack.
1045 See Intel and AMD documentation, keeping in mind that the operand order in
1046 instructions is reversed from the Intel syntax.
1049 @section AMD's Lightweight Profiling Instructions
1054 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1055 instruction set, available on AMD's Family 15h (Orochi) processors.
1057 LWP enables applications to collect and manage performance data, and
1058 react to performance events. The collection of performance data
1059 requires no context switches. LWP runs in the context of a thread and
1060 so several counters can be used independently across multiple threads.
1061 LWP can be used in both 64-bit and legacy 32-bit modes.
1063 For detailed information on the LWP instruction set, see the
1064 @cite{AMD Lightweight Profiling Specification} available at
1065 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1068 @section Bit Manipulation Instructions
1073 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1075 BMI instructions provide several instructions implementing individual
1076 bit manipulation operations such as isolation, masking, setting, or
1079 @c Need to add a specification citation here when available.
1082 @section AMD's Trailing Bit Manipulation Instructions
1087 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1088 instruction set, available on AMD's BDVER2 processors (Trinity and
1091 TBM instructions provide instructions implementing individual bit
1092 manipulation operations such as isolating, masking, setting, resetting,
1093 complementing, and operations on trailing zeros and ones.
1095 @c Need to add a specification citation here when available.
1098 @section Writing 16-bit Code
1100 @cindex i386 16-bit code
1101 @cindex 16-bit code, i386
1102 @cindex real-mode code, i386
1103 @cindex @code{code16gcc} directive, i386
1104 @cindex @code{code16} directive, i386
1105 @cindex @code{code32} directive, i386
1106 @cindex @code{code64} directive, i386
1107 @cindex @code{code64} directive, x86-64
1108 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1109 or 64-bit x86-64 code depending on the default configuration,
1110 it also supports writing code to run in real mode or in 16-bit protected
1111 mode code segments. To do this, put a @samp{.code16} or
1112 @samp{.code16gcc} directive before the assembly language instructions to
1113 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1114 32-bit code with the @samp{.code32} directive or 64-bit code with the
1115 @samp{.code64} directive.
1117 @samp{.code16gcc} provides experimental support for generating 16-bit
1118 code from gcc, and differs from @samp{.code16} in that @samp{call},
1119 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1120 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1121 default to 32-bit size. This is so that the stack pointer is
1122 manipulated in the same way over function calls, allowing access to
1123 function parameters at the same stack offsets as in 32-bit mode.
1124 @samp{.code16gcc} also automatically adds address size prefixes where
1125 necessary to use the 32-bit addressing modes that gcc generates.
1127 The code which @code{@value{AS}} generates in 16-bit mode will not
1128 necessarily run on a 16-bit pre-80386 processor. To write code that
1129 runs on such a processor, you must refrain from using @emph{any} 32-bit
1130 constructs which require @code{@value{AS}} to output address or operand
1133 Note that writing 16-bit code instructions by explicitly specifying a
1134 prefix or an instruction mnemonic suffix within a 32-bit code section
1135 generates different machine instructions than those generated for a
1136 16-bit code segment. In a 32-bit code section, the following code
1137 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1138 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1144 The same code in a 16-bit code section would generate the machine
1145 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1146 is correct since the processor default operand size is assumed to be 16
1147 bits in a 16-bit code section.
1150 @section Specifying CPU Architecture
1152 @cindex arch directive, i386
1153 @cindex i386 arch directive
1154 @cindex arch directive, x86-64
1155 @cindex x86-64 arch directive
1157 @code{@value{AS}} may be told to assemble for a particular CPU
1158 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1159 directive enables a warning when gas detects an instruction that is not
1160 supported on the CPU specified. The choices for @var{cpu_type} are:
1162 @multitable @columnfractions .20 .20 .20 .20
1163 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1164 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1165 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1166 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1167 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1168 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1169 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1170 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1171 @item @samp{generic32} @tab @samp{generic64}
1172 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1173 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1174 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1175 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1176 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1177 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1178 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1179 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1180 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1181 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1182 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1183 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1184 @item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit}
1185 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1186 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1187 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1188 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpid}
1191 Apart from the warning, there are only two other effects on
1192 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1193 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1194 will automatically use a two byte opcode sequence. The larger three
1195 byte opcode sequence is used on the 486 (and when no architecture is
1196 specified) because it executes faster on the 486. Note that you can
1197 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1198 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1199 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1200 conditional jumps will be promoted when necessary to a two instruction
1201 sequence consisting of a conditional jump of the opposite sense around
1202 an unconditional jump to the target.
1204 Following the CPU architecture (but not a sub-architecture, which are those
1205 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1206 control automatic promotion of conditional jumps. @samp{jumps} is the
1207 default, and enables jump promotion; All external jumps will be of the long
1208 variety, and file-local jumps will be promoted as necessary.
1209 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1210 byte offset jumps, and warns about file-local conditional jumps that
1211 @code{@value{AS}} promotes.
1212 Unconditional jumps are treated as for @samp{jumps}.
1221 @section AT&T Syntax bugs
1223 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1224 assemblers, generate floating point instructions with reversed source
1225 and destination registers in certain cases. Unfortunately, gcc and
1226 possibly many other programs use this reversed syntax, so we're stuck
1235 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1236 than the expected @samp{%st(3) - %st}. This happens with all the
1237 non-commutative arithmetic floating point operations with two register
1238 operands where the source register is @samp{%st} and the destination
1239 register is @samp{%st(i)}.
1244 @cindex i386 @code{mul}, @code{imul} instructions
1245 @cindex @code{mul} instruction, i386
1246 @cindex @code{imul} instruction, i386
1247 @cindex @code{mul} instruction, x86-64
1248 @cindex @code{imul} instruction, x86-64
1249 There is some trickery concerning the @samp{mul} and @samp{imul}
1250 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1251 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1252 for @samp{imul}) can be output only in the one operand form. Thus,
1253 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1254 the expanding multiply would clobber the @samp{%edx} register, and this
1255 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1256 64-bit product in @samp{%edx:%eax}.
1258 We have added a two operand form of @samp{imul} when the first operand
1259 is an immediate mode expression and the second operand is a register.
1260 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1261 example, can be done with @samp{imul $69, %eax} rather than @samp{imul