1 @c Copyright (C) 1991-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78 byte nop (0x90) is explicitly specified as the fill byte for alignment.
80 @cindex @samp{--divide} option, i386
82 On SVR4-derived platforms, the character @samp{/} is treated as a comment
83 character, which means that it cannot be used in expressions. The
84 @samp{--divide} option turns @samp{/} into a normal character. This does
85 not disable @samp{/} at the beginning of a line starting a comment, or
86 affect using @samp{#} for starting a comment.
88 @cindex @samp{-march=} option, i386
89 @cindex @samp{-march=} option, x86-64
90 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91 This option specifies the target processor. The assembler will
92 issue an error message if an attempt is made to assemble an instruction
93 which will not execute on the target processor. The following
94 processor names are recognized:
132 In addition to the basic instruction set, the assembler can be told to
133 accept various extension mnemonics. For example,
134 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
135 @var{vmx}. The following extensions are currently supported:
196 @code{avx512_4fmaps},
197 @code{avx512_4vnniw},
198 @code{avx512_vpopcntdq},
201 @code{avx512_bitalg},
212 @code{noavx512_4fmaps},
213 @code{noavx512_4vnniw},
214 @code{noavx512_vpopcntdq},
215 @code{noavx512_vbmi2},
216 @code{noavx512_vnni},
217 @code{noavx512_bitalg},
218 @code{noavx512_bf16},
259 Note that rather than extending a basic instruction set, the extension
260 mnemonics starting with @code{no} revoke the respective functionality.
262 When the @code{.arch} directive is used with @option{-march}, the
263 @code{.arch} directive will take precedent.
265 @cindex @samp{-mtune=} option, i386
266 @cindex @samp{-mtune=} option, x86-64
267 @item -mtune=@var{CPU}
268 This option specifies a processor to optimize for. When used in
269 conjunction with the @option{-march} option, only instructions
270 of the processor specified by the @option{-march} option will be
273 Valid @var{CPU} values are identical to the processor list of
274 @option{-march=@var{CPU}}.
276 @cindex @samp{-msse2avx} option, i386
277 @cindex @samp{-msse2avx} option, x86-64
279 This option specifies that the assembler should encode SSE instructions
282 @cindex @samp{-msse-check=} option, i386
283 @cindex @samp{-msse-check=} option, x86-64
284 @item -msse-check=@var{none}
285 @itemx -msse-check=@var{warning}
286 @itemx -msse-check=@var{error}
287 These options control if the assembler should check SSE instructions.
288 @option{-msse-check=@var{none}} will make the assembler not to check SSE
289 instructions, which is the default. @option{-msse-check=@var{warning}}
290 will make the assembler issue a warning for any SSE instruction.
291 @option{-msse-check=@var{error}} will make the assembler issue an error
292 for any SSE instruction.
294 @cindex @samp{-mavxscalar=} option, i386
295 @cindex @samp{-mavxscalar=} option, x86-64
296 @item -mavxscalar=@var{128}
297 @itemx -mavxscalar=@var{256}
298 These options control how the assembler should encode scalar AVX
299 instructions. @option{-mavxscalar=@var{128}} will encode scalar
300 AVX instructions with 128bit vector length, which is the default.
301 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
302 with 256bit vector length.
304 @cindex @samp{-mvexwig=} option, i386
305 @cindex @samp{-mvexwig=} option, x86-64
306 @item -mvexwig=@var{0}
307 @itemx -mvexwig=@var{1}
308 These options control how the assembler should encode VEX.W-ignored (WIG)
309 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
310 instructions with vex.w = 0, which is the default.
311 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
314 @cindex @samp{-mevexlig=} option, i386
315 @cindex @samp{-mevexlig=} option, x86-64
316 @item -mevexlig=@var{128}
317 @itemx -mevexlig=@var{256}
318 @itemx -mevexlig=@var{512}
319 These options control how the assembler should encode length-ignored
320 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
321 EVEX instructions with 128bit vector length, which is the default.
322 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
323 encode LIG EVEX instructions with 256bit and 512bit vector length,
326 @cindex @samp{-mevexwig=} option, i386
327 @cindex @samp{-mevexwig=} option, x86-64
328 @item -mevexwig=@var{0}
329 @itemx -mevexwig=@var{1}
330 These options control how the assembler should encode w-ignored (WIG)
331 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
332 EVEX instructions with evex.w = 0, which is the default.
333 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
336 @cindex @samp{-mmnemonic=} option, i386
337 @cindex @samp{-mmnemonic=} option, x86-64
338 @item -mmnemonic=@var{att}
339 @itemx -mmnemonic=@var{intel}
340 This option specifies instruction mnemonic for matching instructions.
341 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
344 @cindex @samp{-msyntax=} option, i386
345 @cindex @samp{-msyntax=} option, x86-64
346 @item -msyntax=@var{att}
347 @itemx -msyntax=@var{intel}
348 This option specifies instruction syntax when processing instructions.
349 The @code{.att_syntax} and @code{.intel_syntax} directives will
352 @cindex @samp{-mnaked-reg} option, i386
353 @cindex @samp{-mnaked-reg} option, x86-64
355 This option specifies that registers don't require a @samp{%} prefix.
356 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
358 @cindex @samp{-madd-bnd-prefix} option, i386
359 @cindex @samp{-madd-bnd-prefix} option, x86-64
360 @item -madd-bnd-prefix
361 This option forces the assembler to add BND prefix to all branches, even
362 if such prefix was not explicitly specified in the source code.
364 @cindex @samp{-mshared} option, i386
365 @cindex @samp{-mshared} option, x86-64
367 On ELF target, the assembler normally optimizes out non-PLT relocations
368 against defined non-weak global branch targets with default visibility.
369 The @samp{-mshared} option tells the assembler to generate code which
370 may go into a shared library where all non-weak global branch targets
371 with default visibility can be preempted. The resulting code is
372 slightly bigger. This option only affects the handling of branch
375 @cindex @samp{-mbig-obj} option, x86-64
377 On x86-64 PE/COFF target this option forces the use of big object file
378 format, which allows more than 32768 sections.
380 @cindex @samp{-momit-lock-prefix=} option, i386
381 @cindex @samp{-momit-lock-prefix=} option, x86-64
382 @item -momit-lock-prefix=@var{no}
383 @itemx -momit-lock-prefix=@var{yes}
384 These options control how the assembler should encode lock prefix.
385 This option is intended as a workaround for processors, that fail on
386 lock prefix. This option can only be safely used with single-core,
387 single-thread computers
388 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
389 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
390 which is the default.
392 @cindex @samp{-mfence-as-lock-add=} option, i386
393 @cindex @samp{-mfence-as-lock-add=} option, x86-64
394 @item -mfence-as-lock-add=@var{no}
395 @itemx -mfence-as-lock-add=@var{yes}
396 These options control how the assembler should encode lfence, mfence and
398 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
399 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
400 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
401 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
402 sfence as usual, which is the default.
404 @cindex @samp{-mrelax-relocations=} option, i386
405 @cindex @samp{-mrelax-relocations=} option, x86-64
406 @item -mrelax-relocations=@var{no}
407 @itemx -mrelax-relocations=@var{yes}
408 These options control whether the assembler should generate relax
409 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
410 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
411 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
412 @option{-mrelax-relocations=@var{no}} will not generate relax
413 relocations. The default can be controlled by a configure option
414 @option{--enable-x86-relax-relocations}.
416 @cindex @samp{-mx86-used-note=} option, i386
417 @cindex @samp{-mx86-used-note=} option, x86-64
418 @item -mx86-used-note=@var{no}
419 @itemx -mx86-used-note=@var{yes}
420 These options control whether the assembler should generate
421 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
422 GNU property notes. The default can be controlled by the
423 @option{--enable-x86-used-note} configure option.
425 @cindex @samp{-mevexrcig=} option, i386
426 @cindex @samp{-mevexrcig=} option, x86-64
427 @item -mevexrcig=@var{rne}
428 @itemx -mevexrcig=@var{rd}
429 @itemx -mevexrcig=@var{ru}
430 @itemx -mevexrcig=@var{rz}
431 These options control how the assembler should encode SAE-only
432 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
433 of EVEX instruction with 00, which is the default.
434 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
435 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
436 with 01, 10 and 11 RC bits, respectively.
438 @cindex @samp{-mamd64} option, x86-64
439 @cindex @samp{-mintel64} option, x86-64
442 This option specifies that the assembler should accept only AMD64 or
443 Intel64 ISA in 64-bit mode. The default is to accept both.
445 @cindex @samp{-O0} option, i386
446 @cindex @samp{-O0} option, x86-64
447 @cindex @samp{-O} option, i386
448 @cindex @samp{-O} option, x86-64
449 @cindex @samp{-O1} option, i386
450 @cindex @samp{-O1} option, x86-64
451 @cindex @samp{-O2} option, i386
452 @cindex @samp{-O2} option, x86-64
453 @cindex @samp{-Os} option, i386
454 @cindex @samp{-Os} option, x86-64
455 @item -O0 | -O | -O1 | -O2 | -Os
456 Optimize instruction encoding with smaller instruction size. @samp{-O}
457 and @samp{-O1} encode 64-bit register load instructions with 64-bit
458 immediate as 32-bit register load instructions with 31-bit or 32-bits
459 immediates, encode 64-bit register clearing instructions with 32-bit
460 register clearing instructions and encode 256-bit/512-bit VEX/EVEX
461 vector register clearing instructions with 128-bit VEX vector register
462 clearing instructions as well as encode 128-bit/256-bit EVEX vector
463 register load/store instructions with VEX vector register load/store
464 instructions. @samp{-O2} includes @samp{-O1} optimization plus
465 encodes 256-bit/512-bit EVEX vector register clearing instructions with
466 128-bit EVEX vector register clearing instructions.
467 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
468 and 64-bit register tests with immediate as 8-bit register test with
469 immediate. @samp{-O0} turns off this optimization.
474 @node i386-Directives
475 @section x86 specific Directives
477 @cindex machine directives, x86
478 @cindex x86 machine directives
481 @cindex @code{lcomm} directive, COFF
482 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
483 Reserve @var{length} (an absolute expression) bytes for a local common
484 denoted by @var{symbol}. The section and value of @var{symbol} are
485 those of the new local common. The addresses are allocated in the bss
486 section, so that at run-time the bytes start off zeroed. Since
487 @var{symbol} is not declared global, it is normally not visible to
488 @code{@value{LD}}. The optional third parameter, @var{alignment},
489 specifies the desired alignment of the symbol in the bss section.
491 This directive is only available for COFF based x86 targets.
493 @cindex @code{largecomm} directive, ELF
494 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
495 This directive behaves in the same way as the @code{comm} directive
496 except that the data is placed into the @var{.lbss} section instead of
497 the @var{.bss} section @ref{Comm}.
499 The directive is intended to be used for data which requires a large
500 amount of space, and it is only available for ELF based x86_64
503 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
508 @section i386 Syntactical Considerations
510 * i386-Variations:: AT&T Syntax versus Intel Syntax
511 * i386-Chars:: Special Characters
514 @node i386-Variations
515 @subsection AT&T Syntax versus Intel Syntax
517 @cindex i386 intel_syntax pseudo op
518 @cindex intel_syntax pseudo op, i386
519 @cindex i386 att_syntax pseudo op
520 @cindex att_syntax pseudo op, i386
521 @cindex i386 syntax compatibility
522 @cindex syntax compatibility, i386
523 @cindex x86-64 intel_syntax pseudo op
524 @cindex intel_syntax pseudo op, x86-64
525 @cindex x86-64 att_syntax pseudo op
526 @cindex att_syntax pseudo op, x86-64
527 @cindex x86-64 syntax compatibility
528 @cindex syntax compatibility, x86-64
530 @code{@value{AS}} now supports assembly using Intel assembler syntax.
531 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
532 back to the usual AT&T mode for compatibility with the output of
533 @code{@value{GCC}}. Either of these directives may have an optional
534 argument, @code{prefix}, or @code{noprefix} specifying whether registers
535 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
536 different from Intel syntax. We mention these differences because
537 almost all 80386 documents use Intel syntax. Notable differences
538 between the two syntaxes are:
540 @cindex immediate operands, i386
541 @cindex i386 immediate operands
542 @cindex register operands, i386
543 @cindex i386 register operands
544 @cindex jump/call operands, i386
545 @cindex i386 jump/call operands
546 @cindex operand delimiters, i386
548 @cindex immediate operands, x86-64
549 @cindex x86-64 immediate operands
550 @cindex register operands, x86-64
551 @cindex x86-64 register operands
552 @cindex jump/call operands, x86-64
553 @cindex x86-64 jump/call operands
554 @cindex operand delimiters, x86-64
557 AT&T immediate operands are preceded by @samp{$}; Intel immediate
558 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
559 AT&T register operands are preceded by @samp{%}; Intel register operands
560 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
561 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
563 @cindex i386 source, destination operands
564 @cindex source, destination operands; i386
565 @cindex x86-64 source, destination operands
566 @cindex source, destination operands; x86-64
568 AT&T and Intel syntax use the opposite order for source and destination
569 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
570 @samp{source, dest} convention is maintained for compatibility with
571 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
572 instructions with 2 immediate operands, such as the @samp{enter}
573 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
575 @cindex mnemonic suffixes, i386
576 @cindex sizes operands, i386
577 @cindex i386 size suffixes
578 @cindex mnemonic suffixes, x86-64
579 @cindex sizes operands, x86-64
580 @cindex x86-64 size suffixes
582 In AT&T syntax the size of memory operands is determined from the last
583 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
584 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
585 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
586 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
587 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
588 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
591 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
592 instruction with the 64-bit displacement or immediate operand.
594 @cindex return instructions, i386
595 @cindex i386 jump, call, return
596 @cindex return instructions, x86-64
597 @cindex x86-64 jump, call, return
599 Immediate form long jumps and calls are
600 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
602 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
604 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
605 @samp{ret far @var{stack-adjust}}.
607 @cindex sections, i386
608 @cindex i386 sections
609 @cindex sections, x86-64
610 @cindex x86-64 sections
612 The AT&T assembler does not provide support for multiple section
613 programs. Unix style systems expect all programs to be single sections.
617 @subsection Special Characters
619 @cindex line comment character, i386
620 @cindex i386 line comment character
621 The presence of a @samp{#} appearing anywhere on a line indicates the
622 start of a comment that extends to the end of that line.
624 If a @samp{#} appears as the first character of a line then the whole
625 line is treated as a comment, but in this case the line can also be a
626 logical line number directive (@pxref{Comments}) or a preprocessor
627 control command (@pxref{Preprocessing}).
629 If the @option{--divide} command-line option has not been specified
630 then the @samp{/} character appearing anywhere on a line also
631 introduces a line comment.
633 @cindex line separator, i386
634 @cindex statement separator, i386
635 @cindex i386 line separator
636 The @samp{;} character can be used to separate statements on the same
640 @section i386-Mnemonics
641 @subsection Instruction Naming
643 @cindex i386 instruction naming
644 @cindex instruction naming, i386
645 @cindex x86-64 instruction naming
646 @cindex instruction naming, x86-64
648 Instruction mnemonics are suffixed with one character modifiers which
649 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
650 and @samp{q} specify byte, word, long and quadruple word operands. If
651 no suffix is specified by an instruction then @code{@value{AS}} tries to
652 fill in the missing suffix based on the destination register operand
653 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
654 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
655 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
656 assembler which assumes that a missing mnemonic suffix implies long
657 operand size. (This incompatibility does not affect compiler output
658 since compilers always explicitly specify the mnemonic suffix.)
660 Almost all instructions have the same names in AT&T and Intel format.
661 There are a few exceptions. The sign extend and zero extend
662 instructions need two sizes to specify them. They need a size to
663 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
664 is accomplished by using two instruction mnemonic suffixes in AT&T
665 syntax. Base names for sign extend and zero extend are
666 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
667 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
668 are tacked on to this base name, the @emph{from} suffix before the
669 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
670 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
671 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
672 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
673 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
676 @cindex encoding options, i386
677 @cindex encoding options, x86-64
679 Different encoding options can be specified via pseudo prefixes:
683 @samp{@{disp8@}} -- prefer 8-bit displacement.
686 @samp{@{disp32@}} -- prefer 32-bit displacement.
689 @samp{@{load@}} -- prefer load-form instruction.
692 @samp{@{store@}} -- prefer store-form instruction.
695 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
698 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
701 @samp{@{evex@}} -- encode with EVEX prefix.
704 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
705 instructions (x86-64 only). Note that this differs from the @samp{rex}
706 prefix which generates REX prefix unconditionally.
709 @samp{@{nooptimize@}} -- disable instruction size optimization.
712 @cindex conversion instructions, i386
713 @cindex i386 conversion instructions
714 @cindex conversion instructions, x86-64
715 @cindex x86-64 conversion instructions
716 The Intel-syntax conversion instructions
720 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
723 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
726 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
729 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
732 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
736 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
737 @samp{%rdx:%rax} (x86-64 only),
741 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
742 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
745 @cindex jump instructions, i386
746 @cindex call instructions, i386
747 @cindex jump instructions, x86-64
748 @cindex call instructions, x86-64
749 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
750 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
753 @subsection AT&T Mnemonic versus Intel Mnemonic
755 @cindex i386 mnemonic compatibility
756 @cindex mnemonic compatibility, i386
758 @code{@value{AS}} supports assembly using Intel mnemonic.
759 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
760 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
761 syntax for compatibility with the output of @code{@value{GCC}}.
762 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
763 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
764 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
765 assembler with different mnemonics from those in Intel IA32 specification.
766 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
769 @section Register Naming
771 @cindex i386 registers
772 @cindex registers, i386
773 @cindex x86-64 registers
774 @cindex registers, x86-64
775 Register operands are always prefixed with @samp{%}. The 80386 registers
780 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
781 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
782 frame pointer), and @samp{%esp} (the stack pointer).
785 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
786 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
789 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
790 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
791 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
792 @samp{%cx}, and @samp{%dx})
795 the 6 section registers @samp{%cs} (code section), @samp{%ds}
796 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
800 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
801 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
804 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
805 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
808 the 2 test registers @samp{%tr6} and @samp{%tr7}.
811 the 8 floating point register stack @samp{%st} or equivalently
812 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
813 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
814 These registers are overloaded by 8 MMX registers @samp{%mm0},
815 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
816 @samp{%mm6} and @samp{%mm7}.
819 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
820 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
823 The AMD x86-64 architecture extends the register set by:
827 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
828 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
829 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
833 the 8 extended registers @samp{%r8}--@samp{%r15}.
836 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
839 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
842 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
845 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
848 the 8 debug registers: @samp{%db8}--@samp{%db15}.
851 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
854 With the AVX extensions more registers were made available:
859 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
860 available in 32-bit mode). The bottom 128 bits are overlaid with the
861 @samp{xmm0}--@samp{xmm15} registers.
865 The AVX2 extensions made in 64-bit mode more registers available:
870 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
871 registers @samp{%ymm16}--@samp{%ymm31}.
875 The AVX512 extensions added the following registers:
880 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
881 available in 32-bit mode). The bottom 128 bits are overlaid with the
882 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
883 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
886 the 8 mask registers @samp{%k0}--@samp{%k7}.
891 @section Instruction Prefixes
893 @cindex i386 instruction prefixes
894 @cindex instruction prefixes, i386
895 @cindex prefixes, i386
896 Instruction prefixes are used to modify the following instruction. They
897 are used to repeat string instructions, to provide section overrides, to
898 perform bus lock operations, and to change operand and address sizes.
899 (Most instructions that normally operate on 32-bit operands will use
900 16-bit operands if the instruction has an ``operand size'' prefix.)
901 Instruction prefixes are best written on the same line as the instruction
902 they act upon. For example, the @samp{scas} (scan string) instruction is
906 repne scas %es:(%edi),%al
909 You may also place prefixes on the lines immediately preceding the
910 instruction, but this circumvents checks that @code{@value{AS}} does
911 with prefixes, and will not work with all prefixes.
913 Here is a list of instruction prefixes:
915 @cindex section override prefixes, i386
918 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
919 @samp{fs}, @samp{gs}. These are automatically added by specifying
920 using the @var{section}:@var{memory-operand} form for memory references.
922 @cindex size prefixes, i386
924 Operand/Address size prefixes @samp{data16} and @samp{addr16}
925 change 32-bit operands/addresses into 16-bit operands/addresses,
926 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
927 @code{.code16} section) into 32-bit operands/addresses. These prefixes
928 @emph{must} appear on the same line of code as the instruction they
929 modify. For example, in a 16-bit @code{.code16} section, you might
936 @cindex bus lock prefixes, i386
937 @cindex inhibiting interrupts, i386
939 The bus lock prefix @samp{lock} inhibits interrupts during execution of
940 the instruction it precedes. (This is only valid with certain
941 instructions; see a 80386 manual for details).
943 @cindex coprocessor wait, i386
945 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
946 complete the current instruction. This should never be needed for the
947 80386/80387 combination.
949 @cindex repeat prefixes, i386
951 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
952 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
953 times if the current address size is 16-bits).
954 @cindex REX prefixes, i386
956 The @samp{rex} family of prefixes is used by x86-64 to encode
957 extensions to i386 instruction set. The @samp{rex} prefix has four
958 bits --- an operand size overwrite (@code{64}) used to change operand size
959 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
962 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
963 instruction emits @samp{rex} prefix with all the bits set. By omitting
964 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
965 prefixes as well. Normally, there is no need to write the prefixes
966 explicitly, since gas will automatically generate them based on the
967 instruction operands.
971 @section Memory References
973 @cindex i386 memory references
974 @cindex memory references, i386
975 @cindex x86-64 memory references
976 @cindex memory references, x86-64
977 An Intel syntax indirect memory reference of the form
980 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
984 is translated into the AT&T syntax
987 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
991 where @var{base} and @var{index} are the optional 32-bit base and
992 index registers, @var{disp} is the optional displacement, and
993 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
994 to calculate the address of the operand. If no @var{scale} is
995 specified, @var{scale} is taken to be 1. @var{section} specifies the
996 optional section register for the memory operand, and may override the
997 default section register (see a 80386 manual for section register
998 defaults). Note that section overrides in AT&T syntax @emph{must}
999 be preceded by a @samp{%}. If you specify a section override which
1000 coincides with the default section register, @code{@value{AS}} does @emph{not}
1001 output any section register override prefixes to assemble the given
1002 instruction. Thus, section overrides can be specified to emphasize which
1003 section register is used for a given memory operand.
1005 Here are some examples of Intel and AT&T style memory references:
1008 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1009 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1010 missing, and the default section is used (@samp{%ss} for addressing with
1011 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1013 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1014 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1015 @samp{foo}. All other fields are missing. The section register here
1016 defaults to @samp{%ds}.
1018 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1019 This uses the value pointed to by @samp{foo} as a memory operand.
1020 Note that @var{base} and @var{index} are both missing, but there is only
1021 @emph{one} @samp{,}. This is a syntactic exception.
1023 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1024 This selects the contents of the variable @samp{foo} with section
1025 register @var{section} being @samp{%gs}.
1028 Absolute (as opposed to PC relative) call and jump operands must be
1029 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1030 always chooses PC relative addressing for jump/call labels.
1032 Any instruction that has a memory operand, but no register operand,
1033 @emph{must} specify its size (byte, word, long, or quadruple) with an
1034 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1037 The x86-64 architecture adds an RIP (instruction pointer relative)
1038 addressing. This addressing mode is specified by using @samp{rip} as a
1039 base register. Only constant offsets are valid. For example:
1042 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1043 Points to the address 1234 bytes past the end of the current
1046 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1047 Points to the @code{symbol} in RIP relative way, this is shorter than
1048 the default absolute addressing.
1051 Other addressing modes remain unchanged in x86-64 architecture, except
1052 registers used are 64-bit instead of 32-bit.
1055 @section Handling of Jump Instructions
1057 @cindex jump optimization, i386
1058 @cindex i386 jump optimization
1059 @cindex jump optimization, x86-64
1060 @cindex x86-64 jump optimization
1061 Jump instructions are always optimized to use the smallest possible
1062 displacements. This is accomplished by using byte (8-bit) displacement
1063 jumps whenever the target is sufficiently close. If a byte displacement
1064 is insufficient a long displacement is used. We do not support
1065 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1066 instruction with the @samp{data16} instruction prefix), since the 80386
1067 insists upon masking @samp{%eip} to 16 bits after the word displacement
1068 is added. (See also @pxref{i386-Arch})
1070 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1071 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1072 displacements, so that if you use these instructions (@code{@value{GCC}} does
1073 not use them) you may get an error message (and incorrect code). The AT&T
1074 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1085 @section Floating Point
1087 @cindex i386 floating point
1088 @cindex floating point, i386
1089 @cindex x86-64 floating point
1090 @cindex floating point, x86-64
1091 All 80387 floating point types except packed BCD are supported.
1092 (BCD support may be added without much difficulty). These data
1093 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1094 double (64-bit), and extended (80-bit) precision floating point.
1095 Each supported type has an instruction mnemonic suffix and a constructor
1096 associated with it. Instruction mnemonic suffixes specify the operand's
1097 data type. Constructors build these data types into memory.
1099 @cindex @code{float} directive, i386
1100 @cindex @code{single} directive, i386
1101 @cindex @code{double} directive, i386
1102 @cindex @code{tfloat} directive, i386
1103 @cindex @code{float} directive, x86-64
1104 @cindex @code{single} directive, x86-64
1105 @cindex @code{double} directive, x86-64
1106 @cindex @code{tfloat} directive, x86-64
1109 Floating point constructors are @samp{.float} or @samp{.single},
1110 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1111 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1112 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1113 only supports this format via the @samp{fldt} (load 80-bit real to stack
1114 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1116 @cindex @code{word} directive, i386
1117 @cindex @code{long} directive, i386
1118 @cindex @code{int} directive, i386
1119 @cindex @code{quad} directive, i386
1120 @cindex @code{word} directive, x86-64
1121 @cindex @code{long} directive, x86-64
1122 @cindex @code{int} directive, x86-64
1123 @cindex @code{quad} directive, x86-64
1125 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1126 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1127 corresponding instruction mnemonic suffixes are @samp{s} (single),
1128 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1129 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1130 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1131 stack) instructions.
1134 Register to register operations should not use instruction mnemonic suffixes.
1135 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1136 wrote @samp{fst %st, %st(1)}, since all register to register operations
1137 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1138 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1139 then stores the result in the 4 byte location @samp{mem})
1142 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1145 @cindex 3DNow!, i386
1148 @cindex 3DNow!, x86-64
1149 @cindex SIMD, x86-64
1151 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1152 instructions for integer data), available on Intel's Pentium MMX
1153 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1154 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1155 instruction set (SIMD instructions for 32-bit floating point data)
1156 available on AMD's K6-2 processor and possibly others in the future.
1158 Currently, @code{@value{AS}} does not support Intel's floating point
1161 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1162 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1163 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1164 floating point values. The MMX registers cannot be used at the same time
1165 as the floating point stack.
1167 See Intel and AMD documentation, keeping in mind that the operand order in
1168 instructions is reversed from the Intel syntax.
1171 @section AMD's Lightweight Profiling Instructions
1176 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1177 instruction set, available on AMD's Family 15h (Orochi) processors.
1179 LWP enables applications to collect and manage performance data, and
1180 react to performance events. The collection of performance data
1181 requires no context switches. LWP runs in the context of a thread and
1182 so several counters can be used independently across multiple threads.
1183 LWP can be used in both 64-bit and legacy 32-bit modes.
1185 For detailed information on the LWP instruction set, see the
1186 @cite{AMD Lightweight Profiling Specification} available at
1187 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1190 @section Bit Manipulation Instructions
1195 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1197 BMI instructions provide several instructions implementing individual
1198 bit manipulation operations such as isolation, masking, setting, or
1201 @c Need to add a specification citation here when available.
1204 @section AMD's Trailing Bit Manipulation Instructions
1209 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1210 instruction set, available on AMD's BDVER2 processors (Trinity and
1213 TBM instructions provide instructions implementing individual bit
1214 manipulation operations such as isolating, masking, setting, resetting,
1215 complementing, and operations on trailing zeros and ones.
1217 @c Need to add a specification citation here when available.
1220 @section Writing 16-bit Code
1222 @cindex i386 16-bit code
1223 @cindex 16-bit code, i386
1224 @cindex real-mode code, i386
1225 @cindex @code{code16gcc} directive, i386
1226 @cindex @code{code16} directive, i386
1227 @cindex @code{code32} directive, i386
1228 @cindex @code{code64} directive, i386
1229 @cindex @code{code64} directive, x86-64
1230 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1231 or 64-bit x86-64 code depending on the default configuration,
1232 it also supports writing code to run in real mode or in 16-bit protected
1233 mode code segments. To do this, put a @samp{.code16} or
1234 @samp{.code16gcc} directive before the assembly language instructions to
1235 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1236 32-bit code with the @samp{.code32} directive or 64-bit code with the
1237 @samp{.code64} directive.
1239 @samp{.code16gcc} provides experimental support for generating 16-bit
1240 code from gcc, and differs from @samp{.code16} in that @samp{call},
1241 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1242 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1243 default to 32-bit size. This is so that the stack pointer is
1244 manipulated in the same way over function calls, allowing access to
1245 function parameters at the same stack offsets as in 32-bit mode.
1246 @samp{.code16gcc} also automatically adds address size prefixes where
1247 necessary to use the 32-bit addressing modes that gcc generates.
1249 The code which @code{@value{AS}} generates in 16-bit mode will not
1250 necessarily run on a 16-bit pre-80386 processor. To write code that
1251 runs on such a processor, you must refrain from using @emph{any} 32-bit
1252 constructs which require @code{@value{AS}} to output address or operand
1255 Note that writing 16-bit code instructions by explicitly specifying a
1256 prefix or an instruction mnemonic suffix within a 32-bit code section
1257 generates different machine instructions than those generated for a
1258 16-bit code segment. In a 32-bit code section, the following code
1259 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1260 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1266 The same code in a 16-bit code section would generate the machine
1267 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1268 is correct since the processor default operand size is assumed to be 16
1269 bits in a 16-bit code section.
1272 @section Specifying CPU Architecture
1274 @cindex arch directive, i386
1275 @cindex i386 arch directive
1276 @cindex arch directive, x86-64
1277 @cindex x86-64 arch directive
1279 @code{@value{AS}} may be told to assemble for a particular CPU
1280 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1281 directive enables a warning when gas detects an instruction that is not
1282 supported on the CPU specified. The choices for @var{cpu_type} are:
1284 @multitable @columnfractions .20 .20 .20 .20
1285 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1286 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1287 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1288 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1289 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1290 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1291 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1292 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1293 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1294 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1295 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1296 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1297 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1298 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1299 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1300 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1301 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1302 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1303 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1304 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1305 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1306 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1307 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1308 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1309 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16}
1310 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1311 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1312 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1313 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
1314 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1315 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1316 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1317 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1320 Apart from the warning, there are only two other effects on
1321 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1322 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1323 will automatically use a two byte opcode sequence. The larger three
1324 byte opcode sequence is used on the 486 (and when no architecture is
1325 specified) because it executes faster on the 486. Note that you can
1326 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1327 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1328 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1329 conditional jumps will be promoted when necessary to a two instruction
1330 sequence consisting of a conditional jump of the opposite sense around
1331 an unconditional jump to the target.
1333 Following the CPU architecture (but not a sub-architecture, which are those
1334 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1335 control automatic promotion of conditional jumps. @samp{jumps} is the
1336 default, and enables jump promotion; All external jumps will be of the long
1337 variety, and file-local jumps will be promoted as necessary.
1338 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1339 byte offset jumps, and warns about file-local conditional jumps that
1340 @code{@value{AS}} promotes.
1341 Unconditional jumps are treated as for @samp{jumps}.
1350 @section AT&T Syntax bugs
1352 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1353 assemblers, generate floating point instructions with reversed source
1354 and destination registers in certain cases. Unfortunately, gcc and
1355 possibly many other programs use this reversed syntax, so we're stuck
1364 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1365 than the expected @samp{%st(3) - %st}. This happens with all the
1366 non-commutative arithmetic floating point operations with two register
1367 operands where the source register is @samp{%st} and the destination
1368 register is @samp{%st(i)}.
1373 @cindex i386 @code{mul}, @code{imul} instructions
1374 @cindex @code{mul} instruction, i386
1375 @cindex @code{imul} instruction, i386
1376 @cindex @code{mul} instruction, x86-64
1377 @cindex @code{imul} instruction, x86-64
1378 There is some trickery concerning the @samp{mul} and @samp{imul}
1379 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1380 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1381 for @samp{imul}) can be output only in the one operand form. Thus,
1382 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1383 the expanding multiply would clobber the @samp{%edx} register, and this
1384 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1385 64-bit product in @samp{%edx:%eax}.
1387 We have added a two operand form of @samp{imul} when the first operand
1388 is an immediate mode expression and the second operand is a register.
1389 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1390 example, can be done with @samp{imul $69, %eax} rather than @samp{imul
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