1 @c Copyright (C) 1991-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics. For example,
132 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
133 @var{vmx}. The following extensions are currently supported:
183 @code{avx512_4fmaps},
193 @code{noavx512_4fmaps},
230 Note that rather than extending a basic instruction set, the extension
231 mnemonics starting with @code{no} revoke the respective functionality.
233 When the @code{.arch} directive is used with @option{-march}, the
234 @code{.arch} directive will take precedent.
236 @cindex @samp{-mtune=} option, i386
237 @cindex @samp{-mtune=} option, x86-64
238 @item -mtune=@var{CPU}
239 This option specifies a processor to optimize for. When used in
240 conjunction with the @option{-march} option, only instructions
241 of the processor specified by the @option{-march} option will be
244 Valid @var{CPU} values are identical to the processor list of
245 @option{-march=@var{CPU}}.
247 @cindex @samp{-msse2avx} option, i386
248 @cindex @samp{-msse2avx} option, x86-64
250 This option specifies that the assembler should encode SSE instructions
253 @cindex @samp{-msse-check=} option, i386
254 @cindex @samp{-msse-check=} option, x86-64
255 @item -msse-check=@var{none}
256 @itemx -msse-check=@var{warning}
257 @itemx -msse-check=@var{error}
258 These options control if the assembler should check SSE instructions.
259 @option{-msse-check=@var{none}} will make the assembler not to check SSE
260 instructions, which is the default. @option{-msse-check=@var{warning}}
261 will make the assembler issue a warning for any SSE instruction.
262 @option{-msse-check=@var{error}} will make the assembler issue an error
263 for any SSE instruction.
265 @cindex @samp{-mavxscalar=} option, i386
266 @cindex @samp{-mavxscalar=} option, x86-64
267 @item -mavxscalar=@var{128}
268 @itemx -mavxscalar=@var{256}
269 These options control how the assembler should encode scalar AVX
270 instructions. @option{-mavxscalar=@var{128}} will encode scalar
271 AVX instructions with 128bit vector length, which is the default.
272 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
273 with 256bit vector length.
275 @cindex @samp{-mevexlig=} option, i386
276 @cindex @samp{-mevexlig=} option, x86-64
277 @item -mevexlig=@var{128}
278 @itemx -mevexlig=@var{256}
279 @itemx -mevexlig=@var{512}
280 These options control how the assembler should encode length-ignored
281 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
282 EVEX instructions with 128bit vector length, which is the default.
283 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
284 encode LIG EVEX instructions with 256bit and 512bit vector length,
287 @cindex @samp{-mevexwig=} option, i386
288 @cindex @samp{-mevexwig=} option, x86-64
289 @item -mevexwig=@var{0}
290 @itemx -mevexwig=@var{1}
291 These options control how the assembler should encode w-ignored (WIG)
292 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
293 EVEX instructions with evex.w = 0, which is the default.
294 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
297 @cindex @samp{-mmnemonic=} option, i386
298 @cindex @samp{-mmnemonic=} option, x86-64
299 @item -mmnemonic=@var{att}
300 @itemx -mmnemonic=@var{intel}
301 This option specifies instruction mnemonic for matching instructions.
302 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
305 @cindex @samp{-msyntax=} option, i386
306 @cindex @samp{-msyntax=} option, x86-64
307 @item -msyntax=@var{att}
308 @itemx -msyntax=@var{intel}
309 This option specifies instruction syntax when processing instructions.
310 The @code{.att_syntax} and @code{.intel_syntax} directives will
313 @cindex @samp{-mnaked-reg} option, i386
314 @cindex @samp{-mnaked-reg} option, x86-64
316 This opetion specifies that registers don't require a @samp{%} prefix.
317 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
319 @cindex @samp{-madd-bnd-prefix} option, i386
320 @cindex @samp{-madd-bnd-prefix} option, x86-64
321 @item -madd-bnd-prefix
322 This option forces the assembler to add BND prefix to all branches, even
323 if such prefix was not explicitly specified in the source code.
325 @cindex @samp{-mshared} option, i386
326 @cindex @samp{-mshared} option, x86-64
328 On ELF target, the assembler normally optimizes out non-PLT relocations
329 against defined non-weak global branch targets with default visibility.
330 The @samp{-mshared} option tells the assembler to generate code which
331 may go into a shared library where all non-weak global branch targets
332 with default visibility can be preempted. The resulting code is
333 slightly bigger. This option only affects the handling of branch
336 @cindex @samp{-mbig-obj} option, x86-64
338 On x86-64 PE/COFF target this option forces the use of big object file
339 format, which allows more than 32768 sections.
341 @cindex @samp{-momit-lock-prefix=} option, i386
342 @cindex @samp{-momit-lock-prefix=} option, x86-64
343 @item -momit-lock-prefix=@var{no}
344 @itemx -momit-lock-prefix=@var{yes}
345 These options control how the assembler should encode lock prefix.
346 This option is intended as a workaround for processors, that fail on
347 lock prefix. This option can only be safely used with single-core,
348 single-thread computers
349 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
350 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
351 which is the default.
353 @cindex @samp{-mfence-as-lock-add=} option, i386
354 @cindex @samp{-mfence-as-lock-add=} option, x86-64
355 @item -mfence-as-lock-add=@var{no}
356 @itemx -mfence-as-lock-add=@var{yes}
357 These options control how the assembler should encode lfence, mfence and
359 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
360 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
361 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
362 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
363 sfence as usual, which is the default.
365 @cindex @samp{-mrelax-relocations=} option, i386
366 @cindex @samp{-mrelax-relocations=} option, x86-64
367 @item -mrelax-relocations=@var{no}
368 @itemx -mrelax-relocations=@var{yes}
369 These options control whether the assembler should generate relax
370 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
371 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
372 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
373 @option{-mrelax-relocations=@var{no}} will not generate relax
374 relocations. The default can be controlled by a configure option
375 @option{--enable-x86-relax-relocations}.
377 @cindex @samp{-mevexrcig=} option, i386
378 @cindex @samp{-mevexrcig=} option, x86-64
379 @item -mevexrcig=@var{rne}
380 @itemx -mevexrcig=@var{rd}
381 @itemx -mevexrcig=@var{ru}
382 @itemx -mevexrcig=@var{rz}
383 These options control how the assembler should encode SAE-only
384 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
385 of EVEX instruction with 00, which is the default.
386 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
387 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
388 with 01, 10 and 11 RC bits, respectively.
390 @cindex @samp{-mamd64} option, x86-64
391 @cindex @samp{-mintel64} option, x86-64
394 This option specifies that the assembler should accept only AMD64 or
395 Intel64 ISA in 64-bit mode. The default is to accept both.
400 @node i386-Directives
401 @section x86 specific Directives
403 @cindex machine directives, x86
404 @cindex x86 machine directives
407 @cindex @code{lcomm} directive, COFF
408 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
409 Reserve @var{length} (an absolute expression) bytes for a local common
410 denoted by @var{symbol}. The section and value of @var{symbol} are
411 those of the new local common. The addresses are allocated in the bss
412 section, so that at run-time the bytes start off zeroed. Since
413 @var{symbol} is not declared global, it is normally not visible to
414 @code{@value{LD}}. The optional third parameter, @var{alignment},
415 specifies the desired alignment of the symbol in the bss section.
417 This directive is only available for COFF based x86 targets.
419 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
425 @section i386 Syntactical Considerations
427 * i386-Variations:: AT&T Syntax versus Intel Syntax
428 * i386-Chars:: Special Characters
431 @node i386-Variations
432 @subsection AT&T Syntax versus Intel Syntax
434 @cindex i386 intel_syntax pseudo op
435 @cindex intel_syntax pseudo op, i386
436 @cindex i386 att_syntax pseudo op
437 @cindex att_syntax pseudo op, i386
438 @cindex i386 syntax compatibility
439 @cindex syntax compatibility, i386
440 @cindex x86-64 intel_syntax pseudo op
441 @cindex intel_syntax pseudo op, x86-64
442 @cindex x86-64 att_syntax pseudo op
443 @cindex att_syntax pseudo op, x86-64
444 @cindex x86-64 syntax compatibility
445 @cindex syntax compatibility, x86-64
447 @code{@value{AS}} now supports assembly using Intel assembler syntax.
448 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
449 back to the usual AT&T mode for compatibility with the output of
450 @code{@value{GCC}}. Either of these directives may have an optional
451 argument, @code{prefix}, or @code{noprefix} specifying whether registers
452 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
453 different from Intel syntax. We mention these differences because
454 almost all 80386 documents use Intel syntax. Notable differences
455 between the two syntaxes are:
457 @cindex immediate operands, i386
458 @cindex i386 immediate operands
459 @cindex register operands, i386
460 @cindex i386 register operands
461 @cindex jump/call operands, i386
462 @cindex i386 jump/call operands
463 @cindex operand delimiters, i386
465 @cindex immediate operands, x86-64
466 @cindex x86-64 immediate operands
467 @cindex register operands, x86-64
468 @cindex x86-64 register operands
469 @cindex jump/call operands, x86-64
470 @cindex x86-64 jump/call operands
471 @cindex operand delimiters, x86-64
474 AT&T immediate operands are preceded by @samp{$}; Intel immediate
475 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
476 AT&T register operands are preceded by @samp{%}; Intel register operands
477 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
478 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
480 @cindex i386 source, destination operands
481 @cindex source, destination operands; i386
482 @cindex x86-64 source, destination operands
483 @cindex source, destination operands; x86-64
485 AT&T and Intel syntax use the opposite order for source and destination
486 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
487 @samp{source, dest} convention is maintained for compatibility with
488 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
489 instructions with 2 immediate operands, such as the @samp{enter}
490 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
492 @cindex mnemonic suffixes, i386
493 @cindex sizes operands, i386
494 @cindex i386 size suffixes
495 @cindex mnemonic suffixes, x86-64
496 @cindex sizes operands, x86-64
497 @cindex x86-64 size suffixes
499 In AT&T syntax the size of memory operands is determined from the last
500 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
501 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
502 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
503 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
504 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
505 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
508 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
509 instruction with the 64-bit displacement or immediate operand.
511 @cindex return instructions, i386
512 @cindex i386 jump, call, return
513 @cindex return instructions, x86-64
514 @cindex x86-64 jump, call, return
516 Immediate form long jumps and calls are
517 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
519 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
521 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
522 @samp{ret far @var{stack-adjust}}.
524 @cindex sections, i386
525 @cindex i386 sections
526 @cindex sections, x86-64
527 @cindex x86-64 sections
529 The AT&T assembler does not provide support for multiple section
530 programs. Unix style systems expect all programs to be single sections.
534 @subsection Special Characters
536 @cindex line comment character, i386
537 @cindex i386 line comment character
538 The presence of a @samp{#} appearing anywhere on a line indicates the
539 start of a comment that extends to the end of that line.
541 If a @samp{#} appears as the first character of a line then the whole
542 line is treated as a comment, but in this case the line can also be a
543 logical line number directive (@pxref{Comments}) or a preprocessor
544 control command (@pxref{Preprocessing}).
546 If the @option{--divide} command line option has not been specified
547 then the @samp{/} character appearing anywhere on a line also
548 introduces a line comment.
550 @cindex line separator, i386
551 @cindex statement separator, i386
552 @cindex i386 line separator
553 The @samp{;} character can be used to separate statements on the same
557 @section i386-Mnemonics
558 @subsection Instruction Naming
560 @cindex i386 instruction naming
561 @cindex instruction naming, i386
562 @cindex x86-64 instruction naming
563 @cindex instruction naming, x86-64
565 Instruction mnemonics are suffixed with one character modifiers which
566 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
567 and @samp{q} specify byte, word, long and quadruple word operands. If
568 no suffix is specified by an instruction then @code{@value{AS}} tries to
569 fill in the missing suffix based on the destination register operand
570 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
571 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
572 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
573 assembler which assumes that a missing mnemonic suffix implies long
574 operand size. (This incompatibility does not affect compiler output
575 since compilers always explicitly specify the mnemonic suffix.)
577 Almost all instructions have the same names in AT&T and Intel format.
578 There are a few exceptions. The sign extend and zero extend
579 instructions need two sizes to specify them. They need a size to
580 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
581 is accomplished by using two instruction mnemonic suffixes in AT&T
582 syntax. Base names for sign extend and zero extend are
583 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
584 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
585 are tacked on to this base name, the @emph{from} suffix before the
586 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
587 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
588 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
589 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
590 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
593 @cindex encoding options, i386
594 @cindex encoding options, x86-64
596 Different encoding options can be specified via optional mnemonic
597 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
598 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
599 prefers 8bit or 32bit displacement in encoding.
601 @cindex conversion instructions, i386
602 @cindex i386 conversion instructions
603 @cindex conversion instructions, x86-64
604 @cindex x86-64 conversion instructions
605 The Intel-syntax conversion instructions
609 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
612 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
615 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
618 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
621 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
625 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
626 @samp{%rdx:%rax} (x86-64 only),
630 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
631 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
634 @cindex jump instructions, i386
635 @cindex call instructions, i386
636 @cindex jump instructions, x86-64
637 @cindex call instructions, x86-64
638 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
639 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
642 @subsection AT&T Mnemonic versus Intel Mnemonic
644 @cindex i386 mnemonic compatibility
645 @cindex mnemonic compatibility, i386
647 @code{@value{AS}} supports assembly using Intel mnemonic.
648 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
649 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
650 syntax for compatibility with the output of @code{@value{GCC}}.
651 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
652 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
653 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
654 assembler with different mnemonics from those in Intel IA32 specification.
655 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
658 @section Register Naming
660 @cindex i386 registers
661 @cindex registers, i386
662 @cindex x86-64 registers
663 @cindex registers, x86-64
664 Register operands are always prefixed with @samp{%}. The 80386 registers
669 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
670 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
671 frame pointer), and @samp{%esp} (the stack pointer).
674 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
675 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
678 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
679 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
680 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
681 @samp{%cx}, and @samp{%dx})
684 the 6 section registers @samp{%cs} (code section), @samp{%ds}
685 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
689 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
690 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
693 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
694 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
697 the 2 test registers @samp{%tr6} and @samp{%tr7}.
700 the 8 floating point register stack @samp{%st} or equivalently
701 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
702 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
703 These registers are overloaded by 8 MMX registers @samp{%mm0},
704 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
705 @samp{%mm6} and @samp{%mm7}.
708 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
709 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
712 The AMD x86-64 architecture extends the register set by:
716 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
717 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
718 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
722 the 8 extended registers @samp{%r8}--@samp{%r15}.
725 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
728 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
731 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
734 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
737 the 8 debug registers: @samp{%db8}--@samp{%db15}.
740 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
743 With the AVX extensions more registers were made available:
748 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
749 available in 32-bit mode). The bottom 128 bits are overlaid with the
750 @samp{xmm0}--@samp{xmm15} registers.
754 The AVX2 extensions made in 64-bit mode more registers available:
759 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
760 registers @samp{%ymm16}--@samp{%ymm31}.
764 The AVX512 extensions added the following registers:
769 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
770 available in 32-bit mode). The bottom 128 bits are overlaid with the
771 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
772 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
775 the 8 mask registers @samp{%k0}--@samp{%k7}.
780 @section Instruction Prefixes
782 @cindex i386 instruction prefixes
783 @cindex instruction prefixes, i386
784 @cindex prefixes, i386
785 Instruction prefixes are used to modify the following instruction. They
786 are used to repeat string instructions, to provide section overrides, to
787 perform bus lock operations, and to change operand and address sizes.
788 (Most instructions that normally operate on 32-bit operands will use
789 16-bit operands if the instruction has an ``operand size'' prefix.)
790 Instruction prefixes are best written on the same line as the instruction
791 they act upon. For example, the @samp{scas} (scan string) instruction is
795 repne scas %es:(%edi),%al
798 You may also place prefixes on the lines immediately preceding the
799 instruction, but this circumvents checks that @code{@value{AS}} does
800 with prefixes, and will not work with all prefixes.
802 Here is a list of instruction prefixes:
804 @cindex section override prefixes, i386
807 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
808 @samp{fs}, @samp{gs}. These are automatically added by specifying
809 using the @var{section}:@var{memory-operand} form for memory references.
811 @cindex size prefixes, i386
813 Operand/Address size prefixes @samp{data16} and @samp{addr16}
814 change 32-bit operands/addresses into 16-bit operands/addresses,
815 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
816 @code{.code16} section) into 32-bit operands/addresses. These prefixes
817 @emph{must} appear on the same line of code as the instruction they
818 modify. For example, in a 16-bit @code{.code16} section, you might
825 @cindex bus lock prefixes, i386
826 @cindex inhibiting interrupts, i386
828 The bus lock prefix @samp{lock} inhibits interrupts during execution of
829 the instruction it precedes. (This is only valid with certain
830 instructions; see a 80386 manual for details).
832 @cindex coprocessor wait, i386
834 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
835 complete the current instruction. This should never be needed for the
836 80386/80387 combination.
838 @cindex repeat prefixes, i386
840 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
841 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
842 times if the current address size is 16-bits).
843 @cindex REX prefixes, i386
845 The @samp{rex} family of prefixes is used by x86-64 to encode
846 extensions to i386 instruction set. The @samp{rex} prefix has four
847 bits --- an operand size overwrite (@code{64}) used to change operand size
848 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
851 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
852 instruction emits @samp{rex} prefix with all the bits set. By omitting
853 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
854 prefixes as well. Normally, there is no need to write the prefixes
855 explicitly, since gas will automatically generate them based on the
856 instruction operands.
860 @section Memory References
862 @cindex i386 memory references
863 @cindex memory references, i386
864 @cindex x86-64 memory references
865 @cindex memory references, x86-64
866 An Intel syntax indirect memory reference of the form
869 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
873 is translated into the AT&T syntax
876 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
880 where @var{base} and @var{index} are the optional 32-bit base and
881 index registers, @var{disp} is the optional displacement, and
882 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
883 to calculate the address of the operand. If no @var{scale} is
884 specified, @var{scale} is taken to be 1. @var{section} specifies the
885 optional section register for the memory operand, and may override the
886 default section register (see a 80386 manual for section register
887 defaults). Note that section overrides in AT&T syntax @emph{must}
888 be preceded by a @samp{%}. If you specify a section override which
889 coincides with the default section register, @code{@value{AS}} does @emph{not}
890 output any section register override prefixes to assemble the given
891 instruction. Thus, section overrides can be specified to emphasize which
892 section register is used for a given memory operand.
894 Here are some examples of Intel and AT&T style memory references:
897 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
898 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
899 missing, and the default section is used (@samp{%ss} for addressing with
900 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
902 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
903 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
904 @samp{foo}. All other fields are missing. The section register here
905 defaults to @samp{%ds}.
907 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
908 This uses the value pointed to by @samp{foo} as a memory operand.
909 Note that @var{base} and @var{index} are both missing, but there is only
910 @emph{one} @samp{,}. This is a syntactic exception.
912 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
913 This selects the contents of the variable @samp{foo} with section
914 register @var{section} being @samp{%gs}.
917 Absolute (as opposed to PC relative) call and jump operands must be
918 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
919 always chooses PC relative addressing for jump/call labels.
921 Any instruction that has a memory operand, but no register operand,
922 @emph{must} specify its size (byte, word, long, or quadruple) with an
923 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
926 The x86-64 architecture adds an RIP (instruction pointer relative)
927 addressing. This addressing mode is specified by using @samp{rip} as a
928 base register. Only constant offsets are valid. For example:
931 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
932 Points to the address 1234 bytes past the end of the current
935 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
936 Points to the @code{symbol} in RIP relative way, this is shorter than
937 the default absolute addressing.
940 Other addressing modes remain unchanged in x86-64 architecture, except
941 registers used are 64-bit instead of 32-bit.
944 @section Handling of Jump Instructions
946 @cindex jump optimization, i386
947 @cindex i386 jump optimization
948 @cindex jump optimization, x86-64
949 @cindex x86-64 jump optimization
950 Jump instructions are always optimized to use the smallest possible
951 displacements. This is accomplished by using byte (8-bit) displacement
952 jumps whenever the target is sufficiently close. If a byte displacement
953 is insufficient a long displacement is used. We do not support
954 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
955 instruction with the @samp{data16} instruction prefix), since the 80386
956 insists upon masking @samp{%eip} to 16 bits after the word displacement
957 is added. (See also @pxref{i386-Arch})
959 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
960 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
961 displacements, so that if you use these instructions (@code{@value{GCC}} does
962 not use them) you may get an error message (and incorrect code). The AT&T
963 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
974 @section Floating Point
976 @cindex i386 floating point
977 @cindex floating point, i386
978 @cindex x86-64 floating point
979 @cindex floating point, x86-64
980 All 80387 floating point types except packed BCD are supported.
981 (BCD support may be added without much difficulty). These data
982 types are 16-, 32-, and 64- bit integers, and single (32-bit),
983 double (64-bit), and extended (80-bit) precision floating point.
984 Each supported type has an instruction mnemonic suffix and a constructor
985 associated with it. Instruction mnemonic suffixes specify the operand's
986 data type. Constructors build these data types into memory.
988 @cindex @code{float} directive, i386
989 @cindex @code{single} directive, i386
990 @cindex @code{double} directive, i386
991 @cindex @code{tfloat} directive, i386
992 @cindex @code{float} directive, x86-64
993 @cindex @code{single} directive, x86-64
994 @cindex @code{double} directive, x86-64
995 @cindex @code{tfloat} directive, x86-64
998 Floating point constructors are @samp{.float} or @samp{.single},
999 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1000 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1001 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1002 only supports this format via the @samp{fldt} (load 80-bit real to stack
1003 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1005 @cindex @code{word} directive, i386
1006 @cindex @code{long} directive, i386
1007 @cindex @code{int} directive, i386
1008 @cindex @code{quad} directive, i386
1009 @cindex @code{word} directive, x86-64
1010 @cindex @code{long} directive, x86-64
1011 @cindex @code{int} directive, x86-64
1012 @cindex @code{quad} directive, x86-64
1014 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1015 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1016 corresponding instruction mnemonic suffixes are @samp{s} (single),
1017 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1018 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1019 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1020 stack) instructions.
1023 Register to register operations should not use instruction mnemonic suffixes.
1024 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1025 wrote @samp{fst %st, %st(1)}, since all register to register operations
1026 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1027 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1028 then stores the result in the 4 byte location @samp{mem})
1031 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1034 @cindex 3DNow!, i386
1037 @cindex 3DNow!, x86-64
1038 @cindex SIMD, x86-64
1040 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1041 instructions for integer data), available on Intel's Pentium MMX
1042 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1043 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1044 instruction set (SIMD instructions for 32-bit floating point data)
1045 available on AMD's K6-2 processor and possibly others in the future.
1047 Currently, @code{@value{AS}} does not support Intel's floating point
1050 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1051 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1052 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1053 floating point values. The MMX registers cannot be used at the same time
1054 as the floating point stack.
1056 See Intel and AMD documentation, keeping in mind that the operand order in
1057 instructions is reversed from the Intel syntax.
1060 @section AMD's Lightweight Profiling Instructions
1065 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1066 instruction set, available on AMD's Family 15h (Orochi) processors.
1068 LWP enables applications to collect and manage performance data, and
1069 react to performance events. The collection of performance data
1070 requires no context switches. LWP runs in the context of a thread and
1071 so several counters can be used independently across multiple threads.
1072 LWP can be used in both 64-bit and legacy 32-bit modes.
1074 For detailed information on the LWP instruction set, see the
1075 @cite{AMD Lightweight Profiling Specification} available at
1076 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1079 @section Bit Manipulation Instructions
1084 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1086 BMI instructions provide several instructions implementing individual
1087 bit manipulation operations such as isolation, masking, setting, or
1090 @c Need to add a specification citation here when available.
1093 @section AMD's Trailing Bit Manipulation Instructions
1098 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1099 instruction set, available on AMD's BDVER2 processors (Trinity and
1102 TBM instructions provide instructions implementing individual bit
1103 manipulation operations such as isolating, masking, setting, resetting,
1104 complementing, and operations on trailing zeros and ones.
1106 @c Need to add a specification citation here when available.
1109 @section Writing 16-bit Code
1111 @cindex i386 16-bit code
1112 @cindex 16-bit code, i386
1113 @cindex real-mode code, i386
1114 @cindex @code{code16gcc} directive, i386
1115 @cindex @code{code16} directive, i386
1116 @cindex @code{code32} directive, i386
1117 @cindex @code{code64} directive, i386
1118 @cindex @code{code64} directive, x86-64
1119 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1120 or 64-bit x86-64 code depending on the default configuration,
1121 it also supports writing code to run in real mode or in 16-bit protected
1122 mode code segments. To do this, put a @samp{.code16} or
1123 @samp{.code16gcc} directive before the assembly language instructions to
1124 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1125 32-bit code with the @samp{.code32} directive or 64-bit code with the
1126 @samp{.code64} directive.
1128 @samp{.code16gcc} provides experimental support for generating 16-bit
1129 code from gcc, and differs from @samp{.code16} in that @samp{call},
1130 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1131 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1132 default to 32-bit size. This is so that the stack pointer is
1133 manipulated in the same way over function calls, allowing access to
1134 function parameters at the same stack offsets as in 32-bit mode.
1135 @samp{.code16gcc} also automatically adds address size prefixes where
1136 necessary to use the 32-bit addressing modes that gcc generates.
1138 The code which @code{@value{AS}} generates in 16-bit mode will not
1139 necessarily run on a 16-bit pre-80386 processor. To write code that
1140 runs on such a processor, you must refrain from using @emph{any} 32-bit
1141 constructs which require @code{@value{AS}} to output address or operand
1144 Note that writing 16-bit code instructions by explicitly specifying a
1145 prefix or an instruction mnemonic suffix within a 32-bit code section
1146 generates different machine instructions than those generated for a
1147 16-bit code segment. In a 32-bit code section, the following code
1148 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1149 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1155 The same code in a 16-bit code section would generate the machine
1156 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1157 is correct since the processor default operand size is assumed to be 16
1158 bits in a 16-bit code section.
1161 @section Specifying CPU Architecture
1163 @cindex arch directive, i386
1164 @cindex i386 arch directive
1165 @cindex arch directive, x86-64
1166 @cindex x86-64 arch directive
1168 @code{@value{AS}} may be told to assemble for a particular CPU
1169 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1170 directive enables a warning when gas detects an instruction that is not
1171 supported on the CPU specified. The choices for @var{cpu_type} are:
1173 @multitable @columnfractions .20 .20 .20 .20
1174 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1175 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1176 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1177 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1178 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1179 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1180 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1181 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1182 @item @samp{generic32} @tab @samp{generic64}
1183 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1184 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1185 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1186 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1187 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1188 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1189 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1190 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1191 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1192 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1193 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1194 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1195 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.clwb}
1196 @item @samp{.rdpid} @tab @samp{.ptwrite}
1197 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1198 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1199 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1200 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1203 Apart from the warning, there are only two other effects on
1204 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1205 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1206 will automatically use a two byte opcode sequence. The larger three
1207 byte opcode sequence is used on the 486 (and when no architecture is
1208 specified) because it executes faster on the 486. Note that you can
1209 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1210 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1211 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1212 conditional jumps will be promoted when necessary to a two instruction
1213 sequence consisting of a conditional jump of the opposite sense around
1214 an unconditional jump to the target.
1216 Following the CPU architecture (but not a sub-architecture, which are those
1217 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1218 control automatic promotion of conditional jumps. @samp{jumps} is the
1219 default, and enables jump promotion; All external jumps will be of the long
1220 variety, and file-local jumps will be promoted as necessary.
1221 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1222 byte offset jumps, and warns about file-local conditional jumps that
1223 @code{@value{AS}} promotes.
1224 Unconditional jumps are treated as for @samp{jumps}.
1233 @section AT&T Syntax bugs
1235 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1236 assemblers, generate floating point instructions with reversed source
1237 and destination registers in certain cases. Unfortunately, gcc and
1238 possibly many other programs use this reversed syntax, so we're stuck
1247 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1248 than the expected @samp{%st(3) - %st}. This happens with all the
1249 non-commutative arithmetic floating point operations with two register
1250 operands where the source register is @samp{%st} and the destination
1251 register is @samp{%st(i)}.
1256 @cindex i386 @code{mul}, @code{imul} instructions
1257 @cindex @code{mul} instruction, i386
1258 @cindex @code{imul} instruction, i386
1259 @cindex @code{mul} instruction, x86-64
1260 @cindex @code{imul} instruction, x86-64
1261 There is some trickery concerning the @samp{mul} and @samp{imul}
1262 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1263 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1264 for @samp{imul}) can be output only in the one operand form. Thus,
1265 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1266 the expanding multiply would clobber the @samp{%edx} register, and this
1267 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1268 64-bit product in @samp{%edx:%eax}.
1270 We have added a two operand form of @samp{imul} when the first operand
1271 is an immediate mode expression and the second operand is a register.
1272 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1273 example, can be done with @samp{imul $69, %eax} rather than @samp{imul