1 @c Copyright 1991-2013 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
127 In addition to the basic instruction set, the assembler can be told to
128 accept various extension mnemonics. For example,
129 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
130 @var{vmx}. The following extensions are currently supported:
190 Note that rather than extending a basic instruction set, the extension
191 mnemonics starting with @code{no} revoke the respective functionality.
193 When the @code{.arch} directive is used with @option{-march}, the
194 @code{.arch} directive will take precedent.
196 @cindex @samp{-mtune=} option, i386
197 @cindex @samp{-mtune=} option, x86-64
198 @item -mtune=@var{CPU}
199 This option specifies a processor to optimize for. When used in
200 conjunction with the @option{-march} option, only instructions
201 of the processor specified by the @option{-march} option will be
204 Valid @var{CPU} values are identical to the processor list of
205 @option{-march=@var{CPU}}.
207 @cindex @samp{-msse2avx} option, i386
208 @cindex @samp{-msse2avx} option, x86-64
210 This option specifies that the assembler should encode SSE instructions
213 @cindex @samp{-msse-check=} option, i386
214 @cindex @samp{-msse-check=} option, x86-64
215 @item -msse-check=@var{none}
216 @itemx -msse-check=@var{warning}
217 @itemx -msse-check=@var{error}
218 These options control if the assembler should check SSE instructions.
219 @option{-msse-check=@var{none}} will make the assembler not to check SSE
220 instructions, which is the default. @option{-msse-check=@var{warning}}
221 will make the assembler issue a warning for any SSE instruction.
222 @option{-msse-check=@var{error}} will make the assembler issue an error
223 for any SSE instruction.
225 @cindex @samp{-mavxscalar=} option, i386
226 @cindex @samp{-mavxscalar=} option, x86-64
227 @item -mavxscalar=@var{128}
228 @itemx -mavxscalar=@var{256}
229 These options control how the assembler should encode scalar AVX
230 instructions. @option{-mavxscalar=@var{128}} will encode scalar
231 AVX instructions with 128bit vector length, which is the default.
232 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
233 with 256bit vector length.
235 @cindex @samp{-mevexlig=} option, i386
236 @cindex @samp{-mevexlig=} option, x86-64
237 @item -mevexlig=@var{128}
238 @itemx -mevexlig=@var{256}
239 @itemx -mevexlig=@var{512}
240 These options control how the assembler should encode length-ignored
241 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
242 EVEX instructions with 128bit vector length, which is the default.
243 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
244 encode LIG EVEX instructions with 256bit and 512bit vector length,
247 @cindex @samp{-mevexwig=} option, i386
248 @cindex @samp{-mevexwig=} option, x86-64
249 @item -mevexwig=@var{0}
250 @itemx -mevexwig=@var{1}
251 These options control how the assembler should encode w-ignored (WIG)
252 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
253 EVEX instructions with evex.w = 0, which is the default.
254 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
257 @cindex @samp{-mmnemonic=} option, i386
258 @cindex @samp{-mmnemonic=} option, x86-64
259 @item -mmnemonic=@var{att}
260 @itemx -mmnemonic=@var{intel}
261 This option specifies instruction mnemonic for matching instructions.
262 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
265 @cindex @samp{-msyntax=} option, i386
266 @cindex @samp{-msyntax=} option, x86-64
267 @item -msyntax=@var{att}
268 @itemx -msyntax=@var{intel}
269 This option specifies instruction syntax when processing instructions.
270 The @code{.att_syntax} and @code{.intel_syntax} directives will
273 @cindex @samp{-mnaked-reg} option, i386
274 @cindex @samp{-mnaked-reg} option, x86-64
276 This opetion specifies that registers don't require a @samp{%} prefix.
277 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
279 @cindex @samp{-madd-bnd-prefix} option, i386
280 @cindex @samp{-madd-bnd-prefix} option, x86-64
281 @item -madd-bnd-prefix
282 This option forces the assembler to add BND prefix to all branches, even
283 if such prefix was not explicitly specified in the source code.
288 @node i386-Directives
289 @section x86 specific Directives
291 @cindex machine directives, x86
292 @cindex x86 machine directives
295 @cindex @code{lcomm} directive, COFF
296 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
297 Reserve @var{length} (an absolute expression) bytes for a local common
298 denoted by @var{symbol}. The section and value of @var{symbol} are
299 those of the new local common. The addresses are allocated in the bss
300 section, so that at run-time the bytes start off zeroed. Since
301 @var{symbol} is not declared global, it is normally not visible to
302 @code{@value{LD}}. The optional third parameter, @var{alignment},
303 specifies the desired alignment of the symbol in the bss section.
305 This directive is only available for COFF based x86 targets.
307 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
313 @section i386 Syntactical Considerations
315 * i386-Variations:: AT&T Syntax versus Intel Syntax
316 * i386-Chars:: Special Characters
319 @node i386-Variations
320 @subsection AT&T Syntax versus Intel Syntax
322 @cindex i386 intel_syntax pseudo op
323 @cindex intel_syntax pseudo op, i386
324 @cindex i386 att_syntax pseudo op
325 @cindex att_syntax pseudo op, i386
326 @cindex i386 syntax compatibility
327 @cindex syntax compatibility, i386
328 @cindex x86-64 intel_syntax pseudo op
329 @cindex intel_syntax pseudo op, x86-64
330 @cindex x86-64 att_syntax pseudo op
331 @cindex att_syntax pseudo op, x86-64
332 @cindex x86-64 syntax compatibility
333 @cindex syntax compatibility, x86-64
335 @code{@value{AS}} now supports assembly using Intel assembler syntax.
336 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
337 back to the usual AT&T mode for compatibility with the output of
338 @code{@value{GCC}}. Either of these directives may have an optional
339 argument, @code{prefix}, or @code{noprefix} specifying whether registers
340 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
341 different from Intel syntax. We mention these differences because
342 almost all 80386 documents use Intel syntax. Notable differences
343 between the two syntaxes are:
345 @cindex immediate operands, i386
346 @cindex i386 immediate operands
347 @cindex register operands, i386
348 @cindex i386 register operands
349 @cindex jump/call operands, i386
350 @cindex i386 jump/call operands
351 @cindex operand delimiters, i386
353 @cindex immediate operands, x86-64
354 @cindex x86-64 immediate operands
355 @cindex register operands, x86-64
356 @cindex x86-64 register operands
357 @cindex jump/call operands, x86-64
358 @cindex x86-64 jump/call operands
359 @cindex operand delimiters, x86-64
362 AT&T immediate operands are preceded by @samp{$}; Intel immediate
363 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
364 AT&T register operands are preceded by @samp{%}; Intel register operands
365 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
366 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
368 @cindex i386 source, destination operands
369 @cindex source, destination operands; i386
370 @cindex x86-64 source, destination operands
371 @cindex source, destination operands; x86-64
373 AT&T and Intel syntax use the opposite order for source and destination
374 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
375 @samp{source, dest} convention is maintained for compatibility with
376 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
377 instructions with 2 immediate operands, such as the @samp{enter}
378 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
380 @cindex mnemonic suffixes, i386
381 @cindex sizes operands, i386
382 @cindex i386 size suffixes
383 @cindex mnemonic suffixes, x86-64
384 @cindex sizes operands, x86-64
385 @cindex x86-64 size suffixes
387 In AT&T syntax the size of memory operands is determined from the last
388 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
389 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
390 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
391 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
392 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
393 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
396 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
397 instruction with the 64-bit displacement or immediate operand.
399 @cindex return instructions, i386
400 @cindex i386 jump, call, return
401 @cindex return instructions, x86-64
402 @cindex x86-64 jump, call, return
404 Immediate form long jumps and calls are
405 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
407 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
409 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
410 @samp{ret far @var{stack-adjust}}.
412 @cindex sections, i386
413 @cindex i386 sections
414 @cindex sections, x86-64
415 @cindex x86-64 sections
417 The AT&T assembler does not provide support for multiple section
418 programs. Unix style systems expect all programs to be single sections.
422 @subsection Special Characters
424 @cindex line comment character, i386
425 @cindex i386 line comment character
426 The presence of a @samp{#} appearing anywhere on a line indicates the
427 start of a comment that extends to the end of that line.
429 If a @samp{#} appears as the first character of a line then the whole
430 line is treated as a comment, but in this case the line can also be a
431 logical line number directive (@pxref{Comments}) or a preprocessor
432 control command (@pxref{Preprocessing}).
434 If the @option{--divide} command line option has not been specified
435 then the @samp{/} character appearing anywhere on a line also
436 introduces a line comment.
438 @cindex line separator, i386
439 @cindex statement separator, i386
440 @cindex i386 line separator
441 The @samp{;} character can be used to separate statements on the same
445 @section Instruction Naming
447 @cindex i386 instruction naming
448 @cindex instruction naming, i386
449 @cindex x86-64 instruction naming
450 @cindex instruction naming, x86-64
452 Instruction mnemonics are suffixed with one character modifiers which
453 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
454 and @samp{q} specify byte, word, long and quadruple word operands. If
455 no suffix is specified by an instruction then @code{@value{AS}} tries to
456 fill in the missing suffix based on the destination register operand
457 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
458 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
459 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
460 assembler which assumes that a missing mnemonic suffix implies long
461 operand size. (This incompatibility does not affect compiler output
462 since compilers always explicitly specify the mnemonic suffix.)
464 Almost all instructions have the same names in AT&T and Intel format.
465 There are a few exceptions. The sign extend and zero extend
466 instructions need two sizes to specify them. They need a size to
467 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
468 is accomplished by using two instruction mnemonic suffixes in AT&T
469 syntax. Base names for sign extend and zero extend are
470 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
471 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
472 are tacked on to this base name, the @emph{from} suffix before the
473 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
474 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
475 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
476 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
477 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
480 @cindex encoding options, i386
481 @cindex encoding options, x86-64
483 Different encoding options can be specified via optional mnemonic
484 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
485 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
486 prefers 8bit or 32bit displacement in encoding.
488 @cindex conversion instructions, i386
489 @cindex i386 conversion instructions
490 @cindex conversion instructions, x86-64
491 @cindex x86-64 conversion instructions
492 The Intel-syntax conversion instructions
496 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
499 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
502 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
505 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
508 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
512 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
513 @samp{%rdx:%rax} (x86-64 only),
517 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
518 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
521 @cindex jump instructions, i386
522 @cindex call instructions, i386
523 @cindex jump instructions, x86-64
524 @cindex call instructions, x86-64
525 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
526 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
529 @section AT&T Mnemonic versus Intel Mnemonic
531 @cindex i386 mnemonic compatibility
532 @cindex mnemonic compatibility, i386
534 @code{@value{AS}} supports assembly using Intel mnemonic.
535 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
536 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
537 syntax for compatibility with the output of @code{@value{GCC}}.
538 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
539 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
540 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
541 assembler with different mnemonics from those in Intel IA32 specification.
542 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
545 @section Register Naming
547 @cindex i386 registers
548 @cindex registers, i386
549 @cindex x86-64 registers
550 @cindex registers, x86-64
551 Register operands are always prefixed with @samp{%}. The 80386 registers
556 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
557 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
558 frame pointer), and @samp{%esp} (the stack pointer).
561 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
562 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
565 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
566 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
567 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
568 @samp{%cx}, and @samp{%dx})
571 the 6 section registers @samp{%cs} (code section), @samp{%ds}
572 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
576 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
580 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
581 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
584 the 2 test registers @samp{%tr6} and @samp{%tr7}.
587 the 8 floating point register stack @samp{%st} or equivalently
588 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
589 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
590 These registers are overloaded by 8 MMX registers @samp{%mm0},
591 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
592 @samp{%mm6} and @samp{%mm7}.
595 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
596 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
599 The AMD x86-64 architecture extends the register set by:
603 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
604 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
605 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
609 the 8 extended registers @samp{%r8}--@samp{%r15}.
612 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
615 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
618 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
621 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
624 the 8 debug registers: @samp{%db8}--@samp{%db15}.
627 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
631 @section Instruction Prefixes
633 @cindex i386 instruction prefixes
634 @cindex instruction prefixes, i386
635 @cindex prefixes, i386
636 Instruction prefixes are used to modify the following instruction. They
637 are used to repeat string instructions, to provide section overrides, to
638 perform bus lock operations, and to change operand and address sizes.
639 (Most instructions that normally operate on 32-bit operands will use
640 16-bit operands if the instruction has an ``operand size'' prefix.)
641 Instruction prefixes are best written on the same line as the instruction
642 they act upon. For example, the @samp{scas} (scan string) instruction is
646 repne scas %es:(%edi),%al
649 You may also place prefixes on the lines immediately preceding the
650 instruction, but this circumvents checks that @code{@value{AS}} does
651 with prefixes, and will not work with all prefixes.
653 Here is a list of instruction prefixes:
655 @cindex section override prefixes, i386
658 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
659 @samp{fs}, @samp{gs}. These are automatically added by specifying
660 using the @var{section}:@var{memory-operand} form for memory references.
662 @cindex size prefixes, i386
664 Operand/Address size prefixes @samp{data16} and @samp{addr16}
665 change 32-bit operands/addresses into 16-bit operands/addresses,
666 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
667 @code{.code16} section) into 32-bit operands/addresses. These prefixes
668 @emph{must} appear on the same line of code as the instruction they
669 modify. For example, in a 16-bit @code{.code16} section, you might
676 @cindex bus lock prefixes, i386
677 @cindex inhibiting interrupts, i386
679 The bus lock prefix @samp{lock} inhibits interrupts during execution of
680 the instruction it precedes. (This is only valid with certain
681 instructions; see a 80386 manual for details).
683 @cindex coprocessor wait, i386
685 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
686 complete the current instruction. This should never be needed for the
687 80386/80387 combination.
689 @cindex repeat prefixes, i386
691 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
692 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
693 times if the current address size is 16-bits).
694 @cindex REX prefixes, i386
696 The @samp{rex} family of prefixes is used by x86-64 to encode
697 extensions to i386 instruction set. The @samp{rex} prefix has four
698 bits --- an operand size overwrite (@code{64}) used to change operand size
699 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
702 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
703 instruction emits @samp{rex} prefix with all the bits set. By omitting
704 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
705 prefixes as well. Normally, there is no need to write the prefixes
706 explicitly, since gas will automatically generate them based on the
707 instruction operands.
711 @section Memory References
713 @cindex i386 memory references
714 @cindex memory references, i386
715 @cindex x86-64 memory references
716 @cindex memory references, x86-64
717 An Intel syntax indirect memory reference of the form
720 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
724 is translated into the AT&T syntax
727 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
731 where @var{base} and @var{index} are the optional 32-bit base and
732 index registers, @var{disp} is the optional displacement, and
733 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
734 to calculate the address of the operand. If no @var{scale} is
735 specified, @var{scale} is taken to be 1. @var{section} specifies the
736 optional section register for the memory operand, and may override the
737 default section register (see a 80386 manual for section register
738 defaults). Note that section overrides in AT&T syntax @emph{must}
739 be preceded by a @samp{%}. If you specify a section override which
740 coincides with the default section register, @code{@value{AS}} does @emph{not}
741 output any section register override prefixes to assemble the given
742 instruction. Thus, section overrides can be specified to emphasize which
743 section register is used for a given memory operand.
745 Here are some examples of Intel and AT&T style memory references:
748 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
749 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
750 missing, and the default section is used (@samp{%ss} for addressing with
751 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
753 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
754 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
755 @samp{foo}. All other fields are missing. The section register here
756 defaults to @samp{%ds}.
758 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
759 This uses the value pointed to by @samp{foo} as a memory operand.
760 Note that @var{base} and @var{index} are both missing, but there is only
761 @emph{one} @samp{,}. This is a syntactic exception.
763 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
764 This selects the contents of the variable @samp{foo} with section
765 register @var{section} being @samp{%gs}.
768 Absolute (as opposed to PC relative) call and jump operands must be
769 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
770 always chooses PC relative addressing for jump/call labels.
772 Any instruction that has a memory operand, but no register operand,
773 @emph{must} specify its size (byte, word, long, or quadruple) with an
774 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
777 The x86-64 architecture adds an RIP (instruction pointer relative)
778 addressing. This addressing mode is specified by using @samp{rip} as a
779 base register. Only constant offsets are valid. For example:
782 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
783 Points to the address 1234 bytes past the end of the current
786 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
787 Points to the @code{symbol} in RIP relative way, this is shorter than
788 the default absolute addressing.
791 Other addressing modes remain unchanged in x86-64 architecture, except
792 registers used are 64-bit instead of 32-bit.
795 @section Handling of Jump Instructions
797 @cindex jump optimization, i386
798 @cindex i386 jump optimization
799 @cindex jump optimization, x86-64
800 @cindex x86-64 jump optimization
801 Jump instructions are always optimized to use the smallest possible
802 displacements. This is accomplished by using byte (8-bit) displacement
803 jumps whenever the target is sufficiently close. If a byte displacement
804 is insufficient a long displacement is used. We do not support
805 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
806 instruction with the @samp{data16} instruction prefix), since the 80386
807 insists upon masking @samp{%eip} to 16 bits after the word displacement
808 is added. (See also @pxref{i386-Arch})
810 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
811 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
812 displacements, so that if you use these instructions (@code{@value{GCC}} does
813 not use them) you may get an error message (and incorrect code). The AT&T
814 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
825 @section Floating Point
827 @cindex i386 floating point
828 @cindex floating point, i386
829 @cindex x86-64 floating point
830 @cindex floating point, x86-64
831 All 80387 floating point types except packed BCD are supported.
832 (BCD support may be added without much difficulty). These data
833 types are 16-, 32-, and 64- bit integers, and single (32-bit),
834 double (64-bit), and extended (80-bit) precision floating point.
835 Each supported type has an instruction mnemonic suffix and a constructor
836 associated with it. Instruction mnemonic suffixes specify the operand's
837 data type. Constructors build these data types into memory.
839 @cindex @code{float} directive, i386
840 @cindex @code{single} directive, i386
841 @cindex @code{double} directive, i386
842 @cindex @code{tfloat} directive, i386
843 @cindex @code{float} directive, x86-64
844 @cindex @code{single} directive, x86-64
845 @cindex @code{double} directive, x86-64
846 @cindex @code{tfloat} directive, x86-64
849 Floating point constructors are @samp{.float} or @samp{.single},
850 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
851 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
852 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
853 only supports this format via the @samp{fldt} (load 80-bit real to stack
854 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
856 @cindex @code{word} directive, i386
857 @cindex @code{long} directive, i386
858 @cindex @code{int} directive, i386
859 @cindex @code{quad} directive, i386
860 @cindex @code{word} directive, x86-64
861 @cindex @code{long} directive, x86-64
862 @cindex @code{int} directive, x86-64
863 @cindex @code{quad} directive, x86-64
865 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
866 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
867 corresponding instruction mnemonic suffixes are @samp{s} (single),
868 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
869 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
870 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
874 Register to register operations should not use instruction mnemonic suffixes.
875 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
876 wrote @samp{fst %st, %st(1)}, since all register to register operations
877 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
878 which converts @samp{%st} from 80-bit to 64-bit floating point format,
879 then stores the result in the 4 byte location @samp{mem})
882 @section Intel's MMX and AMD's 3DNow! SIMD Operations
888 @cindex 3DNow!, x86-64
891 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
892 instructions for integer data), available on Intel's Pentium MMX
893 processors and Pentium II processors, AMD's K6 and K6-2 processors,
894 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
895 instruction set (SIMD instructions for 32-bit floating point data)
896 available on AMD's K6-2 processor and possibly others in the future.
898 Currently, @code{@value{AS}} does not support Intel's floating point
901 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
902 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
903 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
904 floating point values. The MMX registers cannot be used at the same time
905 as the floating point stack.
907 See Intel and AMD documentation, keeping in mind that the operand order in
908 instructions is reversed from the Intel syntax.
911 @section AMD's Lightweight Profiling Instructions
916 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
917 instruction set, available on AMD's Family 15h (Orochi) processors.
919 LWP enables applications to collect and manage performance data, and
920 react to performance events. The collection of performance data
921 requires no context switches. LWP runs in the context of a thread and
922 so several counters can be used independently across multiple threads.
923 LWP can be used in both 64-bit and legacy 32-bit modes.
925 For detailed information on the LWP instruction set, see the
926 @cite{AMD Lightweight Profiling Specification} available at
927 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
930 @section Bit Manipulation Instructions
935 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
937 BMI instructions provide several instructions implementing individual
938 bit manipulation operations such as isolation, masking, setting, or
941 @c Need to add a specification citation here when available.
944 @section AMD's Trailing Bit Manipulation Instructions
949 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
950 instruction set, available on AMD's BDVER2 processors (Trinity and
953 TBM instructions provide instructions implementing individual bit
954 manipulation operations such as isolating, masking, setting, resetting,
955 complementing, and operations on trailing zeros and ones.
957 @c Need to add a specification citation here when available.
960 @section Writing 16-bit Code
962 @cindex i386 16-bit code
963 @cindex 16-bit code, i386
964 @cindex real-mode code, i386
965 @cindex @code{code16gcc} directive, i386
966 @cindex @code{code16} directive, i386
967 @cindex @code{code32} directive, i386
968 @cindex @code{code64} directive, i386
969 @cindex @code{code64} directive, x86-64
970 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
971 or 64-bit x86-64 code depending on the default configuration,
972 it also supports writing code to run in real mode or in 16-bit protected
973 mode code segments. To do this, put a @samp{.code16} or
974 @samp{.code16gcc} directive before the assembly language instructions to
975 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
976 32-bit code with the @samp{.code32} directive or 64-bit code with the
977 @samp{.code64} directive.
979 @samp{.code16gcc} provides experimental support for generating 16-bit
980 code from gcc, and differs from @samp{.code16} in that @samp{call},
981 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
982 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
983 default to 32-bit size. This is so that the stack pointer is
984 manipulated in the same way over function calls, allowing access to
985 function parameters at the same stack offsets as in 32-bit mode.
986 @samp{.code16gcc} also automatically adds address size prefixes where
987 necessary to use the 32-bit addressing modes that gcc generates.
989 The code which @code{@value{AS}} generates in 16-bit mode will not
990 necessarily run on a 16-bit pre-80386 processor. To write code that
991 runs on such a processor, you must refrain from using @emph{any} 32-bit
992 constructs which require @code{@value{AS}} to output address or operand
995 Note that writing 16-bit code instructions by explicitly specifying a
996 prefix or an instruction mnemonic suffix within a 32-bit code section
997 generates different machine instructions than those generated for a
998 16-bit code segment. In a 32-bit code section, the following code
999 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1000 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1006 The same code in a 16-bit code section would generate the machine
1007 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1008 is correct since the processor default operand size is assumed to be 16
1009 bits in a 16-bit code section.
1012 @section AT&T Syntax bugs
1014 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1015 assemblers, generate floating point instructions with reversed source
1016 and destination registers in certain cases. Unfortunately, gcc and
1017 possibly many other programs use this reversed syntax, so we're stuck
1026 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1027 than the expected @samp{%st(3) - %st}. This happens with all the
1028 non-commutative arithmetic floating point operations with two register
1029 operands where the source register is @samp{%st} and the destination
1030 register is @samp{%st(i)}.
1033 @section Specifying CPU Architecture
1035 @cindex arch directive, i386
1036 @cindex i386 arch directive
1037 @cindex arch directive, x86-64
1038 @cindex x86-64 arch directive
1040 @code{@value{AS}} may be told to assemble for a particular CPU
1041 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1042 directive enables a warning when gas detects an instruction that is not
1043 supported on the CPU specified. The choices for @var{cpu_type} are:
1045 @multitable @columnfractions .20 .20 .20 .20
1046 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1047 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1048 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1049 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1050 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1051 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1052 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1053 @item @samp{btver1} @tab @samp{btver2}
1054 @item @samp{generic32} @tab @samp{generic64}
1055 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1056 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1057 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1058 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1059 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1060 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1061 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1062 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1063 @item @samp{.smap} @tab @samp{.mpx}
1064 @item @samp{.smap} @tab @samp{.sha}
1065 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1066 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1067 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1068 @item @samp{.padlock}
1069 @item @samp{.smap} @tab @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er}
1070 @item @samp{.avx512pf} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a}
1071 @item @samp{.sse5} @tab @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1072 @item @samp{.abm} @tab @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
1073 @item @samp{.cx16} @tab @samp{.padlock}
1076 Apart from the warning, there are only two other effects on
1077 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1078 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1079 will automatically use a two byte opcode sequence. The larger three
1080 byte opcode sequence is used on the 486 (and when no architecture is
1081 specified) because it executes faster on the 486. Note that you can
1082 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1083 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1084 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1085 conditional jumps will be promoted when necessary to a two instruction
1086 sequence consisting of a conditional jump of the opposite sense around
1087 an unconditional jump to the target.
1089 Following the CPU architecture (but not a sub-architecture, which are those
1090 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1091 control automatic promotion of conditional jumps. @samp{jumps} is the
1092 default, and enables jump promotion; All external jumps will be of the long
1093 variety, and file-local jumps will be promoted as necessary.
1094 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1095 byte offset jumps, and warns about file-local conditional jumps that
1096 @code{@value{AS}} promotes.
1097 Unconditional jumps are treated as for @samp{jumps}.
1108 @cindex i386 @code{mul}, @code{imul} instructions
1109 @cindex @code{mul} instruction, i386
1110 @cindex @code{imul} instruction, i386
1111 @cindex @code{mul} instruction, x86-64
1112 @cindex @code{imul} instruction, x86-64
1113 There is some trickery concerning the @samp{mul} and @samp{imul}
1114 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1115 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1116 for @samp{imul}) can be output only in the one operand form. Thus,
1117 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1118 the expanding multiply would clobber the @samp{%edx} register, and this
1119 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1120 64-bit product in @samp{%edx:%eax}.
1122 We have added a two operand form of @samp{imul} when the first operand
1123 is an immediate mode expression and the second operand is a register.
1124 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1125 example, can be done with @samp{imul $69, %eax} rather than @samp{imul