1 @c Copyright (C) 1991-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78 byte nop (0x90) is explicitly specified as the fill byte for alignment.
80 @cindex @samp{--divide} option, i386
82 On SVR4-derived platforms, the character @samp{/} is treated as a comment
83 character, which means that it cannot be used in expressions. The
84 @samp{--divide} option turns @samp{/} into a normal character. This does
85 not disable @samp{/} at the beginning of a line starting a comment, or
86 affect using @samp{#} for starting a comment.
88 @cindex @samp{-march=} option, i386
89 @cindex @samp{-march=} option, x86-64
90 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91 This option specifies the target processor. The assembler will
92 issue an error message if an attempt is made to assemble an instruction
93 which will not execute on the target processor. The following
94 processor names are recognized:
132 In addition to the basic instruction set, the assembler can be told to
133 accept various extension mnemonics. For example,
134 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
135 @var{vmx}. The following extensions are currently supported:
196 @code{avx512_4fmaps},
197 @code{avx512_4vnniw},
198 @code{avx512_vpopcntdq},
201 @code{avx512_bitalg},
212 @code{noavx512_4fmaps},
213 @code{noavx512_4vnniw},
214 @code{noavx512_vpopcntdq},
215 @code{noavx512_vbmi2},
216 @code{noavx512_vnni},
217 @code{noavx512_bitalg},
218 @code{noavx512_vp2intersect},
219 @code{noavx512_bf16},
261 Note that rather than extending a basic instruction set, the extension
262 mnemonics starting with @code{no} revoke the respective functionality.
264 When the @code{.arch} directive is used with @option{-march}, the
265 @code{.arch} directive will take precedent.
267 @cindex @samp{-mtune=} option, i386
268 @cindex @samp{-mtune=} option, x86-64
269 @item -mtune=@var{CPU}
270 This option specifies a processor to optimize for. When used in
271 conjunction with the @option{-march} option, only instructions
272 of the processor specified by the @option{-march} option will be
275 Valid @var{CPU} values are identical to the processor list of
276 @option{-march=@var{CPU}}.
278 @cindex @samp{-msse2avx} option, i386
279 @cindex @samp{-msse2avx} option, x86-64
281 This option specifies that the assembler should encode SSE instructions
284 @cindex @samp{-msse-check=} option, i386
285 @cindex @samp{-msse-check=} option, x86-64
286 @item -msse-check=@var{none}
287 @itemx -msse-check=@var{warning}
288 @itemx -msse-check=@var{error}
289 These options control if the assembler should check SSE instructions.
290 @option{-msse-check=@var{none}} will make the assembler not to check SSE
291 instructions, which is the default. @option{-msse-check=@var{warning}}
292 will make the assembler issue a warning for any SSE instruction.
293 @option{-msse-check=@var{error}} will make the assembler issue an error
294 for any SSE instruction.
296 @cindex @samp{-mavxscalar=} option, i386
297 @cindex @samp{-mavxscalar=} option, x86-64
298 @item -mavxscalar=@var{128}
299 @itemx -mavxscalar=@var{256}
300 These options control how the assembler should encode scalar AVX
301 instructions. @option{-mavxscalar=@var{128}} will encode scalar
302 AVX instructions with 128bit vector length, which is the default.
303 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
304 with 256bit vector length.
306 WARNING: Don't use this for production code - due to CPU errata the
307 resulting code may not work on certain models.
309 @cindex @samp{-mvexwig=} option, i386
310 @cindex @samp{-mvexwig=} option, x86-64
311 @item -mvexwig=@var{0}
312 @itemx -mvexwig=@var{1}
313 These options control how the assembler should encode VEX.W-ignored (WIG)
314 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
315 instructions with vex.w = 0, which is the default.
316 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
319 WARNING: Don't use this for production code - due to CPU errata the
320 resulting code may not work on certain models.
322 @cindex @samp{-mevexlig=} option, i386
323 @cindex @samp{-mevexlig=} option, x86-64
324 @item -mevexlig=@var{128}
325 @itemx -mevexlig=@var{256}
326 @itemx -mevexlig=@var{512}
327 These options control how the assembler should encode length-ignored
328 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
329 EVEX instructions with 128bit vector length, which is the default.
330 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
331 encode LIG EVEX instructions with 256bit and 512bit vector length,
334 @cindex @samp{-mevexwig=} option, i386
335 @cindex @samp{-mevexwig=} option, x86-64
336 @item -mevexwig=@var{0}
337 @itemx -mevexwig=@var{1}
338 These options control how the assembler should encode w-ignored (WIG)
339 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
340 EVEX instructions with evex.w = 0, which is the default.
341 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
344 @cindex @samp{-mmnemonic=} option, i386
345 @cindex @samp{-mmnemonic=} option, x86-64
346 @item -mmnemonic=@var{att}
347 @itemx -mmnemonic=@var{intel}
348 This option specifies instruction mnemonic for matching instructions.
349 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
352 @cindex @samp{-msyntax=} option, i386
353 @cindex @samp{-msyntax=} option, x86-64
354 @item -msyntax=@var{att}
355 @itemx -msyntax=@var{intel}
356 This option specifies instruction syntax when processing instructions.
357 The @code{.att_syntax} and @code{.intel_syntax} directives will
360 @cindex @samp{-mnaked-reg} option, i386
361 @cindex @samp{-mnaked-reg} option, x86-64
363 This option specifies that registers don't require a @samp{%} prefix.
364 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
366 @cindex @samp{-madd-bnd-prefix} option, i386
367 @cindex @samp{-madd-bnd-prefix} option, x86-64
368 @item -madd-bnd-prefix
369 This option forces the assembler to add BND prefix to all branches, even
370 if such prefix was not explicitly specified in the source code.
372 @cindex @samp{-mshared} option, i386
373 @cindex @samp{-mshared} option, x86-64
375 On ELF target, the assembler normally optimizes out non-PLT relocations
376 against defined non-weak global branch targets with default visibility.
377 The @samp{-mshared} option tells the assembler to generate code which
378 may go into a shared library where all non-weak global branch targets
379 with default visibility can be preempted. The resulting code is
380 slightly bigger. This option only affects the handling of branch
383 @cindex @samp{-mbig-obj} option, x86-64
385 On x86-64 PE/COFF target this option forces the use of big object file
386 format, which allows more than 32768 sections.
388 @cindex @samp{-momit-lock-prefix=} option, i386
389 @cindex @samp{-momit-lock-prefix=} option, x86-64
390 @item -momit-lock-prefix=@var{no}
391 @itemx -momit-lock-prefix=@var{yes}
392 These options control how the assembler should encode lock prefix.
393 This option is intended as a workaround for processors, that fail on
394 lock prefix. This option can only be safely used with single-core,
395 single-thread computers
396 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
397 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
398 which is the default.
400 @cindex @samp{-mfence-as-lock-add=} option, i386
401 @cindex @samp{-mfence-as-lock-add=} option, x86-64
402 @item -mfence-as-lock-add=@var{no}
403 @itemx -mfence-as-lock-add=@var{yes}
404 These options control how the assembler should encode lfence, mfence and
406 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
407 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
408 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
409 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
410 sfence as usual, which is the default.
412 @cindex @samp{-mrelax-relocations=} option, i386
413 @cindex @samp{-mrelax-relocations=} option, x86-64
414 @item -mrelax-relocations=@var{no}
415 @itemx -mrelax-relocations=@var{yes}
416 These options control whether the assembler should generate relax
417 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
418 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
419 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
420 @option{-mrelax-relocations=@var{no}} will not generate relax
421 relocations. The default can be controlled by a configure option
422 @option{--enable-x86-relax-relocations}.
424 @cindex @samp{-mx86-used-note=} option, i386
425 @cindex @samp{-mx86-used-note=} option, x86-64
426 @item -mx86-used-note=@var{no}
427 @itemx -mx86-used-note=@var{yes}
428 These options control whether the assembler should generate
429 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
430 GNU property notes. The default can be controlled by the
431 @option{--enable-x86-used-note} configure option.
433 @cindex @samp{-mevexrcig=} option, i386
434 @cindex @samp{-mevexrcig=} option, x86-64
435 @item -mevexrcig=@var{rne}
436 @itemx -mevexrcig=@var{rd}
437 @itemx -mevexrcig=@var{ru}
438 @itemx -mevexrcig=@var{rz}
439 These options control how the assembler should encode SAE-only
440 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
441 of EVEX instruction with 00, which is the default.
442 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
443 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
444 with 01, 10 and 11 RC bits, respectively.
446 @cindex @samp{-mamd64} option, x86-64
447 @cindex @samp{-mintel64} option, x86-64
450 This option specifies that the assembler should accept only AMD64 or
451 Intel64 ISA in 64-bit mode. The default is to accept both.
453 @cindex @samp{-O0} option, i386
454 @cindex @samp{-O0} option, x86-64
455 @cindex @samp{-O} option, i386
456 @cindex @samp{-O} option, x86-64
457 @cindex @samp{-O1} option, i386
458 @cindex @samp{-O1} option, x86-64
459 @cindex @samp{-O2} option, i386
460 @cindex @samp{-O2} option, x86-64
461 @cindex @samp{-Os} option, i386
462 @cindex @samp{-Os} option, x86-64
463 @item -O0 | -O | -O1 | -O2 | -Os
464 Optimize instruction encoding with smaller instruction size. @samp{-O}
465 and @samp{-O1} encode 64-bit register load instructions with 64-bit
466 immediate as 32-bit register load instructions with 31-bit or 32-bits
467 immediates, encode 64-bit register clearing instructions with 32-bit
468 register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
469 register clearing instructions with 128-bit VEX vector register
470 clearing instructions, encode 128-bit/256-bit EVEX vector
471 register load/store instructions with VEX vector register load/store
472 instructions, and encode 128-bit/256-bit EVEX packed integer logical
473 instructions with 128-bit/256-bit VEX packed integer logical.
475 @samp{-O2} includes @samp{-O1} optimization plus encodes
476 256-bit/512-bit EVEX vector register clearing instructions with 128-bit
477 EVEX vector register clearing instructions.
479 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
480 and 64-bit register tests with immediate as 8-bit register test with
481 immediate. @samp{-O0} turns off this optimization.
486 @node i386-Directives
487 @section x86 specific Directives
489 @cindex machine directives, x86
490 @cindex x86 machine directives
493 @cindex @code{lcomm} directive, COFF
494 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
495 Reserve @var{length} (an absolute expression) bytes for a local common
496 denoted by @var{symbol}. The section and value of @var{symbol} are
497 those of the new local common. The addresses are allocated in the bss
498 section, so that at run-time the bytes start off zeroed. Since
499 @var{symbol} is not declared global, it is normally not visible to
500 @code{@value{LD}}. The optional third parameter, @var{alignment},
501 specifies the desired alignment of the symbol in the bss section.
503 This directive is only available for COFF based x86 targets.
505 @cindex @code{largecomm} directive, ELF
506 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
507 This directive behaves in the same way as the @code{comm} directive
508 except that the data is placed into the @var{.lbss} section instead of
509 the @var{.bss} section @ref{Comm}.
511 The directive is intended to be used for data which requires a large
512 amount of space, and it is only available for ELF based x86_64
515 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
520 @section i386 Syntactical Considerations
522 * i386-Variations:: AT&T Syntax versus Intel Syntax
523 * i386-Chars:: Special Characters
526 @node i386-Variations
527 @subsection AT&T Syntax versus Intel Syntax
529 @cindex i386 intel_syntax pseudo op
530 @cindex intel_syntax pseudo op, i386
531 @cindex i386 att_syntax pseudo op
532 @cindex att_syntax pseudo op, i386
533 @cindex i386 syntax compatibility
534 @cindex syntax compatibility, i386
535 @cindex x86-64 intel_syntax pseudo op
536 @cindex intel_syntax pseudo op, x86-64
537 @cindex x86-64 att_syntax pseudo op
538 @cindex att_syntax pseudo op, x86-64
539 @cindex x86-64 syntax compatibility
540 @cindex syntax compatibility, x86-64
542 @code{@value{AS}} now supports assembly using Intel assembler syntax.
543 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
544 back to the usual AT&T mode for compatibility with the output of
545 @code{@value{GCC}}. Either of these directives may have an optional
546 argument, @code{prefix}, or @code{noprefix} specifying whether registers
547 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
548 different from Intel syntax. We mention these differences because
549 almost all 80386 documents use Intel syntax. Notable differences
550 between the two syntaxes are:
552 @cindex immediate operands, i386
553 @cindex i386 immediate operands
554 @cindex register operands, i386
555 @cindex i386 register operands
556 @cindex jump/call operands, i386
557 @cindex i386 jump/call operands
558 @cindex operand delimiters, i386
560 @cindex immediate operands, x86-64
561 @cindex x86-64 immediate operands
562 @cindex register operands, x86-64
563 @cindex x86-64 register operands
564 @cindex jump/call operands, x86-64
565 @cindex x86-64 jump/call operands
566 @cindex operand delimiters, x86-64
569 AT&T immediate operands are preceded by @samp{$}; Intel immediate
570 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
571 AT&T register operands are preceded by @samp{%}; Intel register operands
572 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
573 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
575 @cindex i386 source, destination operands
576 @cindex source, destination operands; i386
577 @cindex x86-64 source, destination operands
578 @cindex source, destination operands; x86-64
580 AT&T and Intel syntax use the opposite order for source and destination
581 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
582 @samp{source, dest} convention is maintained for compatibility with
583 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
584 instructions with 2 immediate operands, such as the @samp{enter}
585 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
587 @cindex mnemonic suffixes, i386
588 @cindex sizes operands, i386
589 @cindex i386 size suffixes
590 @cindex mnemonic suffixes, x86-64
591 @cindex sizes operands, x86-64
592 @cindex x86-64 size suffixes
594 In AT&T syntax the size of memory operands is determined from the last
595 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
596 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
597 (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
598 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
599 (256-bit vector) and zmm (512-bit vector) memory references, only when there's
600 no other way to disambiguate an instruction. Intel syntax accomplishes this by
601 prefixing memory operands (@emph{not} the instruction mnemonics) with
602 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
603 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
604 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
605 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
606 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
608 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
609 instruction with the 64-bit displacement or immediate operand.
611 @cindex return instructions, i386
612 @cindex i386 jump, call, return
613 @cindex return instructions, x86-64
614 @cindex x86-64 jump, call, return
616 Immediate form long jumps and calls are
617 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
619 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
621 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
622 @samp{ret far @var{stack-adjust}}.
624 @cindex sections, i386
625 @cindex i386 sections
626 @cindex sections, x86-64
627 @cindex x86-64 sections
629 The AT&T assembler does not provide support for multiple section
630 programs. Unix style systems expect all programs to be single sections.
634 @subsection Special Characters
636 @cindex line comment character, i386
637 @cindex i386 line comment character
638 The presence of a @samp{#} appearing anywhere on a line indicates the
639 start of a comment that extends to the end of that line.
641 If a @samp{#} appears as the first character of a line then the whole
642 line is treated as a comment, but in this case the line can also be a
643 logical line number directive (@pxref{Comments}) or a preprocessor
644 control command (@pxref{Preprocessing}).
646 If the @option{--divide} command-line option has not been specified
647 then the @samp{/} character appearing anywhere on a line also
648 introduces a line comment.
650 @cindex line separator, i386
651 @cindex statement separator, i386
652 @cindex i386 line separator
653 The @samp{;} character can be used to separate statements on the same
657 @section i386-Mnemonics
658 @subsection Instruction Naming
660 @cindex i386 instruction naming
661 @cindex instruction naming, i386
662 @cindex x86-64 instruction naming
663 @cindex instruction naming, x86-64
665 Instruction mnemonics are suffixed with one character modifiers which
666 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
667 and @samp{q} specify byte, word, long and quadruple word operands. If
668 no suffix is specified by an instruction then @code{@value{AS}} tries to
669 fill in the missing suffix based on the destination register operand
670 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
671 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
672 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
673 assembler which assumes that a missing mnemonic suffix implies long
674 operand size. (This incompatibility does not affect compiler output
675 since compilers always explicitly specify the mnemonic suffix.)
677 Almost all instructions have the same names in AT&T and Intel format.
678 There are a few exceptions. The sign extend and zero extend
679 instructions need two sizes to specify them. They need a size to
680 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
681 is accomplished by using two instruction mnemonic suffixes in AT&T
682 syntax. Base names for sign extend and zero extend are
683 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
684 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
685 are tacked on to this base name, the @emph{from} suffix before the
686 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
687 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
688 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
689 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
690 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
693 @cindex encoding options, i386
694 @cindex encoding options, x86-64
696 Different encoding options can be specified via pseudo prefixes:
700 @samp{@{disp8@}} -- prefer 8-bit displacement.
703 @samp{@{disp32@}} -- prefer 32-bit displacement.
706 @samp{@{load@}} -- prefer load-form instruction.
709 @samp{@{store@}} -- prefer store-form instruction.
712 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
715 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
718 @samp{@{evex@}} -- encode with EVEX prefix.
721 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
722 instructions (x86-64 only). Note that this differs from the @samp{rex}
723 prefix which generates REX prefix unconditionally.
726 @samp{@{nooptimize@}} -- disable instruction size optimization.
729 @cindex conversion instructions, i386
730 @cindex i386 conversion instructions
731 @cindex conversion instructions, x86-64
732 @cindex x86-64 conversion instructions
733 The Intel-syntax conversion instructions
737 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
740 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
743 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
746 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
749 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
753 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
754 @samp{%rdx:%rax} (x86-64 only),
758 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
759 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
762 @cindex jump instructions, i386
763 @cindex call instructions, i386
764 @cindex jump instructions, x86-64
765 @cindex call instructions, x86-64
766 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
767 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
770 @subsection AT&T Mnemonic versus Intel Mnemonic
772 @cindex i386 mnemonic compatibility
773 @cindex mnemonic compatibility, i386
775 @code{@value{AS}} supports assembly using Intel mnemonic.
776 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
777 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
778 syntax for compatibility with the output of @code{@value{GCC}}.
779 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
780 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
781 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
782 assembler with different mnemonics from those in Intel IA32 specification.
783 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
786 @section Register Naming
788 @cindex i386 registers
789 @cindex registers, i386
790 @cindex x86-64 registers
791 @cindex registers, x86-64
792 Register operands are always prefixed with @samp{%}. The 80386 registers
797 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
798 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
799 frame pointer), and @samp{%esp} (the stack pointer).
802 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
803 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
806 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
807 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
808 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
809 @samp{%cx}, and @samp{%dx})
812 the 6 section registers @samp{%cs} (code section), @samp{%ds}
813 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
817 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
818 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
821 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
822 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
825 the 2 test registers @samp{%tr6} and @samp{%tr7}.
828 the 8 floating point register stack @samp{%st} or equivalently
829 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
830 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
831 These registers are overloaded by 8 MMX registers @samp{%mm0},
832 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
833 @samp{%mm6} and @samp{%mm7}.
836 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
837 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
840 The AMD x86-64 architecture extends the register set by:
844 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
845 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
846 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
850 the 8 extended registers @samp{%r8}--@samp{%r15}.
853 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
856 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
859 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
862 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
865 the 8 debug registers: @samp{%db8}--@samp{%db15}.
868 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
871 With the AVX extensions more registers were made available:
876 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
877 available in 32-bit mode). The bottom 128 bits are overlaid with the
878 @samp{xmm0}--@samp{xmm15} registers.
882 The AVX2 extensions made in 64-bit mode more registers available:
887 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
888 registers @samp{%ymm16}--@samp{%ymm31}.
892 The AVX512 extensions added the following registers:
897 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
898 available in 32-bit mode). The bottom 128 bits are overlaid with the
899 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
900 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
903 the 8 mask registers @samp{%k0}--@samp{%k7}.
908 @section Instruction Prefixes
910 @cindex i386 instruction prefixes
911 @cindex instruction prefixes, i386
912 @cindex prefixes, i386
913 Instruction prefixes are used to modify the following instruction. They
914 are used to repeat string instructions, to provide section overrides, to
915 perform bus lock operations, and to change operand and address sizes.
916 (Most instructions that normally operate on 32-bit operands will use
917 16-bit operands if the instruction has an ``operand size'' prefix.)
918 Instruction prefixes are best written on the same line as the instruction
919 they act upon. For example, the @samp{scas} (scan string) instruction is
923 repne scas %es:(%edi),%al
926 You may also place prefixes on the lines immediately preceding the
927 instruction, but this circumvents checks that @code{@value{AS}} does
928 with prefixes, and will not work with all prefixes.
930 Here is a list of instruction prefixes:
932 @cindex section override prefixes, i386
935 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
936 @samp{fs}, @samp{gs}. These are automatically added by specifying
937 using the @var{section}:@var{memory-operand} form for memory references.
939 @cindex size prefixes, i386
941 Operand/Address size prefixes @samp{data16} and @samp{addr16}
942 change 32-bit operands/addresses into 16-bit operands/addresses,
943 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
944 @code{.code16} section) into 32-bit operands/addresses. These prefixes
945 @emph{must} appear on the same line of code as the instruction they
946 modify. For example, in a 16-bit @code{.code16} section, you might
953 @cindex bus lock prefixes, i386
954 @cindex inhibiting interrupts, i386
956 The bus lock prefix @samp{lock} inhibits interrupts during execution of
957 the instruction it precedes. (This is only valid with certain
958 instructions; see a 80386 manual for details).
960 @cindex coprocessor wait, i386
962 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
963 complete the current instruction. This should never be needed for the
964 80386/80387 combination.
966 @cindex repeat prefixes, i386
968 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
969 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
970 times if the current address size is 16-bits).
971 @cindex REX prefixes, i386
973 The @samp{rex} family of prefixes is used by x86-64 to encode
974 extensions to i386 instruction set. The @samp{rex} prefix has four
975 bits --- an operand size overwrite (@code{64}) used to change operand size
976 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
979 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
980 instruction emits @samp{rex} prefix with all the bits set. By omitting
981 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
982 prefixes as well. Normally, there is no need to write the prefixes
983 explicitly, since gas will automatically generate them based on the
984 instruction operands.
988 @section Memory References
990 @cindex i386 memory references
991 @cindex memory references, i386
992 @cindex x86-64 memory references
993 @cindex memory references, x86-64
994 An Intel syntax indirect memory reference of the form
997 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
1001 is translated into the AT&T syntax
1004 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
1008 where @var{base} and @var{index} are the optional 32-bit base and
1009 index registers, @var{disp} is the optional displacement, and
1010 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
1011 to calculate the address of the operand. If no @var{scale} is
1012 specified, @var{scale} is taken to be 1. @var{section} specifies the
1013 optional section register for the memory operand, and may override the
1014 default section register (see a 80386 manual for section register
1015 defaults). Note that section overrides in AT&T syntax @emph{must}
1016 be preceded by a @samp{%}. If you specify a section override which
1017 coincides with the default section register, @code{@value{AS}} does @emph{not}
1018 output any section register override prefixes to assemble the given
1019 instruction. Thus, section overrides can be specified to emphasize which
1020 section register is used for a given memory operand.
1022 Here are some examples of Intel and AT&T style memory references:
1025 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1026 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1027 missing, and the default section is used (@samp{%ss} for addressing with
1028 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1030 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1031 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1032 @samp{foo}. All other fields are missing. The section register here
1033 defaults to @samp{%ds}.
1035 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1036 This uses the value pointed to by @samp{foo} as a memory operand.
1037 Note that @var{base} and @var{index} are both missing, but there is only
1038 @emph{one} @samp{,}. This is a syntactic exception.
1040 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1041 This selects the contents of the variable @samp{foo} with section
1042 register @var{section} being @samp{%gs}.
1045 Absolute (as opposed to PC relative) call and jump operands must be
1046 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1047 always chooses PC relative addressing for jump/call labels.
1049 Any instruction that has a memory operand, but no register operand,
1050 @emph{must} specify its size (byte, word, long, or quadruple) with an
1051 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1054 The x86-64 architecture adds an RIP (instruction pointer relative)
1055 addressing. This addressing mode is specified by using @samp{rip} as a
1056 base register. Only constant offsets are valid. For example:
1059 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1060 Points to the address 1234 bytes past the end of the current
1063 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1064 Points to the @code{symbol} in RIP relative way, this is shorter than
1065 the default absolute addressing.
1068 Other addressing modes remain unchanged in x86-64 architecture, except
1069 registers used are 64-bit instead of 32-bit.
1072 @section Handling of Jump Instructions
1074 @cindex jump optimization, i386
1075 @cindex i386 jump optimization
1076 @cindex jump optimization, x86-64
1077 @cindex x86-64 jump optimization
1078 Jump instructions are always optimized to use the smallest possible
1079 displacements. This is accomplished by using byte (8-bit) displacement
1080 jumps whenever the target is sufficiently close. If a byte displacement
1081 is insufficient a long displacement is used. We do not support
1082 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1083 instruction with the @samp{data16} instruction prefix), since the 80386
1084 insists upon masking @samp{%eip} to 16 bits after the word displacement
1085 is added. (See also @pxref{i386-Arch})
1087 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1088 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1089 displacements, so that if you use these instructions (@code{@value{GCC}} does
1090 not use them) you may get an error message (and incorrect code). The AT&T
1091 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1102 @section Floating Point
1104 @cindex i386 floating point
1105 @cindex floating point, i386
1106 @cindex x86-64 floating point
1107 @cindex floating point, x86-64
1108 All 80387 floating point types except packed BCD are supported.
1109 (BCD support may be added without much difficulty). These data
1110 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1111 double (64-bit), and extended (80-bit) precision floating point.
1112 Each supported type has an instruction mnemonic suffix and a constructor
1113 associated with it. Instruction mnemonic suffixes specify the operand's
1114 data type. Constructors build these data types into memory.
1116 @cindex @code{float} directive, i386
1117 @cindex @code{single} directive, i386
1118 @cindex @code{double} directive, i386
1119 @cindex @code{tfloat} directive, i386
1120 @cindex @code{float} directive, x86-64
1121 @cindex @code{single} directive, x86-64
1122 @cindex @code{double} directive, x86-64
1123 @cindex @code{tfloat} directive, x86-64
1126 Floating point constructors are @samp{.float} or @samp{.single},
1127 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1128 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1129 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1130 only supports this format via the @samp{fldt} (load 80-bit real to stack
1131 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1133 @cindex @code{word} directive, i386
1134 @cindex @code{long} directive, i386
1135 @cindex @code{int} directive, i386
1136 @cindex @code{quad} directive, i386
1137 @cindex @code{word} directive, x86-64
1138 @cindex @code{long} directive, x86-64
1139 @cindex @code{int} directive, x86-64
1140 @cindex @code{quad} directive, x86-64
1142 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1143 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1144 corresponding instruction mnemonic suffixes are @samp{s} (single),
1145 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1146 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1147 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1148 stack) instructions.
1151 Register to register operations should not use instruction mnemonic suffixes.
1152 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1153 wrote @samp{fst %st, %st(1)}, since all register to register operations
1154 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1155 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1156 then stores the result in the 4 byte location @samp{mem})
1159 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1162 @cindex 3DNow!, i386
1165 @cindex 3DNow!, x86-64
1166 @cindex SIMD, x86-64
1168 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1169 instructions for integer data), available on Intel's Pentium MMX
1170 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1171 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1172 instruction set (SIMD instructions for 32-bit floating point data)
1173 available on AMD's K6-2 processor and possibly others in the future.
1175 Currently, @code{@value{AS}} does not support Intel's floating point
1178 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1179 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1180 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1181 floating point values. The MMX registers cannot be used at the same time
1182 as the floating point stack.
1184 See Intel and AMD documentation, keeping in mind that the operand order in
1185 instructions is reversed from the Intel syntax.
1188 @section AMD's Lightweight Profiling Instructions
1193 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1194 instruction set, available on AMD's Family 15h (Orochi) processors.
1196 LWP enables applications to collect and manage performance data, and
1197 react to performance events. The collection of performance data
1198 requires no context switches. LWP runs in the context of a thread and
1199 so several counters can be used independently across multiple threads.
1200 LWP can be used in both 64-bit and legacy 32-bit modes.
1202 For detailed information on the LWP instruction set, see the
1203 @cite{AMD Lightweight Profiling Specification} available at
1204 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1207 @section Bit Manipulation Instructions
1212 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1214 BMI instructions provide several instructions implementing individual
1215 bit manipulation operations such as isolation, masking, setting, or
1218 @c Need to add a specification citation here when available.
1221 @section AMD's Trailing Bit Manipulation Instructions
1226 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1227 instruction set, available on AMD's BDVER2 processors (Trinity and
1230 TBM instructions provide instructions implementing individual bit
1231 manipulation operations such as isolating, masking, setting, resetting,
1232 complementing, and operations on trailing zeros and ones.
1234 @c Need to add a specification citation here when available.
1237 @section Writing 16-bit Code
1239 @cindex i386 16-bit code
1240 @cindex 16-bit code, i386
1241 @cindex real-mode code, i386
1242 @cindex @code{code16gcc} directive, i386
1243 @cindex @code{code16} directive, i386
1244 @cindex @code{code32} directive, i386
1245 @cindex @code{code64} directive, i386
1246 @cindex @code{code64} directive, x86-64
1247 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1248 or 64-bit x86-64 code depending on the default configuration,
1249 it also supports writing code to run in real mode or in 16-bit protected
1250 mode code segments. To do this, put a @samp{.code16} or
1251 @samp{.code16gcc} directive before the assembly language instructions to
1252 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1253 32-bit code with the @samp{.code32} directive or 64-bit code with the
1254 @samp{.code64} directive.
1256 @samp{.code16gcc} provides experimental support for generating 16-bit
1257 code from gcc, and differs from @samp{.code16} in that @samp{call},
1258 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1259 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1260 default to 32-bit size. This is so that the stack pointer is
1261 manipulated in the same way over function calls, allowing access to
1262 function parameters at the same stack offsets as in 32-bit mode.
1263 @samp{.code16gcc} also automatically adds address size prefixes where
1264 necessary to use the 32-bit addressing modes that gcc generates.
1266 The code which @code{@value{AS}} generates in 16-bit mode will not
1267 necessarily run on a 16-bit pre-80386 processor. To write code that
1268 runs on such a processor, you must refrain from using @emph{any} 32-bit
1269 constructs which require @code{@value{AS}} to output address or operand
1272 Note that writing 16-bit code instructions by explicitly specifying a
1273 prefix or an instruction mnemonic suffix within a 32-bit code section
1274 generates different machine instructions than those generated for a
1275 16-bit code segment. In a 32-bit code section, the following code
1276 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1277 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1283 The same code in a 16-bit code section would generate the machine
1284 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1285 is correct since the processor default operand size is assumed to be 16
1286 bits in a 16-bit code section.
1289 @section Specifying CPU Architecture
1291 @cindex arch directive, i386
1292 @cindex i386 arch directive
1293 @cindex arch directive, x86-64
1294 @cindex x86-64 arch directive
1296 @code{@value{AS}} may be told to assemble for a particular CPU
1297 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1298 directive enables a warning when gas detects an instruction that is not
1299 supported on the CPU specified. The choices for @var{cpu_type} are:
1301 @multitable @columnfractions .20 .20 .20 .20
1302 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1303 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1304 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1305 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1306 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1307 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1308 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1309 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1310 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1311 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1312 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1313 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1314 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1315 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1316 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1317 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1318 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1319 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1320 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1321 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1322 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1323 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1324 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1325 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1326 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1327 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1328 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1329 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1330 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
1331 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1332 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1333 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1334 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1337 Apart from the warning, there are only two other effects on
1338 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1339 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1340 will automatically use a two byte opcode sequence. The larger three
1341 byte opcode sequence is used on the 486 (and when no architecture is
1342 specified) because it executes faster on the 486. Note that you can
1343 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1344 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1345 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1346 conditional jumps will be promoted when necessary to a two instruction
1347 sequence consisting of a conditional jump of the opposite sense around
1348 an unconditional jump to the target.
1350 Following the CPU architecture (but not a sub-architecture, which are those
1351 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1352 control automatic promotion of conditional jumps. @samp{jumps} is the
1353 default, and enables jump promotion; All external jumps will be of the long
1354 variety, and file-local jumps will be promoted as necessary.
1355 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1356 byte offset jumps, and warns about file-local conditional jumps that
1357 @code{@value{AS}} promotes.
1358 Unconditional jumps are treated as for @samp{jumps}.
1367 @section AT&T Syntax bugs
1369 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1370 assemblers, generate floating point instructions with reversed source
1371 and destination registers in certain cases. Unfortunately, gcc and
1372 possibly many other programs use this reversed syntax, so we're stuck
1381 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1382 than the expected @samp{%st(3) - %st}. This happens with all the
1383 non-commutative arithmetic floating point operations with two register
1384 operands where the source register is @samp{%st} and the destination
1385 register is @samp{%st(i)}.
1390 @cindex i386 @code{mul}, @code{imul} instructions
1391 @cindex @code{mul} instruction, i386
1392 @cindex @code{imul} instruction, i386
1393 @cindex @code{mul} instruction, x86-64
1394 @cindex @code{imul} instruction, x86-64
1395 There is some trickery concerning the @samp{mul} and @samp{imul}
1396 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1397 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1398 for @samp{imul}) can be output only in the one operand form. Thus,
1399 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1400 the expanding multiply would clobber the @samp{%edx} register, and this
1401 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1402 64-bit product in @samp{%edx:%eax}.
1404 We have added a two operand form of @samp{imul} when the first operand
1405 is an immediate mode expression and the second operand is a register.
1406 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1407 example, can be done with @samp{imul $69, %eax} rather than @samp{imul