1 @c Copyright (C) 1991-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics. For example,
132 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
133 @var{vmx}. The following extensions are currently supported:
183 @code{avx512_4fmaps},
184 @code{avx512_4vnniw},
185 @code{avx512_vpopcntdq},
195 @code{noavx512_4fmaps},
196 @code{noavx512_4vnniw},
197 @code{noavx512_vpopcntdq},
234 Note that rather than extending a basic instruction set, the extension
235 mnemonics starting with @code{no} revoke the respective functionality.
237 When the @code{.arch} directive is used with @option{-march}, the
238 @code{.arch} directive will take precedent.
240 @cindex @samp{-mtune=} option, i386
241 @cindex @samp{-mtune=} option, x86-64
242 @item -mtune=@var{CPU}
243 This option specifies a processor to optimize for. When used in
244 conjunction with the @option{-march} option, only instructions
245 of the processor specified by the @option{-march} option will be
248 Valid @var{CPU} values are identical to the processor list of
249 @option{-march=@var{CPU}}.
251 @cindex @samp{-msse2avx} option, i386
252 @cindex @samp{-msse2avx} option, x86-64
254 This option specifies that the assembler should encode SSE instructions
257 @cindex @samp{-msse-check=} option, i386
258 @cindex @samp{-msse-check=} option, x86-64
259 @item -msse-check=@var{none}
260 @itemx -msse-check=@var{warning}
261 @itemx -msse-check=@var{error}
262 These options control if the assembler should check SSE instructions.
263 @option{-msse-check=@var{none}} will make the assembler not to check SSE
264 instructions, which is the default. @option{-msse-check=@var{warning}}
265 will make the assembler issue a warning for any SSE instruction.
266 @option{-msse-check=@var{error}} will make the assembler issue an error
267 for any SSE instruction.
269 @cindex @samp{-mavxscalar=} option, i386
270 @cindex @samp{-mavxscalar=} option, x86-64
271 @item -mavxscalar=@var{128}
272 @itemx -mavxscalar=@var{256}
273 These options control how the assembler should encode scalar AVX
274 instructions. @option{-mavxscalar=@var{128}} will encode scalar
275 AVX instructions with 128bit vector length, which is the default.
276 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
277 with 256bit vector length.
279 @cindex @samp{-mevexlig=} option, i386
280 @cindex @samp{-mevexlig=} option, x86-64
281 @item -mevexlig=@var{128}
282 @itemx -mevexlig=@var{256}
283 @itemx -mevexlig=@var{512}
284 These options control how the assembler should encode length-ignored
285 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
286 EVEX instructions with 128bit vector length, which is the default.
287 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
288 encode LIG EVEX instructions with 256bit and 512bit vector length,
291 @cindex @samp{-mevexwig=} option, i386
292 @cindex @samp{-mevexwig=} option, x86-64
293 @item -mevexwig=@var{0}
294 @itemx -mevexwig=@var{1}
295 These options control how the assembler should encode w-ignored (WIG)
296 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
297 EVEX instructions with evex.w = 0, which is the default.
298 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
301 @cindex @samp{-mmnemonic=} option, i386
302 @cindex @samp{-mmnemonic=} option, x86-64
303 @item -mmnemonic=@var{att}
304 @itemx -mmnemonic=@var{intel}
305 This option specifies instruction mnemonic for matching instructions.
306 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
309 @cindex @samp{-msyntax=} option, i386
310 @cindex @samp{-msyntax=} option, x86-64
311 @item -msyntax=@var{att}
312 @itemx -msyntax=@var{intel}
313 This option specifies instruction syntax when processing instructions.
314 The @code{.att_syntax} and @code{.intel_syntax} directives will
317 @cindex @samp{-mnaked-reg} option, i386
318 @cindex @samp{-mnaked-reg} option, x86-64
320 This option specifies that registers don't require a @samp{%} prefix.
321 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
323 @cindex @samp{-madd-bnd-prefix} option, i386
324 @cindex @samp{-madd-bnd-prefix} option, x86-64
325 @item -madd-bnd-prefix
326 This option forces the assembler to add BND prefix to all branches, even
327 if such prefix was not explicitly specified in the source code.
329 @cindex @samp{-mshared} option, i386
330 @cindex @samp{-mshared} option, x86-64
332 On ELF target, the assembler normally optimizes out non-PLT relocations
333 against defined non-weak global branch targets with default visibility.
334 The @samp{-mshared} option tells the assembler to generate code which
335 may go into a shared library where all non-weak global branch targets
336 with default visibility can be preempted. The resulting code is
337 slightly bigger. This option only affects the handling of branch
340 @cindex @samp{-mbig-obj} option, x86-64
342 On x86-64 PE/COFF target this option forces the use of big object file
343 format, which allows more than 32768 sections.
345 @cindex @samp{-momit-lock-prefix=} option, i386
346 @cindex @samp{-momit-lock-prefix=} option, x86-64
347 @item -momit-lock-prefix=@var{no}
348 @itemx -momit-lock-prefix=@var{yes}
349 These options control how the assembler should encode lock prefix.
350 This option is intended as a workaround for processors, that fail on
351 lock prefix. This option can only be safely used with single-core,
352 single-thread computers
353 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
354 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
355 which is the default.
357 @cindex @samp{-mfence-as-lock-add=} option, i386
358 @cindex @samp{-mfence-as-lock-add=} option, x86-64
359 @item -mfence-as-lock-add=@var{no}
360 @itemx -mfence-as-lock-add=@var{yes}
361 These options control how the assembler should encode lfence, mfence and
363 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
364 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
365 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
366 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
367 sfence as usual, which is the default.
369 @cindex @samp{-mrelax-relocations=} option, i386
370 @cindex @samp{-mrelax-relocations=} option, x86-64
371 @item -mrelax-relocations=@var{no}
372 @itemx -mrelax-relocations=@var{yes}
373 These options control whether the assembler should generate relax
374 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
375 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
376 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
377 @option{-mrelax-relocations=@var{no}} will not generate relax
378 relocations. The default can be controlled by a configure option
379 @option{--enable-x86-relax-relocations}.
381 @cindex @samp{-mevexrcig=} option, i386
382 @cindex @samp{-mevexrcig=} option, x86-64
383 @item -mevexrcig=@var{rne}
384 @itemx -mevexrcig=@var{rd}
385 @itemx -mevexrcig=@var{ru}
386 @itemx -mevexrcig=@var{rz}
387 These options control how the assembler should encode SAE-only
388 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
389 of EVEX instruction with 00, which is the default.
390 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
391 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
392 with 01, 10 and 11 RC bits, respectively.
394 @cindex @samp{-mamd64} option, x86-64
395 @cindex @samp{-mintel64} option, x86-64
398 This option specifies that the assembler should accept only AMD64 or
399 Intel64 ISA in 64-bit mode. The default is to accept both.
404 @node i386-Directives
405 @section x86 specific Directives
407 @cindex machine directives, x86
408 @cindex x86 machine directives
411 @cindex @code{lcomm} directive, COFF
412 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
413 Reserve @var{length} (an absolute expression) bytes for a local common
414 denoted by @var{symbol}. The section and value of @var{symbol} are
415 those of the new local common. The addresses are allocated in the bss
416 section, so that at run-time the bytes start off zeroed. Since
417 @var{symbol} is not declared global, it is normally not visible to
418 @code{@value{LD}}. The optional third parameter, @var{alignment},
419 specifies the desired alignment of the symbol in the bss section.
421 This directive is only available for COFF based x86 targets.
423 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
429 @section i386 Syntactical Considerations
431 * i386-Variations:: AT&T Syntax versus Intel Syntax
432 * i386-Chars:: Special Characters
435 @node i386-Variations
436 @subsection AT&T Syntax versus Intel Syntax
438 @cindex i386 intel_syntax pseudo op
439 @cindex intel_syntax pseudo op, i386
440 @cindex i386 att_syntax pseudo op
441 @cindex att_syntax pseudo op, i386
442 @cindex i386 syntax compatibility
443 @cindex syntax compatibility, i386
444 @cindex x86-64 intel_syntax pseudo op
445 @cindex intel_syntax pseudo op, x86-64
446 @cindex x86-64 att_syntax pseudo op
447 @cindex att_syntax pseudo op, x86-64
448 @cindex x86-64 syntax compatibility
449 @cindex syntax compatibility, x86-64
451 @code{@value{AS}} now supports assembly using Intel assembler syntax.
452 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
453 back to the usual AT&T mode for compatibility with the output of
454 @code{@value{GCC}}. Either of these directives may have an optional
455 argument, @code{prefix}, or @code{noprefix} specifying whether registers
456 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
457 different from Intel syntax. We mention these differences because
458 almost all 80386 documents use Intel syntax. Notable differences
459 between the two syntaxes are:
461 @cindex immediate operands, i386
462 @cindex i386 immediate operands
463 @cindex register operands, i386
464 @cindex i386 register operands
465 @cindex jump/call operands, i386
466 @cindex i386 jump/call operands
467 @cindex operand delimiters, i386
469 @cindex immediate operands, x86-64
470 @cindex x86-64 immediate operands
471 @cindex register operands, x86-64
472 @cindex x86-64 register operands
473 @cindex jump/call operands, x86-64
474 @cindex x86-64 jump/call operands
475 @cindex operand delimiters, x86-64
478 AT&T immediate operands are preceded by @samp{$}; Intel immediate
479 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
480 AT&T register operands are preceded by @samp{%}; Intel register operands
481 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
482 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
484 @cindex i386 source, destination operands
485 @cindex source, destination operands; i386
486 @cindex x86-64 source, destination operands
487 @cindex source, destination operands; x86-64
489 AT&T and Intel syntax use the opposite order for source and destination
490 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
491 @samp{source, dest} convention is maintained for compatibility with
492 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
493 instructions with 2 immediate operands, such as the @samp{enter}
494 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
496 @cindex mnemonic suffixes, i386
497 @cindex sizes operands, i386
498 @cindex i386 size suffixes
499 @cindex mnemonic suffixes, x86-64
500 @cindex sizes operands, x86-64
501 @cindex x86-64 size suffixes
503 In AT&T syntax the size of memory operands is determined from the last
504 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
505 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
506 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
507 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
508 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
509 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
512 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
513 instruction with the 64-bit displacement or immediate operand.
515 @cindex return instructions, i386
516 @cindex i386 jump, call, return
517 @cindex return instructions, x86-64
518 @cindex x86-64 jump, call, return
520 Immediate form long jumps and calls are
521 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
523 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
525 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
526 @samp{ret far @var{stack-adjust}}.
528 @cindex sections, i386
529 @cindex i386 sections
530 @cindex sections, x86-64
531 @cindex x86-64 sections
533 The AT&T assembler does not provide support for multiple section
534 programs. Unix style systems expect all programs to be single sections.
538 @subsection Special Characters
540 @cindex line comment character, i386
541 @cindex i386 line comment character
542 The presence of a @samp{#} appearing anywhere on a line indicates the
543 start of a comment that extends to the end of that line.
545 If a @samp{#} appears as the first character of a line then the whole
546 line is treated as a comment, but in this case the line can also be a
547 logical line number directive (@pxref{Comments}) or a preprocessor
548 control command (@pxref{Preprocessing}).
550 If the @option{--divide} command line option has not been specified
551 then the @samp{/} character appearing anywhere on a line also
552 introduces a line comment.
554 @cindex line separator, i386
555 @cindex statement separator, i386
556 @cindex i386 line separator
557 The @samp{;} character can be used to separate statements on the same
561 @section i386-Mnemonics
562 @subsection Instruction Naming
564 @cindex i386 instruction naming
565 @cindex instruction naming, i386
566 @cindex x86-64 instruction naming
567 @cindex instruction naming, x86-64
569 Instruction mnemonics are suffixed with one character modifiers which
570 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
571 and @samp{q} specify byte, word, long and quadruple word operands. If
572 no suffix is specified by an instruction then @code{@value{AS}} tries to
573 fill in the missing suffix based on the destination register operand
574 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
575 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
576 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
577 assembler which assumes that a missing mnemonic suffix implies long
578 operand size. (This incompatibility does not affect compiler output
579 since compilers always explicitly specify the mnemonic suffix.)
581 Almost all instructions have the same names in AT&T and Intel format.
582 There are a few exceptions. The sign extend and zero extend
583 instructions need two sizes to specify them. They need a size to
584 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
585 is accomplished by using two instruction mnemonic suffixes in AT&T
586 syntax. Base names for sign extend and zero extend are
587 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
588 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
589 are tacked on to this base name, the @emph{from} suffix before the
590 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
591 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
592 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
593 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
594 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
597 @cindex encoding options, i386
598 @cindex encoding options, x86-64
600 Different encoding options can be specified via optional mnemonic
601 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
602 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
603 prefers 8bit or 32bit displacement in encoding.
605 @cindex conversion instructions, i386
606 @cindex i386 conversion instructions
607 @cindex conversion instructions, x86-64
608 @cindex x86-64 conversion instructions
609 The Intel-syntax conversion instructions
613 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
616 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
619 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
622 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
625 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
629 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
630 @samp{%rdx:%rax} (x86-64 only),
634 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
635 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
638 @cindex jump instructions, i386
639 @cindex call instructions, i386
640 @cindex jump instructions, x86-64
641 @cindex call instructions, x86-64
642 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
643 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
646 @subsection AT&T Mnemonic versus Intel Mnemonic
648 @cindex i386 mnemonic compatibility
649 @cindex mnemonic compatibility, i386
651 @code{@value{AS}} supports assembly using Intel mnemonic.
652 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
653 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
654 syntax for compatibility with the output of @code{@value{GCC}}.
655 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
656 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
657 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
658 assembler with different mnemonics from those in Intel IA32 specification.
659 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
662 @section Register Naming
664 @cindex i386 registers
665 @cindex registers, i386
666 @cindex x86-64 registers
667 @cindex registers, x86-64
668 Register operands are always prefixed with @samp{%}. The 80386 registers
673 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
674 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
675 frame pointer), and @samp{%esp} (the stack pointer).
678 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
679 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
682 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
683 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
684 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
685 @samp{%cx}, and @samp{%dx})
688 the 6 section registers @samp{%cs} (code section), @samp{%ds}
689 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
693 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
694 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
697 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
698 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
701 the 2 test registers @samp{%tr6} and @samp{%tr7}.
704 the 8 floating point register stack @samp{%st} or equivalently
705 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
706 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
707 These registers are overloaded by 8 MMX registers @samp{%mm0},
708 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
709 @samp{%mm6} and @samp{%mm7}.
712 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
713 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
716 The AMD x86-64 architecture extends the register set by:
720 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
721 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
722 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
726 the 8 extended registers @samp{%r8}--@samp{%r15}.
729 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
732 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
735 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
738 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
741 the 8 debug registers: @samp{%db8}--@samp{%db15}.
744 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
747 With the AVX extensions more registers were made available:
752 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
753 available in 32-bit mode). The bottom 128 bits are overlaid with the
754 @samp{xmm0}--@samp{xmm15} registers.
758 The AVX2 extensions made in 64-bit mode more registers available:
763 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
764 registers @samp{%ymm16}--@samp{%ymm31}.
768 The AVX512 extensions added the following registers:
773 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
774 available in 32-bit mode). The bottom 128 bits are overlaid with the
775 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
776 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
779 the 8 mask registers @samp{%k0}--@samp{%k7}.
784 @section Instruction Prefixes
786 @cindex i386 instruction prefixes
787 @cindex instruction prefixes, i386
788 @cindex prefixes, i386
789 Instruction prefixes are used to modify the following instruction. They
790 are used to repeat string instructions, to provide section overrides, to
791 perform bus lock operations, and to change operand and address sizes.
792 (Most instructions that normally operate on 32-bit operands will use
793 16-bit operands if the instruction has an ``operand size'' prefix.)
794 Instruction prefixes are best written on the same line as the instruction
795 they act upon. For example, the @samp{scas} (scan string) instruction is
799 repne scas %es:(%edi),%al
802 You may also place prefixes on the lines immediately preceding the
803 instruction, but this circumvents checks that @code{@value{AS}} does
804 with prefixes, and will not work with all prefixes.
806 Here is a list of instruction prefixes:
808 @cindex section override prefixes, i386
811 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
812 @samp{fs}, @samp{gs}. These are automatically added by specifying
813 using the @var{section}:@var{memory-operand} form for memory references.
815 @cindex size prefixes, i386
817 Operand/Address size prefixes @samp{data16} and @samp{addr16}
818 change 32-bit operands/addresses into 16-bit operands/addresses,
819 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
820 @code{.code16} section) into 32-bit operands/addresses. These prefixes
821 @emph{must} appear on the same line of code as the instruction they
822 modify. For example, in a 16-bit @code{.code16} section, you might
829 @cindex bus lock prefixes, i386
830 @cindex inhibiting interrupts, i386
832 The bus lock prefix @samp{lock} inhibits interrupts during execution of
833 the instruction it precedes. (This is only valid with certain
834 instructions; see a 80386 manual for details).
836 @cindex coprocessor wait, i386
838 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
839 complete the current instruction. This should never be needed for the
840 80386/80387 combination.
842 @cindex repeat prefixes, i386
844 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
845 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
846 times if the current address size is 16-bits).
847 @cindex REX prefixes, i386
849 The @samp{rex} family of prefixes is used by x86-64 to encode
850 extensions to i386 instruction set. The @samp{rex} prefix has four
851 bits --- an operand size overwrite (@code{64}) used to change operand size
852 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
855 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
856 instruction emits @samp{rex} prefix with all the bits set. By omitting
857 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
858 prefixes as well. Normally, there is no need to write the prefixes
859 explicitly, since gas will automatically generate them based on the
860 instruction operands.
864 @section Memory References
866 @cindex i386 memory references
867 @cindex memory references, i386
868 @cindex x86-64 memory references
869 @cindex memory references, x86-64
870 An Intel syntax indirect memory reference of the form
873 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
877 is translated into the AT&T syntax
880 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
884 where @var{base} and @var{index} are the optional 32-bit base and
885 index registers, @var{disp} is the optional displacement, and
886 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
887 to calculate the address of the operand. If no @var{scale} is
888 specified, @var{scale} is taken to be 1. @var{section} specifies the
889 optional section register for the memory operand, and may override the
890 default section register (see a 80386 manual for section register
891 defaults). Note that section overrides in AT&T syntax @emph{must}
892 be preceded by a @samp{%}. If you specify a section override which
893 coincides with the default section register, @code{@value{AS}} does @emph{not}
894 output any section register override prefixes to assemble the given
895 instruction. Thus, section overrides can be specified to emphasize which
896 section register is used for a given memory operand.
898 Here are some examples of Intel and AT&T style memory references:
901 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
902 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
903 missing, and the default section is used (@samp{%ss} for addressing with
904 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
906 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
907 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
908 @samp{foo}. All other fields are missing. The section register here
909 defaults to @samp{%ds}.
911 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
912 This uses the value pointed to by @samp{foo} as a memory operand.
913 Note that @var{base} and @var{index} are both missing, but there is only
914 @emph{one} @samp{,}. This is a syntactic exception.
916 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
917 This selects the contents of the variable @samp{foo} with section
918 register @var{section} being @samp{%gs}.
921 Absolute (as opposed to PC relative) call and jump operands must be
922 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
923 always chooses PC relative addressing for jump/call labels.
925 Any instruction that has a memory operand, but no register operand,
926 @emph{must} specify its size (byte, word, long, or quadruple) with an
927 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
930 The x86-64 architecture adds an RIP (instruction pointer relative)
931 addressing. This addressing mode is specified by using @samp{rip} as a
932 base register. Only constant offsets are valid. For example:
935 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
936 Points to the address 1234 bytes past the end of the current
939 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
940 Points to the @code{symbol} in RIP relative way, this is shorter than
941 the default absolute addressing.
944 Other addressing modes remain unchanged in x86-64 architecture, except
945 registers used are 64-bit instead of 32-bit.
948 @section Handling of Jump Instructions
950 @cindex jump optimization, i386
951 @cindex i386 jump optimization
952 @cindex jump optimization, x86-64
953 @cindex x86-64 jump optimization
954 Jump instructions are always optimized to use the smallest possible
955 displacements. This is accomplished by using byte (8-bit) displacement
956 jumps whenever the target is sufficiently close. If a byte displacement
957 is insufficient a long displacement is used. We do not support
958 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
959 instruction with the @samp{data16} instruction prefix), since the 80386
960 insists upon masking @samp{%eip} to 16 bits after the word displacement
961 is added. (See also @pxref{i386-Arch})
963 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
964 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
965 displacements, so that if you use these instructions (@code{@value{GCC}} does
966 not use them) you may get an error message (and incorrect code). The AT&T
967 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
978 @section Floating Point
980 @cindex i386 floating point
981 @cindex floating point, i386
982 @cindex x86-64 floating point
983 @cindex floating point, x86-64
984 All 80387 floating point types except packed BCD are supported.
985 (BCD support may be added without much difficulty). These data
986 types are 16-, 32-, and 64- bit integers, and single (32-bit),
987 double (64-bit), and extended (80-bit) precision floating point.
988 Each supported type has an instruction mnemonic suffix and a constructor
989 associated with it. Instruction mnemonic suffixes specify the operand's
990 data type. Constructors build these data types into memory.
992 @cindex @code{float} directive, i386
993 @cindex @code{single} directive, i386
994 @cindex @code{double} directive, i386
995 @cindex @code{tfloat} directive, i386
996 @cindex @code{float} directive, x86-64
997 @cindex @code{single} directive, x86-64
998 @cindex @code{double} directive, x86-64
999 @cindex @code{tfloat} directive, x86-64
1002 Floating point constructors are @samp{.float} or @samp{.single},
1003 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1004 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1005 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1006 only supports this format via the @samp{fldt} (load 80-bit real to stack
1007 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1009 @cindex @code{word} directive, i386
1010 @cindex @code{long} directive, i386
1011 @cindex @code{int} directive, i386
1012 @cindex @code{quad} directive, i386
1013 @cindex @code{word} directive, x86-64
1014 @cindex @code{long} directive, x86-64
1015 @cindex @code{int} directive, x86-64
1016 @cindex @code{quad} directive, x86-64
1018 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1019 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1020 corresponding instruction mnemonic suffixes are @samp{s} (single),
1021 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1022 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1023 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1024 stack) instructions.
1027 Register to register operations should not use instruction mnemonic suffixes.
1028 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1029 wrote @samp{fst %st, %st(1)}, since all register to register operations
1030 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1031 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1032 then stores the result in the 4 byte location @samp{mem})
1035 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1038 @cindex 3DNow!, i386
1041 @cindex 3DNow!, x86-64
1042 @cindex SIMD, x86-64
1044 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1045 instructions for integer data), available on Intel's Pentium MMX
1046 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1047 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1048 instruction set (SIMD instructions for 32-bit floating point data)
1049 available on AMD's K6-2 processor and possibly others in the future.
1051 Currently, @code{@value{AS}} does not support Intel's floating point
1054 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1055 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1056 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1057 floating point values. The MMX registers cannot be used at the same time
1058 as the floating point stack.
1060 See Intel and AMD documentation, keeping in mind that the operand order in
1061 instructions is reversed from the Intel syntax.
1064 @section AMD's Lightweight Profiling Instructions
1069 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1070 instruction set, available on AMD's Family 15h (Orochi) processors.
1072 LWP enables applications to collect and manage performance data, and
1073 react to performance events. The collection of performance data
1074 requires no context switches. LWP runs in the context of a thread and
1075 so several counters can be used independently across multiple threads.
1076 LWP can be used in both 64-bit and legacy 32-bit modes.
1078 For detailed information on the LWP instruction set, see the
1079 @cite{AMD Lightweight Profiling Specification} available at
1080 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1083 @section Bit Manipulation Instructions
1088 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1090 BMI instructions provide several instructions implementing individual
1091 bit manipulation operations such as isolation, masking, setting, or
1094 @c Need to add a specification citation here when available.
1097 @section AMD's Trailing Bit Manipulation Instructions
1102 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1103 instruction set, available on AMD's BDVER2 processors (Trinity and
1106 TBM instructions provide instructions implementing individual bit
1107 manipulation operations such as isolating, masking, setting, resetting,
1108 complementing, and operations on trailing zeros and ones.
1110 @c Need to add a specification citation here when available.
1113 @section Writing 16-bit Code
1115 @cindex i386 16-bit code
1116 @cindex 16-bit code, i386
1117 @cindex real-mode code, i386
1118 @cindex @code{code16gcc} directive, i386
1119 @cindex @code{code16} directive, i386
1120 @cindex @code{code32} directive, i386
1121 @cindex @code{code64} directive, i386
1122 @cindex @code{code64} directive, x86-64
1123 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1124 or 64-bit x86-64 code depending on the default configuration,
1125 it also supports writing code to run in real mode or in 16-bit protected
1126 mode code segments. To do this, put a @samp{.code16} or
1127 @samp{.code16gcc} directive before the assembly language instructions to
1128 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1129 32-bit code with the @samp{.code32} directive or 64-bit code with the
1130 @samp{.code64} directive.
1132 @samp{.code16gcc} provides experimental support for generating 16-bit
1133 code from gcc, and differs from @samp{.code16} in that @samp{call},
1134 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1135 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1136 default to 32-bit size. This is so that the stack pointer is
1137 manipulated in the same way over function calls, allowing access to
1138 function parameters at the same stack offsets as in 32-bit mode.
1139 @samp{.code16gcc} also automatically adds address size prefixes where
1140 necessary to use the 32-bit addressing modes that gcc generates.
1142 The code which @code{@value{AS}} generates in 16-bit mode will not
1143 necessarily run on a 16-bit pre-80386 processor. To write code that
1144 runs on such a processor, you must refrain from using @emph{any} 32-bit
1145 constructs which require @code{@value{AS}} to output address or operand
1148 Note that writing 16-bit code instructions by explicitly specifying a
1149 prefix or an instruction mnemonic suffix within a 32-bit code section
1150 generates different machine instructions than those generated for a
1151 16-bit code segment. In a 32-bit code section, the following code
1152 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1153 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1159 The same code in a 16-bit code section would generate the machine
1160 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1161 is correct since the processor default operand size is assumed to be 16
1162 bits in a 16-bit code section.
1165 @section Specifying CPU Architecture
1167 @cindex arch directive, i386
1168 @cindex i386 arch directive
1169 @cindex arch directive, x86-64
1170 @cindex x86-64 arch directive
1172 @code{@value{AS}} may be told to assemble for a particular CPU
1173 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1174 directive enables a warning when gas detects an instruction that is not
1175 supported on the CPU specified. The choices for @var{cpu_type} are:
1177 @multitable @columnfractions .20 .20 .20 .20
1178 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1179 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1180 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1181 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1182 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1183 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1184 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1185 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1186 @item @samp{generic32} @tab @samp{generic64}
1187 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1188 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1189 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1190 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1191 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1192 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1193 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1194 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1195 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1196 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1197 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1198 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1199 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1200 @item @samp{.avx512_vpopcntdq} @tab @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite}
1201 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1202 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1203 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1204 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1207 Apart from the warning, there are only two other effects on
1208 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1209 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1210 will automatically use a two byte opcode sequence. The larger three
1211 byte opcode sequence is used on the 486 (and when no architecture is
1212 specified) because it executes faster on the 486. Note that you can
1213 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1214 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1215 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1216 conditional jumps will be promoted when necessary to a two instruction
1217 sequence consisting of a conditional jump of the opposite sense around
1218 an unconditional jump to the target.
1220 Following the CPU architecture (but not a sub-architecture, which are those
1221 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1222 control automatic promotion of conditional jumps. @samp{jumps} is the
1223 default, and enables jump promotion; All external jumps will be of the long
1224 variety, and file-local jumps will be promoted as necessary.
1225 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1226 byte offset jumps, and warns about file-local conditional jumps that
1227 @code{@value{AS}} promotes.
1228 Unconditional jumps are treated as for @samp{jumps}.
1237 @section AT&T Syntax bugs
1239 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1240 assemblers, generate floating point instructions with reversed source
1241 and destination registers in certain cases. Unfortunately, gcc and
1242 possibly many other programs use this reversed syntax, so we're stuck
1251 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1252 than the expected @samp{%st(3) - %st}. This happens with all the
1253 non-commutative arithmetic floating point operations with two register
1254 operands where the source register is @samp{%st} and the destination
1255 register is @samp{%st(i)}.
1260 @cindex i386 @code{mul}, @code{imul} instructions
1261 @cindex @code{mul} instruction, i386
1262 @cindex @code{imul} instruction, i386
1263 @cindex @code{mul} instruction, x86-64
1264 @cindex @code{imul} instruction, x86-64
1265 There is some trickery concerning the @samp{mul} and @samp{imul}
1266 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1267 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1268 for @samp{imul}) can be output only in the one operand form. Thus,
1269 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1270 the expanding multiply would clobber the @samp{%edx} register, and this
1271 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1272 64-bit product in @samp{%edx:%eax}.
1274 We have added a two operand form of @samp{imul} when the first operand
1275 is an immediate mode expression and the second operand is a register.
1276 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1277 example, can be done with @samp{imul $69, %eax} rather than @samp{imul