Add -mno-shared to x86 assembler
[deliverable/binutils-gdb.git] / gas / doc / c-i386.texi
1 @c Copyright (C) 1991-2015 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
4 @c man end
5
6 @ifset GENERIC
7 @page
8 @node i386-Dependent
9 @chapter 80386 Dependent Features
10 @end ifset
11 @ifclear GENERIC
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
14 @end ifclear
15
16 @cindex i386 support
17 @cindex i80386 support
18 @cindex x86-64 support
19
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
23
24 @menu
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
41 * i386-Notes:: Notes
42 @end menu
43
44 @node i386-Options
45 @section Options
46
47 @cindex options for i386
48 @cindex options for x86-64
49 @cindex i386 options
50 @cindex x86-64 options
51
52 The i386 version of @code{@value{AS}} has a few machine
53 dependent options:
54
55 @c man begin OPTIONS
56 @table @gcctabopt
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
67 respectively.
68
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
73
74 @item -n
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
78
79 @cindex @samp{--divide} option, i386
80 @item --divide
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
86
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
94 @code{i8086},
95 @code{i186},
96 @code{i286},
97 @code{i386},
98 @code{i486},
99 @code{i586},
100 @code{i686},
101 @code{pentium},
102 @code{pentiumpro},
103 @code{pentiumii},
104 @code{pentiumiii},
105 @code{pentium4},
106 @code{prescott},
107 @code{nocona},
108 @code{core},
109 @code{core2},
110 @code{corei7},
111 @code{l1om},
112 @code{k1om},
113 @code{k6},
114 @code{k6_2},
115 @code{athlon},
116 @code{opteron},
117 @code{k8},
118 @code{amdfam10},
119 @code{bdver1},
120 @code{bdver2},
121 @code{bdver3},
122 @code{bdver4},
123 @code{znver1},
124 @code{btver1},
125 @code{btver2},
126 @code{generic32} and
127 @code{generic64}.
128
129 In addition to the basic instruction set, the assembler can be told to
130 accept various extension mnemonics. For example,
131 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
132 @var{vmx}. The following extensions are currently supported:
133 @code{8087},
134 @code{287},
135 @code{387},
136 @code{no87},
137 @code{mmx},
138 @code{nommx},
139 @code{sse},
140 @code{sse2},
141 @code{sse3},
142 @code{ssse3},
143 @code{sse4.1},
144 @code{sse4.2},
145 @code{sse4},
146 @code{nosse},
147 @code{avx},
148 @code{avx2},
149 @code{adx},
150 @code{rdseed},
151 @code{prfchw},
152 @code{smap},
153 @code{mpx},
154 @code{sha},
155 @code{prefetchwt1},
156 @code{clflushopt},
157 @code{se1},
158 @code{clwb},
159 @code{pcommit},
160 @code{avx512f},
161 @code{avx512cd},
162 @code{avx512er},
163 @code{avx512pf},
164 @code{avx512vl},
165 @code{avx512bw},
166 @code{avx512dq},
167 @code{avx512ifma},
168 @code{avx512vbmi},
169 @code{noavx},
170 @code{vmx},
171 @code{vmfunc},
172 @code{smx},
173 @code{xsave},
174 @code{xsaveopt},
175 @code{xsavec},
176 @code{xsaves},
177 @code{aes},
178 @code{pclmul},
179 @code{fsgsbase},
180 @code{rdrnd},
181 @code{f16c},
182 @code{bmi2},
183 @code{fma},
184 @code{movbe},
185 @code{ept},
186 @code{lzcnt},
187 @code{hle},
188 @code{rtm},
189 @code{invpcid},
190 @code{clflush},
191 @code{clzero},
192 @code{lwp},
193 @code{fma4},
194 @code{xop},
195 @code{cx16},
196 @code{syscall},
197 @code{rdtscp},
198 @code{3dnow},
199 @code{3dnowa},
200 @code{sse4a},
201 @code{sse5},
202 @code{svme},
203 @code{abm} and
204 @code{padlock}.
205 Note that rather than extending a basic instruction set, the extension
206 mnemonics starting with @code{no} revoke the respective functionality.
207
208 When the @code{.arch} directive is used with @option{-march}, the
209 @code{.arch} directive will take precedent.
210
211 @cindex @samp{-mtune=} option, i386
212 @cindex @samp{-mtune=} option, x86-64
213 @item -mtune=@var{CPU}
214 This option specifies a processor to optimize for. When used in
215 conjunction with the @option{-march} option, only instructions
216 of the processor specified by the @option{-march} option will be
217 generated.
218
219 Valid @var{CPU} values are identical to the processor list of
220 @option{-march=@var{CPU}}.
221
222 @cindex @samp{-msse2avx} option, i386
223 @cindex @samp{-msse2avx} option, x86-64
224 @item -msse2avx
225 This option specifies that the assembler should encode SSE instructions
226 with VEX prefix.
227
228 @cindex @samp{-msse-check=} option, i386
229 @cindex @samp{-msse-check=} option, x86-64
230 @item -msse-check=@var{none}
231 @itemx -msse-check=@var{warning}
232 @itemx -msse-check=@var{error}
233 These options control if the assembler should check SSE instructions.
234 @option{-msse-check=@var{none}} will make the assembler not to check SSE
235 instructions, which is the default. @option{-msse-check=@var{warning}}
236 will make the assembler issue a warning for any SSE instruction.
237 @option{-msse-check=@var{error}} will make the assembler issue an error
238 for any SSE instruction.
239
240 @cindex @samp{-mavxscalar=} option, i386
241 @cindex @samp{-mavxscalar=} option, x86-64
242 @item -mavxscalar=@var{128}
243 @itemx -mavxscalar=@var{256}
244 These options control how the assembler should encode scalar AVX
245 instructions. @option{-mavxscalar=@var{128}} will encode scalar
246 AVX instructions with 128bit vector length, which is the default.
247 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
248 with 256bit vector length.
249
250 @cindex @samp{-mevexlig=} option, i386
251 @cindex @samp{-mevexlig=} option, x86-64
252 @item -mevexlig=@var{128}
253 @itemx -mevexlig=@var{256}
254 @itemx -mevexlig=@var{512}
255 These options control how the assembler should encode length-ignored
256 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
257 EVEX instructions with 128bit vector length, which is the default.
258 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
259 encode LIG EVEX instructions with 256bit and 512bit vector length,
260 respectively.
261
262 @cindex @samp{-mevexwig=} option, i386
263 @cindex @samp{-mevexwig=} option, x86-64
264 @item -mevexwig=@var{0}
265 @itemx -mevexwig=@var{1}
266 These options control how the assembler should encode w-ignored (WIG)
267 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
268 EVEX instructions with evex.w = 0, which is the default.
269 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
270 evex.w = 1.
271
272 @cindex @samp{-mmnemonic=} option, i386
273 @cindex @samp{-mmnemonic=} option, x86-64
274 @item -mmnemonic=@var{att}
275 @itemx -mmnemonic=@var{intel}
276 This option specifies instruction mnemonic for matching instructions.
277 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
278 take precedent.
279
280 @cindex @samp{-msyntax=} option, i386
281 @cindex @samp{-msyntax=} option, x86-64
282 @item -msyntax=@var{att}
283 @itemx -msyntax=@var{intel}
284 This option specifies instruction syntax when processing instructions.
285 The @code{.att_syntax} and @code{.intel_syntax} directives will
286 take precedent.
287
288 @cindex @samp{-mnaked-reg} option, i386
289 @cindex @samp{-mnaked-reg} option, x86-64
290 @item -mnaked-reg
291 This opetion specifies that registers don't require a @samp{%} prefix.
292 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
293
294 @cindex @samp{-madd-bnd-prefix} option, i386
295 @cindex @samp{-madd-bnd-prefix} option, x86-64
296 @item -madd-bnd-prefix
297 This option forces the assembler to add BND prefix to all branches, even
298 if such prefix was not explicitly specified in the source code.
299
300 @cindex @samp{-mno-shared} option, i386
301 @cindex @samp{-mno-shared} option, x86-64
302 @item -mno-shared
303 On ELF target, the assembler normally generates code which can go into a
304 shared library where non-weak symbols can be preempted. The
305 @samp{-mno-shared} option tells the assembler to generate code not for
306 a shared library, where non-weak symbols won't be preempted. The
307 resulting code is slightly smaller. This option mainly affects the
308 handling of branch instructions.
309
310 @cindex @samp{-mbig-obj} option, x86-64
311 @item -mbig-obj
312 On x86-64 PE/COFF target this option forces the use of big object file
313 format, which allows more than 32768 sections.
314
315 @cindex @samp{-momit-lock-prefix=} option, i386
316 @cindex @samp{-momit-lock-prefix=} option, x86-64
317 @item -momit-lock-prefix=@var{no}
318 @itemx -momit-lock-prefix=@var{yes}
319 These options control how the assembler should encode lock prefix.
320 This option is intended as a workaround for processors, that fail on
321 lock prefix. This option can only be safely used with single-core,
322 single-thread computers
323 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
324 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
325 which is the default.
326
327 @cindex @samp{-mevexrcig=} option, i386
328 @cindex @samp{-mevexrcig=} option, x86-64
329 @item -mevexrcig=@var{rne}
330 @itemx -mevexrcig=@var{rd}
331 @itemx -mevexrcig=@var{ru}
332 @itemx -mevexrcig=@var{rz}
333 These options control how the assembler should encode SAE-only
334 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
335 of EVEX instruction with 00, which is the default.
336 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
337 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
338 with 01, 10 and 11 RC bits, respectively.
339
340 @end table
341 @c man end
342
343 @node i386-Directives
344 @section x86 specific Directives
345
346 @cindex machine directives, x86
347 @cindex x86 machine directives
348 @table @code
349
350 @cindex @code{lcomm} directive, COFF
351 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
352 Reserve @var{length} (an absolute expression) bytes for a local common
353 denoted by @var{symbol}. The section and value of @var{symbol} are
354 those of the new local common. The addresses are allocated in the bss
355 section, so that at run-time the bytes start off zeroed. Since
356 @var{symbol} is not declared global, it is normally not visible to
357 @code{@value{LD}}. The optional third parameter, @var{alignment},
358 specifies the desired alignment of the symbol in the bss section.
359
360 This directive is only available for COFF based x86 targets.
361
362 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
363 @c .largecomm
364
365 @end table
366
367 @node i386-Syntax
368 @section i386 Syntactical Considerations
369 @menu
370 * i386-Variations:: AT&T Syntax versus Intel Syntax
371 * i386-Chars:: Special Characters
372 @end menu
373
374 @node i386-Variations
375 @subsection AT&T Syntax versus Intel Syntax
376
377 @cindex i386 intel_syntax pseudo op
378 @cindex intel_syntax pseudo op, i386
379 @cindex i386 att_syntax pseudo op
380 @cindex att_syntax pseudo op, i386
381 @cindex i386 syntax compatibility
382 @cindex syntax compatibility, i386
383 @cindex x86-64 intel_syntax pseudo op
384 @cindex intel_syntax pseudo op, x86-64
385 @cindex x86-64 att_syntax pseudo op
386 @cindex att_syntax pseudo op, x86-64
387 @cindex x86-64 syntax compatibility
388 @cindex syntax compatibility, x86-64
389
390 @code{@value{AS}} now supports assembly using Intel assembler syntax.
391 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
392 back to the usual AT&T mode for compatibility with the output of
393 @code{@value{GCC}}. Either of these directives may have an optional
394 argument, @code{prefix}, or @code{noprefix} specifying whether registers
395 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
396 different from Intel syntax. We mention these differences because
397 almost all 80386 documents use Intel syntax. Notable differences
398 between the two syntaxes are:
399
400 @cindex immediate operands, i386
401 @cindex i386 immediate operands
402 @cindex register operands, i386
403 @cindex i386 register operands
404 @cindex jump/call operands, i386
405 @cindex i386 jump/call operands
406 @cindex operand delimiters, i386
407
408 @cindex immediate operands, x86-64
409 @cindex x86-64 immediate operands
410 @cindex register operands, x86-64
411 @cindex x86-64 register operands
412 @cindex jump/call operands, x86-64
413 @cindex x86-64 jump/call operands
414 @cindex operand delimiters, x86-64
415 @itemize @bullet
416 @item
417 AT&T immediate operands are preceded by @samp{$}; Intel immediate
418 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
419 AT&T register operands are preceded by @samp{%}; Intel register operands
420 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
421 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
422
423 @cindex i386 source, destination operands
424 @cindex source, destination operands; i386
425 @cindex x86-64 source, destination operands
426 @cindex source, destination operands; x86-64
427 @item
428 AT&T and Intel syntax use the opposite order for source and destination
429 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
430 @samp{source, dest} convention is maintained for compatibility with
431 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
432 instructions with 2 immediate operands, such as the @samp{enter}
433 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
434
435 @cindex mnemonic suffixes, i386
436 @cindex sizes operands, i386
437 @cindex i386 size suffixes
438 @cindex mnemonic suffixes, x86-64
439 @cindex sizes operands, x86-64
440 @cindex x86-64 size suffixes
441 @item
442 In AT&T syntax the size of memory operands is determined from the last
443 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
444 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
445 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
446 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
447 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
448 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
449 syntax.
450
451 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
452 instruction with the 64-bit displacement or immediate operand.
453
454 @cindex return instructions, i386
455 @cindex i386 jump, call, return
456 @cindex return instructions, x86-64
457 @cindex x86-64 jump, call, return
458 @item
459 Immediate form long jumps and calls are
460 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
461 Intel syntax is
462 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
463 instruction
464 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
465 @samp{ret far @var{stack-adjust}}.
466
467 @cindex sections, i386
468 @cindex i386 sections
469 @cindex sections, x86-64
470 @cindex x86-64 sections
471 @item
472 The AT&T assembler does not provide support for multiple section
473 programs. Unix style systems expect all programs to be single sections.
474 @end itemize
475
476 @node i386-Chars
477 @subsection Special Characters
478
479 @cindex line comment character, i386
480 @cindex i386 line comment character
481 The presence of a @samp{#} appearing anywhere on a line indicates the
482 start of a comment that extends to the end of that line.
483
484 If a @samp{#} appears as the first character of a line then the whole
485 line is treated as a comment, but in this case the line can also be a
486 logical line number directive (@pxref{Comments}) or a preprocessor
487 control command (@pxref{Preprocessing}).
488
489 If the @option{--divide} command line option has not been specified
490 then the @samp{/} character appearing anywhere on a line also
491 introduces a line comment.
492
493 @cindex line separator, i386
494 @cindex statement separator, i386
495 @cindex i386 line separator
496 The @samp{;} character can be used to separate statements on the same
497 line.
498
499 @node i386-Mnemonics
500 @section i386-Mnemonics
501 @subsection Instruction Naming
502
503 @cindex i386 instruction naming
504 @cindex instruction naming, i386
505 @cindex x86-64 instruction naming
506 @cindex instruction naming, x86-64
507
508 Instruction mnemonics are suffixed with one character modifiers which
509 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
510 and @samp{q} specify byte, word, long and quadruple word operands. If
511 no suffix is specified by an instruction then @code{@value{AS}} tries to
512 fill in the missing suffix based on the destination register operand
513 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
514 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
515 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
516 assembler which assumes that a missing mnemonic suffix implies long
517 operand size. (This incompatibility does not affect compiler output
518 since compilers always explicitly specify the mnemonic suffix.)
519
520 Almost all instructions have the same names in AT&T and Intel format.
521 There are a few exceptions. The sign extend and zero extend
522 instructions need two sizes to specify them. They need a size to
523 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
524 is accomplished by using two instruction mnemonic suffixes in AT&T
525 syntax. Base names for sign extend and zero extend are
526 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
527 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
528 are tacked on to this base name, the @emph{from} suffix before the
529 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
530 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
531 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
532 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
533 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
534 quadruple word).
535
536 @cindex encoding options, i386
537 @cindex encoding options, x86-64
538
539 Different encoding options can be specified via optional mnemonic
540 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
541 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
542 prefers 8bit or 32bit displacement in encoding.
543
544 @cindex conversion instructions, i386
545 @cindex i386 conversion instructions
546 @cindex conversion instructions, x86-64
547 @cindex x86-64 conversion instructions
548 The Intel-syntax conversion instructions
549
550 @itemize @bullet
551 @item
552 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
553
554 @item
555 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
556
557 @item
558 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
559
560 @item
561 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
562
563 @item
564 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
565 (x86-64 only),
566
567 @item
568 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
569 @samp{%rdx:%rax} (x86-64 only),
570 @end itemize
571
572 @noindent
573 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
574 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
575 instructions.
576
577 @cindex jump instructions, i386
578 @cindex call instructions, i386
579 @cindex jump instructions, x86-64
580 @cindex call instructions, x86-64
581 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
582 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
583 convention.
584
585 @subsection AT&T Mnemonic versus Intel Mnemonic
586
587 @cindex i386 mnemonic compatibility
588 @cindex mnemonic compatibility, i386
589
590 @code{@value{AS}} supports assembly using Intel mnemonic.
591 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
592 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
593 syntax for compatibility with the output of @code{@value{GCC}}.
594 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
595 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
596 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
597 assembler with different mnemonics from those in Intel IA32 specification.
598 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
599
600 @node i386-Regs
601 @section Register Naming
602
603 @cindex i386 registers
604 @cindex registers, i386
605 @cindex x86-64 registers
606 @cindex registers, x86-64
607 Register operands are always prefixed with @samp{%}. The 80386 registers
608 consist of
609
610 @itemize @bullet
611 @item
612 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
613 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
614 frame pointer), and @samp{%esp} (the stack pointer).
615
616 @item
617 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
618 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
619
620 @item
621 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
622 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
623 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
624 @samp{%cx}, and @samp{%dx})
625
626 @item
627 the 6 section registers @samp{%cs} (code section), @samp{%ds}
628 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
629 and @samp{%gs}.
630
631 @item
632 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
633 @samp{%cr3}.
634
635 @item
636 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
637 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
638
639 @item
640 the 2 test registers @samp{%tr6} and @samp{%tr7}.
641
642 @item
643 the 8 floating point register stack @samp{%st} or equivalently
644 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
645 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
646 These registers are overloaded by 8 MMX registers @samp{%mm0},
647 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
648 @samp{%mm6} and @samp{%mm7}.
649
650 @item
651 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
652 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
653 @end itemize
654
655 The AMD x86-64 architecture extends the register set by:
656
657 @itemize @bullet
658 @item
659 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
660 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
661 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
662 pointer)
663
664 @item
665 the 8 extended registers @samp{%r8}--@samp{%r15}.
666
667 @item
668 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
669
670 @item
671 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
672
673 @item
674 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
675
676 @item
677 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
678
679 @item
680 the 8 debug registers: @samp{%db8}--@samp{%db15}.
681
682 @item
683 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
684 @end itemize
685
686 @node i386-Prefixes
687 @section Instruction Prefixes
688
689 @cindex i386 instruction prefixes
690 @cindex instruction prefixes, i386
691 @cindex prefixes, i386
692 Instruction prefixes are used to modify the following instruction. They
693 are used to repeat string instructions, to provide section overrides, to
694 perform bus lock operations, and to change operand and address sizes.
695 (Most instructions that normally operate on 32-bit operands will use
696 16-bit operands if the instruction has an ``operand size'' prefix.)
697 Instruction prefixes are best written on the same line as the instruction
698 they act upon. For example, the @samp{scas} (scan string) instruction is
699 repeated with:
700
701 @smallexample
702 repne scas %es:(%edi),%al
703 @end smallexample
704
705 You may also place prefixes on the lines immediately preceding the
706 instruction, but this circumvents checks that @code{@value{AS}} does
707 with prefixes, and will not work with all prefixes.
708
709 Here is a list of instruction prefixes:
710
711 @cindex section override prefixes, i386
712 @itemize @bullet
713 @item
714 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
715 @samp{fs}, @samp{gs}. These are automatically added by specifying
716 using the @var{section}:@var{memory-operand} form for memory references.
717
718 @cindex size prefixes, i386
719 @item
720 Operand/Address size prefixes @samp{data16} and @samp{addr16}
721 change 32-bit operands/addresses into 16-bit operands/addresses,
722 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
723 @code{.code16} section) into 32-bit operands/addresses. These prefixes
724 @emph{must} appear on the same line of code as the instruction they
725 modify. For example, in a 16-bit @code{.code16} section, you might
726 write:
727
728 @smallexample
729 addr32 jmpl *(%ebx)
730 @end smallexample
731
732 @cindex bus lock prefixes, i386
733 @cindex inhibiting interrupts, i386
734 @item
735 The bus lock prefix @samp{lock} inhibits interrupts during execution of
736 the instruction it precedes. (This is only valid with certain
737 instructions; see a 80386 manual for details).
738
739 @cindex coprocessor wait, i386
740 @item
741 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
742 complete the current instruction. This should never be needed for the
743 80386/80387 combination.
744
745 @cindex repeat prefixes, i386
746 @item
747 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
748 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
749 times if the current address size is 16-bits).
750 @cindex REX prefixes, i386
751 @item
752 The @samp{rex} family of prefixes is used by x86-64 to encode
753 extensions to i386 instruction set. The @samp{rex} prefix has four
754 bits --- an operand size overwrite (@code{64}) used to change operand size
755 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
756 register set.
757
758 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
759 instruction emits @samp{rex} prefix with all the bits set. By omitting
760 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
761 prefixes as well. Normally, there is no need to write the prefixes
762 explicitly, since gas will automatically generate them based on the
763 instruction operands.
764 @end itemize
765
766 @node i386-Memory
767 @section Memory References
768
769 @cindex i386 memory references
770 @cindex memory references, i386
771 @cindex x86-64 memory references
772 @cindex memory references, x86-64
773 An Intel syntax indirect memory reference of the form
774
775 @smallexample
776 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
777 @end smallexample
778
779 @noindent
780 is translated into the AT&T syntax
781
782 @smallexample
783 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
784 @end smallexample
785
786 @noindent
787 where @var{base} and @var{index} are the optional 32-bit base and
788 index registers, @var{disp} is the optional displacement, and
789 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
790 to calculate the address of the operand. If no @var{scale} is
791 specified, @var{scale} is taken to be 1. @var{section} specifies the
792 optional section register for the memory operand, and may override the
793 default section register (see a 80386 manual for section register
794 defaults). Note that section overrides in AT&T syntax @emph{must}
795 be preceded by a @samp{%}. If you specify a section override which
796 coincides with the default section register, @code{@value{AS}} does @emph{not}
797 output any section register override prefixes to assemble the given
798 instruction. Thus, section overrides can be specified to emphasize which
799 section register is used for a given memory operand.
800
801 Here are some examples of Intel and AT&T style memory references:
802
803 @table @asis
804 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
805 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
806 missing, and the default section is used (@samp{%ss} for addressing with
807 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
808
809 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
810 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
811 @samp{foo}. All other fields are missing. The section register here
812 defaults to @samp{%ds}.
813
814 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
815 This uses the value pointed to by @samp{foo} as a memory operand.
816 Note that @var{base} and @var{index} are both missing, but there is only
817 @emph{one} @samp{,}. This is a syntactic exception.
818
819 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
820 This selects the contents of the variable @samp{foo} with section
821 register @var{section} being @samp{%gs}.
822 @end table
823
824 Absolute (as opposed to PC relative) call and jump operands must be
825 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
826 always chooses PC relative addressing for jump/call labels.
827
828 Any instruction that has a memory operand, but no register operand,
829 @emph{must} specify its size (byte, word, long, or quadruple) with an
830 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
831 respectively).
832
833 The x86-64 architecture adds an RIP (instruction pointer relative)
834 addressing. This addressing mode is specified by using @samp{rip} as a
835 base register. Only constant offsets are valid. For example:
836
837 @table @asis
838 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
839 Points to the address 1234 bytes past the end of the current
840 instruction.
841
842 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
843 Points to the @code{symbol} in RIP relative way, this is shorter than
844 the default absolute addressing.
845 @end table
846
847 Other addressing modes remain unchanged in x86-64 architecture, except
848 registers used are 64-bit instead of 32-bit.
849
850 @node i386-Jumps
851 @section Handling of Jump Instructions
852
853 @cindex jump optimization, i386
854 @cindex i386 jump optimization
855 @cindex jump optimization, x86-64
856 @cindex x86-64 jump optimization
857 Jump instructions are always optimized to use the smallest possible
858 displacements. This is accomplished by using byte (8-bit) displacement
859 jumps whenever the target is sufficiently close. If a byte displacement
860 is insufficient a long displacement is used. We do not support
861 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
862 instruction with the @samp{data16} instruction prefix), since the 80386
863 insists upon masking @samp{%eip} to 16 bits after the word displacement
864 is added. (See also @pxref{i386-Arch})
865
866 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
867 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
868 displacements, so that if you use these instructions (@code{@value{GCC}} does
869 not use them) you may get an error message (and incorrect code). The AT&T
870 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
871 to
872
873 @smallexample
874 jcxz cx_zero
875 jmp cx_nonzero
876 cx_zero: jmp foo
877 cx_nonzero:
878 @end smallexample
879
880 @node i386-Float
881 @section Floating Point
882
883 @cindex i386 floating point
884 @cindex floating point, i386
885 @cindex x86-64 floating point
886 @cindex floating point, x86-64
887 All 80387 floating point types except packed BCD are supported.
888 (BCD support may be added without much difficulty). These data
889 types are 16-, 32-, and 64- bit integers, and single (32-bit),
890 double (64-bit), and extended (80-bit) precision floating point.
891 Each supported type has an instruction mnemonic suffix and a constructor
892 associated with it. Instruction mnemonic suffixes specify the operand's
893 data type. Constructors build these data types into memory.
894
895 @cindex @code{float} directive, i386
896 @cindex @code{single} directive, i386
897 @cindex @code{double} directive, i386
898 @cindex @code{tfloat} directive, i386
899 @cindex @code{float} directive, x86-64
900 @cindex @code{single} directive, x86-64
901 @cindex @code{double} directive, x86-64
902 @cindex @code{tfloat} directive, x86-64
903 @itemize @bullet
904 @item
905 Floating point constructors are @samp{.float} or @samp{.single},
906 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
907 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
908 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
909 only supports this format via the @samp{fldt} (load 80-bit real to stack
910 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
911
912 @cindex @code{word} directive, i386
913 @cindex @code{long} directive, i386
914 @cindex @code{int} directive, i386
915 @cindex @code{quad} directive, i386
916 @cindex @code{word} directive, x86-64
917 @cindex @code{long} directive, x86-64
918 @cindex @code{int} directive, x86-64
919 @cindex @code{quad} directive, x86-64
920 @item
921 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
922 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
923 corresponding instruction mnemonic suffixes are @samp{s} (single),
924 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
925 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
926 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
927 stack) instructions.
928 @end itemize
929
930 Register to register operations should not use instruction mnemonic suffixes.
931 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
932 wrote @samp{fst %st, %st(1)}, since all register to register operations
933 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
934 which converts @samp{%st} from 80-bit to 64-bit floating point format,
935 then stores the result in the 4 byte location @samp{mem})
936
937 @node i386-SIMD
938 @section Intel's MMX and AMD's 3DNow! SIMD Operations
939
940 @cindex MMX, i386
941 @cindex 3DNow!, i386
942 @cindex SIMD, i386
943 @cindex MMX, x86-64
944 @cindex 3DNow!, x86-64
945 @cindex SIMD, x86-64
946
947 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
948 instructions for integer data), available on Intel's Pentium MMX
949 processors and Pentium II processors, AMD's K6 and K6-2 processors,
950 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
951 instruction set (SIMD instructions for 32-bit floating point data)
952 available on AMD's K6-2 processor and possibly others in the future.
953
954 Currently, @code{@value{AS}} does not support Intel's floating point
955 SIMD, Katmai (KNI).
956
957 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
958 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
959 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
960 floating point values. The MMX registers cannot be used at the same time
961 as the floating point stack.
962
963 See Intel and AMD documentation, keeping in mind that the operand order in
964 instructions is reversed from the Intel syntax.
965
966 @node i386-LWP
967 @section AMD's Lightweight Profiling Instructions
968
969 @cindex LWP, i386
970 @cindex LWP, x86-64
971
972 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
973 instruction set, available on AMD's Family 15h (Orochi) processors.
974
975 LWP enables applications to collect and manage performance data, and
976 react to performance events. The collection of performance data
977 requires no context switches. LWP runs in the context of a thread and
978 so several counters can be used independently across multiple threads.
979 LWP can be used in both 64-bit and legacy 32-bit modes.
980
981 For detailed information on the LWP instruction set, see the
982 @cite{AMD Lightweight Profiling Specification} available at
983 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
984
985 @node i386-BMI
986 @section Bit Manipulation Instructions
987
988 @cindex BMI, i386
989 @cindex BMI, x86-64
990
991 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
992
993 BMI instructions provide several instructions implementing individual
994 bit manipulation operations such as isolation, masking, setting, or
995 resetting.
996
997 @c Need to add a specification citation here when available.
998
999 @node i386-TBM
1000 @section AMD's Trailing Bit Manipulation Instructions
1001
1002 @cindex TBM, i386
1003 @cindex TBM, x86-64
1004
1005 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1006 instruction set, available on AMD's BDVER2 processors (Trinity and
1007 Viperfish).
1008
1009 TBM instructions provide instructions implementing individual bit
1010 manipulation operations such as isolating, masking, setting, resetting,
1011 complementing, and operations on trailing zeros and ones.
1012
1013 @c Need to add a specification citation here when available.
1014
1015 @node i386-16bit
1016 @section Writing 16-bit Code
1017
1018 @cindex i386 16-bit code
1019 @cindex 16-bit code, i386
1020 @cindex real-mode code, i386
1021 @cindex @code{code16gcc} directive, i386
1022 @cindex @code{code16} directive, i386
1023 @cindex @code{code32} directive, i386
1024 @cindex @code{code64} directive, i386
1025 @cindex @code{code64} directive, x86-64
1026 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1027 or 64-bit x86-64 code depending on the default configuration,
1028 it also supports writing code to run in real mode or in 16-bit protected
1029 mode code segments. To do this, put a @samp{.code16} or
1030 @samp{.code16gcc} directive before the assembly language instructions to
1031 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1032 32-bit code with the @samp{.code32} directive or 64-bit code with the
1033 @samp{.code64} directive.
1034
1035 @samp{.code16gcc} provides experimental support for generating 16-bit
1036 code from gcc, and differs from @samp{.code16} in that @samp{call},
1037 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1038 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1039 default to 32-bit size. This is so that the stack pointer is
1040 manipulated in the same way over function calls, allowing access to
1041 function parameters at the same stack offsets as in 32-bit mode.
1042 @samp{.code16gcc} also automatically adds address size prefixes where
1043 necessary to use the 32-bit addressing modes that gcc generates.
1044
1045 The code which @code{@value{AS}} generates in 16-bit mode will not
1046 necessarily run on a 16-bit pre-80386 processor. To write code that
1047 runs on such a processor, you must refrain from using @emph{any} 32-bit
1048 constructs which require @code{@value{AS}} to output address or operand
1049 size prefixes.
1050
1051 Note that writing 16-bit code instructions by explicitly specifying a
1052 prefix or an instruction mnemonic suffix within a 32-bit code section
1053 generates different machine instructions than those generated for a
1054 16-bit code segment. In a 32-bit code section, the following code
1055 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1056 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1057
1058 @smallexample
1059 pushw $4
1060 @end smallexample
1061
1062 The same code in a 16-bit code section would generate the machine
1063 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1064 is correct since the processor default operand size is assumed to be 16
1065 bits in a 16-bit code section.
1066
1067 @node i386-Arch
1068 @section Specifying CPU Architecture
1069
1070 @cindex arch directive, i386
1071 @cindex i386 arch directive
1072 @cindex arch directive, x86-64
1073 @cindex x86-64 arch directive
1074
1075 @code{@value{AS}} may be told to assemble for a particular CPU
1076 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1077 directive enables a warning when gas detects an instruction that is not
1078 supported on the CPU specified. The choices for @var{cpu_type} are:
1079
1080 @multitable @columnfractions .20 .20 .20 .20
1081 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1082 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1083 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1084 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1085 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1086 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1087 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1088 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1089 @item @samp{generic32} @tab @samp{generic64}
1090 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1091 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1092 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1093 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1094 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1095 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1096 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1097 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1098 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1099 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1100 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1101 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1102 @item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit}
1103 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1104 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1105 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1106 @item @samp{.padlock} @tab @samp{.clzero}
1107 @end multitable
1108
1109 Apart from the warning, there are only two other effects on
1110 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1111 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1112 will automatically use a two byte opcode sequence. The larger three
1113 byte opcode sequence is used on the 486 (and when no architecture is
1114 specified) because it executes faster on the 486. Note that you can
1115 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1116 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1117 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1118 conditional jumps will be promoted when necessary to a two instruction
1119 sequence consisting of a conditional jump of the opposite sense around
1120 an unconditional jump to the target.
1121
1122 Following the CPU architecture (but not a sub-architecture, which are those
1123 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1124 control automatic promotion of conditional jumps. @samp{jumps} is the
1125 default, and enables jump promotion; All external jumps will be of the long
1126 variety, and file-local jumps will be promoted as necessary.
1127 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1128 byte offset jumps, and warns about file-local conditional jumps that
1129 @code{@value{AS}} promotes.
1130 Unconditional jumps are treated as for @samp{jumps}.
1131
1132 For example
1133
1134 @smallexample
1135 .arch i8086,nojumps
1136 @end smallexample
1137
1138 @node i386-Bugs
1139 @section AT&T Syntax bugs
1140
1141 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1142 assemblers, generate floating point instructions with reversed source
1143 and destination registers in certain cases. Unfortunately, gcc and
1144 possibly many other programs use this reversed syntax, so we're stuck
1145 with it.
1146
1147 For example
1148
1149 @smallexample
1150 fsub %st,%st(3)
1151 @end smallexample
1152 @noindent
1153 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1154 than the expected @samp{%st(3) - %st}. This happens with all the
1155 non-commutative arithmetic floating point operations with two register
1156 operands where the source register is @samp{%st} and the destination
1157 register is @samp{%st(i)}.
1158
1159 @node i386-Notes
1160 @section Notes
1161
1162 @cindex i386 @code{mul}, @code{imul} instructions
1163 @cindex @code{mul} instruction, i386
1164 @cindex @code{imul} instruction, i386
1165 @cindex @code{mul} instruction, x86-64
1166 @cindex @code{imul} instruction, x86-64
1167 There is some trickery concerning the @samp{mul} and @samp{imul}
1168 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1169 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1170 for @samp{imul}) can be output only in the one operand form. Thus,
1171 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1172 the expanding multiply would clobber the @samp{%edx} register, and this
1173 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1174 64-bit product in @samp{%edx:%eax}.
1175
1176 We have added a two operand form of @samp{imul} when the first operand
1177 is an immediate mode expression and the second operand is a register.
1178 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1179 example, can be done with @samp{imul $69, %eax} rather than @samp{imul
1180 $69, %eax, %eax}.
1181
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