Add AMD btver1 and btver2 support
[deliverable/binutils-gdb.git] / gas / doc / c-i386.texi
1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
2 @c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
6 @c man end
7
8 @ifset GENERIC
9 @page
10 @node i386-Dependent
11 @chapter 80386 Dependent Features
12 @end ifset
13 @ifclear GENERIC
14 @node Machine Dependencies
15 @chapter 80386 Dependent Features
16 @end ifclear
17
18 @cindex i386 support
19 @cindex i80386 support
20 @cindex x86-64 support
21
22 The i386 version @code{@value{AS}} supports both the original Intel 386
23 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
24 extending the Intel architecture to 64-bits.
25
26 @menu
27 * i386-Options:: Options
28 * i386-Directives:: X86 specific directives
29 * i386-Syntax:: Syntactical considerations
30 * i386-Mnemonics:: Instruction Naming
31 * i386-Regs:: Register Naming
32 * i386-Prefixes:: Instruction Prefixes
33 * i386-Memory:: Memory References
34 * i386-Jumps:: Handling of Jump Instructions
35 * i386-Float:: Floating Point
36 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
37 * i386-LWP:: AMD's Lightweight Profiling Instructions
38 * i386-BMI:: Bit Manipulation Instruction
39 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
40 * i386-16bit:: Writing 16-bit Code
41 * i386-Arch:: Specifying an x86 CPU architecture
42 * i386-Bugs:: AT&T Syntax bugs
43 * i386-Notes:: Notes
44 @end menu
45
46 @node i386-Options
47 @section Options
48
49 @cindex options for i386
50 @cindex options for x86-64
51 @cindex i386 options
52 @cindex x86-64 options
53
54 The i386 version of @code{@value{AS}} has a few machine
55 dependent options:
56
57 @c man begin OPTIONS
58 @table @gcctabopt
59 @cindex @samp{--32} option, i386
60 @cindex @samp{--32} option, x86-64
61 @cindex @samp{--x32} option, i386
62 @cindex @samp{--x32} option, x86-64
63 @cindex @samp{--64} option, i386
64 @cindex @samp{--64} option, x86-64
65 @item --32 | --x32 | --64
66 Select the word size, either 32 bits or 64 bits. @samp{--32}
67 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
68 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 respectively.
70
71 These options are only available with the ELF object file format, and
72 require that the necessary BFD support has been included (on a 32-bit
73 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
74 usage and use x86-64 as target platform).
75
76 @item -n
77 By default, x86 GAS replaces multiple nop instructions used for
78 alignment within code sections with multi-byte nop instructions such
79 as leal 0(%esi,1),%esi. This switch disables the optimization.
80
81 @cindex @samp{--divide} option, i386
82 @item --divide
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
88
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
96 @code{i8086},
97 @code{i186},
98 @code{i286},
99 @code{i386},
100 @code{i486},
101 @code{i586},
102 @code{i686},
103 @code{pentium},
104 @code{pentiumpro},
105 @code{pentiumii},
106 @code{pentiumiii},
107 @code{pentium4},
108 @code{prescott},
109 @code{nocona},
110 @code{core},
111 @code{core2},
112 @code{corei7},
113 @code{l1om},
114 @code{k1om},
115 @code{k6},
116 @code{k6_2},
117 @code{athlon},
118 @code{opteron},
119 @code{k8},
120 @code{amdfam10},
121 @code{bdver1},
122 @code{bdver2},
123 @code{btver1},
124 @code{btver2},
125 @code{generic32} and
126 @code{generic64}.
127
128 In addition to the basic instruction set, the assembler can be told to
129 accept various extension mnemonics. For example,
130 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
131 @var{vmx}. The following extensions are currently supported:
132 @code{8087},
133 @code{287},
134 @code{387},
135 @code{no87},
136 @code{mmx},
137 @code{nommx},
138 @code{sse},
139 @code{sse2},
140 @code{sse3},
141 @code{ssse3},
142 @code{sse4.1},
143 @code{sse4.2},
144 @code{sse4},
145 @code{nosse},
146 @code{avx},
147 @code{avx2},
148 @code{adx},
149 @code{rdseed},
150 @code{prfchw},
151 @code{noavx},
152 @code{vmx},
153 @code{vmfunc},
154 @code{smx},
155 @code{xsave},
156 @code{xsaveopt},
157 @code{aes},
158 @code{pclmul},
159 @code{fsgsbase},
160 @code{rdrnd},
161 @code{f16c},
162 @code{bmi2},
163 @code{fma},
164 @code{movbe},
165 @code{ept},
166 @code{lzcnt},
167 @code{hle},
168 @code{rtm},
169 @code{invpcid},
170 @code{clflush},
171 @code{lwp},
172 @code{fma4},
173 @code{xop},
174 @code{syscall},
175 @code{rdtscp},
176 @code{3dnow},
177 @code{3dnowa},
178 @code{sse4a},
179 @code{sse5},
180 @code{svme},
181 @code{abm} and
182 @code{padlock}.
183 Note that rather than extending a basic instruction set, the extension
184 mnemonics starting with @code{no} revoke the respective functionality.
185
186 When the @code{.arch} directive is used with @option{-march}, the
187 @code{.arch} directive will take precedent.
188
189 @cindex @samp{-mtune=} option, i386
190 @cindex @samp{-mtune=} option, x86-64
191 @item -mtune=@var{CPU}
192 This option specifies a processor to optimize for. When used in
193 conjunction with the @option{-march} option, only instructions
194 of the processor specified by the @option{-march} option will be
195 generated.
196
197 Valid @var{CPU} values are identical to the processor list of
198 @option{-march=@var{CPU}}.
199
200 @cindex @samp{-msse2avx} option, i386
201 @cindex @samp{-msse2avx} option, x86-64
202 @item -msse2avx
203 This option specifies that the assembler should encode SSE instructions
204 with VEX prefix.
205
206 @cindex @samp{-msse-check=} option, i386
207 @cindex @samp{-msse-check=} option, x86-64
208 @item -msse-check=@var{none}
209 @itemx -msse-check=@var{warning}
210 @itemx -msse-check=@var{error}
211 These options control if the assembler should check SSE intructions.
212 @option{-msse-check=@var{none}} will make the assembler not to check SSE
213 instructions, which is the default. @option{-msse-check=@var{warning}}
214 will make the assembler issue a warning for any SSE intruction.
215 @option{-msse-check=@var{error}} will make the assembler issue an error
216 for any SSE intruction.
217
218 @cindex @samp{-mavxscalar=} option, i386
219 @cindex @samp{-mavxscalar=} option, x86-64
220 @item -mavxscalar=@var{128}
221 @itemx -mavxscalar=@var{256}
222 These options control how the assembler should encode scalar AVX
223 instructions. @option{-mavxscalar=@var{128}} will encode scalar
224 AVX instructions with 128bit vector length, which is the default.
225 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
226 with 256bit vector length.
227
228 @cindex @samp{-mmnemonic=} option, i386
229 @cindex @samp{-mmnemonic=} option, x86-64
230 @item -mmnemonic=@var{att}
231 @itemx -mmnemonic=@var{intel}
232 This option specifies instruction mnemonic for matching instructions.
233 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
234 take precedent.
235
236 @cindex @samp{-msyntax=} option, i386
237 @cindex @samp{-msyntax=} option, x86-64
238 @item -msyntax=@var{att}
239 @itemx -msyntax=@var{intel}
240 This option specifies instruction syntax when processing instructions.
241 The @code{.att_syntax} and @code{.intel_syntax} directives will
242 take precedent.
243
244 @cindex @samp{-mnaked-reg} option, i386
245 @cindex @samp{-mnaked-reg} option, x86-64
246 @item -mnaked-reg
247 This opetion specifies that registers don't require a @samp{%} prefix.
248 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
249
250 @end table
251 @c man end
252
253 @node i386-Directives
254 @section x86 specific Directives
255
256 @cindex machine directives, x86
257 @cindex x86 machine directives
258 @table @code
259
260 @cindex @code{lcomm} directive, COFF
261 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
262 Reserve @var{length} (an absolute expression) bytes for a local common
263 denoted by @var{symbol}. The section and value of @var{symbol} are
264 those of the new local common. The addresses are allocated in the bss
265 section, so that at run-time the bytes start off zeroed. Since
266 @var{symbol} is not declared global, it is normally not visible to
267 @code{@value{LD}}. The optional third parameter, @var{alignment},
268 specifies the desired alignment of the symbol in the bss section.
269
270 This directive is only available for COFF based x86 targets.
271
272 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
273 @c .largecomm
274
275 @end table
276
277 @node i386-Syntax
278 @section i386 Syntactical Considerations
279 @menu
280 * i386-Variations:: AT&T Syntax versus Intel Syntax
281 * i386-Chars:: Special Characters
282 @end menu
283
284 @node i386-Variations
285 @subsection AT&T Syntax versus Intel Syntax
286
287 @cindex i386 intel_syntax pseudo op
288 @cindex intel_syntax pseudo op, i386
289 @cindex i386 att_syntax pseudo op
290 @cindex att_syntax pseudo op, i386
291 @cindex i386 syntax compatibility
292 @cindex syntax compatibility, i386
293 @cindex x86-64 intel_syntax pseudo op
294 @cindex intel_syntax pseudo op, x86-64
295 @cindex x86-64 att_syntax pseudo op
296 @cindex att_syntax pseudo op, x86-64
297 @cindex x86-64 syntax compatibility
298 @cindex syntax compatibility, x86-64
299
300 @code{@value{AS}} now supports assembly using Intel assembler syntax.
301 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
302 back to the usual AT&T mode for compatibility with the output of
303 @code{@value{GCC}}. Either of these directives may have an optional
304 argument, @code{prefix}, or @code{noprefix} specifying whether registers
305 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
306 different from Intel syntax. We mention these differences because
307 almost all 80386 documents use Intel syntax. Notable differences
308 between the two syntaxes are:
309
310 @cindex immediate operands, i386
311 @cindex i386 immediate operands
312 @cindex register operands, i386
313 @cindex i386 register operands
314 @cindex jump/call operands, i386
315 @cindex i386 jump/call operands
316 @cindex operand delimiters, i386
317
318 @cindex immediate operands, x86-64
319 @cindex x86-64 immediate operands
320 @cindex register operands, x86-64
321 @cindex x86-64 register operands
322 @cindex jump/call operands, x86-64
323 @cindex x86-64 jump/call operands
324 @cindex operand delimiters, x86-64
325 @itemize @bullet
326 @item
327 AT&T immediate operands are preceded by @samp{$}; Intel immediate
328 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
329 AT&T register operands are preceded by @samp{%}; Intel register operands
330 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
331 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
332
333 @cindex i386 source, destination operands
334 @cindex source, destination operands; i386
335 @cindex x86-64 source, destination operands
336 @cindex source, destination operands; x86-64
337 @item
338 AT&T and Intel syntax use the opposite order for source and destination
339 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
340 @samp{source, dest} convention is maintained for compatibility with
341 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
342 instructions with 2 immediate operands, such as the @samp{enter}
343 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
344
345 @cindex mnemonic suffixes, i386
346 @cindex sizes operands, i386
347 @cindex i386 size suffixes
348 @cindex mnemonic suffixes, x86-64
349 @cindex sizes operands, x86-64
350 @cindex x86-64 size suffixes
351 @item
352 In AT&T syntax the size of memory operands is determined from the last
353 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
354 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
355 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
356 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
357 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
358 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
359 syntax.
360
361 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
362 instruction with the 64-bit displacement or immediate operand.
363
364 @cindex return instructions, i386
365 @cindex i386 jump, call, return
366 @cindex return instructions, x86-64
367 @cindex x86-64 jump, call, return
368 @item
369 Immediate form long jumps and calls are
370 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
371 Intel syntax is
372 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
373 instruction
374 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
375 @samp{ret far @var{stack-adjust}}.
376
377 @cindex sections, i386
378 @cindex i386 sections
379 @cindex sections, x86-64
380 @cindex x86-64 sections
381 @item
382 The AT&T assembler does not provide support for multiple section
383 programs. Unix style systems expect all programs to be single sections.
384 @end itemize
385
386 @node i386-Chars
387 @subsection Special Characters
388
389 @cindex line comment character, i386
390 @cindex i386 line comment character
391 The presence of a @samp{#} appearing anywhere on a line indicates the
392 start of a comment that extends to the end of that line.
393
394 If a @samp{#} appears as the first character of a line then the whole
395 line is treated as a comment, but in this case the line can also be a
396 logical line number directive (@pxref{Comments}) or a preprocessor
397 control command (@pxref{Preprocessing}).
398
399 If the @option{--divide} command line option has not been specified
400 then the @samp{/} character appearing anywhere on a line also
401 introduces a line comment.
402
403 @cindex line separator, i386
404 @cindex statement separator, i386
405 @cindex i386 line separator
406 The @samp{;} character can be used to separate statements on the same
407 line.
408
409 @node i386-Mnemonics
410 @section Instruction Naming
411
412 @cindex i386 instruction naming
413 @cindex instruction naming, i386
414 @cindex x86-64 instruction naming
415 @cindex instruction naming, x86-64
416
417 Instruction mnemonics are suffixed with one character modifiers which
418 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
419 and @samp{q} specify byte, word, long and quadruple word operands. If
420 no suffix is specified by an instruction then @code{@value{AS}} tries to
421 fill in the missing suffix based on the destination register operand
422 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
423 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
424 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
425 assembler which assumes that a missing mnemonic suffix implies long
426 operand size. (This incompatibility does not affect compiler output
427 since compilers always explicitly specify the mnemonic suffix.)
428
429 Almost all instructions have the same names in AT&T and Intel format.
430 There are a few exceptions. The sign extend and zero extend
431 instructions need two sizes to specify them. They need a size to
432 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
433 is accomplished by using two instruction mnemonic suffixes in AT&T
434 syntax. Base names for sign extend and zero extend are
435 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
436 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
437 are tacked on to this base name, the @emph{from} suffix before the
438 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
439 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
440 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
441 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
442 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
443 quadruple word).
444
445 @cindex encoding options, i386
446 @cindex encoding options, x86-64
447
448 Different encoding options can be specified via optional mnemonic
449 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
450 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
451 prefers 8bit or 32bit displacement in encoding.
452
453 @cindex conversion instructions, i386
454 @cindex i386 conversion instructions
455 @cindex conversion instructions, x86-64
456 @cindex x86-64 conversion instructions
457 The Intel-syntax conversion instructions
458
459 @itemize @bullet
460 @item
461 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
462
463 @item
464 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
465
466 @item
467 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
468
469 @item
470 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
471
472 @item
473 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
474 (x86-64 only),
475
476 @item
477 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
478 @samp{%rdx:%rax} (x86-64 only),
479 @end itemize
480
481 @noindent
482 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
483 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
484 instructions.
485
486 @cindex jump instructions, i386
487 @cindex call instructions, i386
488 @cindex jump instructions, x86-64
489 @cindex call instructions, x86-64
490 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
491 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
492 convention.
493
494 @section AT&T Mnemonic versus Intel Mnemonic
495
496 @cindex i386 mnemonic compatibility
497 @cindex mnemonic compatibility, i386
498
499 @code{@value{AS}} supports assembly using Intel mnemonic.
500 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
501 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
502 syntax for compatibility with the output of @code{@value{GCC}}.
503 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
504 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
505 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
506 assembler with different mnemonics from those in Intel IA32 specification.
507 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
508
509 @node i386-Regs
510 @section Register Naming
511
512 @cindex i386 registers
513 @cindex registers, i386
514 @cindex x86-64 registers
515 @cindex registers, x86-64
516 Register operands are always prefixed with @samp{%}. The 80386 registers
517 consist of
518
519 @itemize @bullet
520 @item
521 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
522 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
523 frame pointer), and @samp{%esp} (the stack pointer).
524
525 @item
526 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
527 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
528
529 @item
530 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
531 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
532 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
533 @samp{%cx}, and @samp{%dx})
534
535 @item
536 the 6 section registers @samp{%cs} (code section), @samp{%ds}
537 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
538 and @samp{%gs}.
539
540 @item
541 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
542 @samp{%cr3}.
543
544 @item
545 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
546 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
547
548 @item
549 the 2 test registers @samp{%tr6} and @samp{%tr7}.
550
551 @item
552 the 8 floating point register stack @samp{%st} or equivalently
553 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
554 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
555 These registers are overloaded by 8 MMX registers @samp{%mm0},
556 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
557 @samp{%mm6} and @samp{%mm7}.
558
559 @item
560 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
561 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
562 @end itemize
563
564 The AMD x86-64 architecture extends the register set by:
565
566 @itemize @bullet
567 @item
568 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
569 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
570 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
571 pointer)
572
573 @item
574 the 8 extended registers @samp{%r8}--@samp{%r15}.
575
576 @item
577 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
578
579 @item
580 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
581
582 @item
583 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
584
585 @item
586 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
587
588 @item
589 the 8 debug registers: @samp{%db8}--@samp{%db15}.
590
591 @item
592 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
593 @end itemize
594
595 @node i386-Prefixes
596 @section Instruction Prefixes
597
598 @cindex i386 instruction prefixes
599 @cindex instruction prefixes, i386
600 @cindex prefixes, i386
601 Instruction prefixes are used to modify the following instruction. They
602 are used to repeat string instructions, to provide section overrides, to
603 perform bus lock operations, and to change operand and address sizes.
604 (Most instructions that normally operate on 32-bit operands will use
605 16-bit operands if the instruction has an ``operand size'' prefix.)
606 Instruction prefixes are best written on the same line as the instruction
607 they act upon. For example, the @samp{scas} (scan string) instruction is
608 repeated with:
609
610 @smallexample
611 repne scas %es:(%edi),%al
612 @end smallexample
613
614 You may also place prefixes on the lines immediately preceding the
615 instruction, but this circumvents checks that @code{@value{AS}} does
616 with prefixes, and will not work with all prefixes.
617
618 Here is a list of instruction prefixes:
619
620 @cindex section override prefixes, i386
621 @itemize @bullet
622 @item
623 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
624 @samp{fs}, @samp{gs}. These are automatically added by specifying
625 using the @var{section}:@var{memory-operand} form for memory references.
626
627 @cindex size prefixes, i386
628 @item
629 Operand/Address size prefixes @samp{data16} and @samp{addr16}
630 change 32-bit operands/addresses into 16-bit operands/addresses,
631 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
632 @code{.code16} section) into 32-bit operands/addresses. These prefixes
633 @emph{must} appear on the same line of code as the instruction they
634 modify. For example, in a 16-bit @code{.code16} section, you might
635 write:
636
637 @smallexample
638 addr32 jmpl *(%ebx)
639 @end smallexample
640
641 @cindex bus lock prefixes, i386
642 @cindex inhibiting interrupts, i386
643 @item
644 The bus lock prefix @samp{lock} inhibits interrupts during execution of
645 the instruction it precedes. (This is only valid with certain
646 instructions; see a 80386 manual for details).
647
648 @cindex coprocessor wait, i386
649 @item
650 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
651 complete the current instruction. This should never be needed for the
652 80386/80387 combination.
653
654 @cindex repeat prefixes, i386
655 @item
656 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
657 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
658 times if the current address size is 16-bits).
659 @cindex REX prefixes, i386
660 @item
661 The @samp{rex} family of prefixes is used by x86-64 to encode
662 extensions to i386 instruction set. The @samp{rex} prefix has four
663 bits --- an operand size overwrite (@code{64}) used to change operand size
664 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
665 register set.
666
667 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
668 instruction emits @samp{rex} prefix with all the bits set. By omitting
669 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
670 prefixes as well. Normally, there is no need to write the prefixes
671 explicitly, since gas will automatically generate them based on the
672 instruction operands.
673 @end itemize
674
675 @node i386-Memory
676 @section Memory References
677
678 @cindex i386 memory references
679 @cindex memory references, i386
680 @cindex x86-64 memory references
681 @cindex memory references, x86-64
682 An Intel syntax indirect memory reference of the form
683
684 @smallexample
685 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
686 @end smallexample
687
688 @noindent
689 is translated into the AT&T syntax
690
691 @smallexample
692 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
693 @end smallexample
694
695 @noindent
696 where @var{base} and @var{index} are the optional 32-bit base and
697 index registers, @var{disp} is the optional displacement, and
698 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
699 to calculate the address of the operand. If no @var{scale} is
700 specified, @var{scale} is taken to be 1. @var{section} specifies the
701 optional section register for the memory operand, and may override the
702 default section register (see a 80386 manual for section register
703 defaults). Note that section overrides in AT&T syntax @emph{must}
704 be preceded by a @samp{%}. If you specify a section override which
705 coincides with the default section register, @code{@value{AS}} does @emph{not}
706 output any section register override prefixes to assemble the given
707 instruction. Thus, section overrides can be specified to emphasize which
708 section register is used for a given memory operand.
709
710 Here are some examples of Intel and AT&T style memory references:
711
712 @table @asis
713 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
714 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
715 missing, and the default section is used (@samp{%ss} for addressing with
716 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
717
718 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
719 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
720 @samp{foo}. All other fields are missing. The section register here
721 defaults to @samp{%ds}.
722
723 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
724 This uses the value pointed to by @samp{foo} as a memory operand.
725 Note that @var{base} and @var{index} are both missing, but there is only
726 @emph{one} @samp{,}. This is a syntactic exception.
727
728 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
729 This selects the contents of the variable @samp{foo} with section
730 register @var{section} being @samp{%gs}.
731 @end table
732
733 Absolute (as opposed to PC relative) call and jump operands must be
734 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
735 always chooses PC relative addressing for jump/call labels.
736
737 Any instruction that has a memory operand, but no register operand,
738 @emph{must} specify its size (byte, word, long, or quadruple) with an
739 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
740 respectively).
741
742 The x86-64 architecture adds an RIP (instruction pointer relative)
743 addressing. This addressing mode is specified by using @samp{rip} as a
744 base register. Only constant offsets are valid. For example:
745
746 @table @asis
747 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
748 Points to the address 1234 bytes past the end of the current
749 instruction.
750
751 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
752 Points to the @code{symbol} in RIP relative way, this is shorter than
753 the default absolute addressing.
754 @end table
755
756 Other addressing modes remain unchanged in x86-64 architecture, except
757 registers used are 64-bit instead of 32-bit.
758
759 @node i386-Jumps
760 @section Handling of Jump Instructions
761
762 @cindex jump optimization, i386
763 @cindex i386 jump optimization
764 @cindex jump optimization, x86-64
765 @cindex x86-64 jump optimization
766 Jump instructions are always optimized to use the smallest possible
767 displacements. This is accomplished by using byte (8-bit) displacement
768 jumps whenever the target is sufficiently close. If a byte displacement
769 is insufficient a long displacement is used. We do not support
770 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
771 instruction with the @samp{data16} instruction prefix), since the 80386
772 insists upon masking @samp{%eip} to 16 bits after the word displacement
773 is added. (See also @pxref{i386-Arch})
774
775 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
776 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
777 displacements, so that if you use these instructions (@code{@value{GCC}} does
778 not use them) you may get an error message (and incorrect code). The AT&T
779 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
780 to
781
782 @smallexample
783 jcxz cx_zero
784 jmp cx_nonzero
785 cx_zero: jmp foo
786 cx_nonzero:
787 @end smallexample
788
789 @node i386-Float
790 @section Floating Point
791
792 @cindex i386 floating point
793 @cindex floating point, i386
794 @cindex x86-64 floating point
795 @cindex floating point, x86-64
796 All 80387 floating point types except packed BCD are supported.
797 (BCD support may be added without much difficulty). These data
798 types are 16-, 32-, and 64- bit integers, and single (32-bit),
799 double (64-bit), and extended (80-bit) precision floating point.
800 Each supported type has an instruction mnemonic suffix and a constructor
801 associated with it. Instruction mnemonic suffixes specify the operand's
802 data type. Constructors build these data types into memory.
803
804 @cindex @code{float} directive, i386
805 @cindex @code{single} directive, i386
806 @cindex @code{double} directive, i386
807 @cindex @code{tfloat} directive, i386
808 @cindex @code{float} directive, x86-64
809 @cindex @code{single} directive, x86-64
810 @cindex @code{double} directive, x86-64
811 @cindex @code{tfloat} directive, x86-64
812 @itemize @bullet
813 @item
814 Floating point constructors are @samp{.float} or @samp{.single},
815 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
816 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
817 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
818 only supports this format via the @samp{fldt} (load 80-bit real to stack
819 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
820
821 @cindex @code{word} directive, i386
822 @cindex @code{long} directive, i386
823 @cindex @code{int} directive, i386
824 @cindex @code{quad} directive, i386
825 @cindex @code{word} directive, x86-64
826 @cindex @code{long} directive, x86-64
827 @cindex @code{int} directive, x86-64
828 @cindex @code{quad} directive, x86-64
829 @item
830 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
831 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
832 corresponding instruction mnemonic suffixes are @samp{s} (single),
833 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
834 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
835 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
836 stack) instructions.
837 @end itemize
838
839 Register to register operations should not use instruction mnemonic suffixes.
840 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
841 wrote @samp{fst %st, %st(1)}, since all register to register operations
842 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
843 which converts @samp{%st} from 80-bit to 64-bit floating point format,
844 then stores the result in the 4 byte location @samp{mem})
845
846 @node i386-SIMD
847 @section Intel's MMX and AMD's 3DNow! SIMD Operations
848
849 @cindex MMX, i386
850 @cindex 3DNow!, i386
851 @cindex SIMD, i386
852 @cindex MMX, x86-64
853 @cindex 3DNow!, x86-64
854 @cindex SIMD, x86-64
855
856 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
857 instructions for integer data), available on Intel's Pentium MMX
858 processors and Pentium II processors, AMD's K6 and K6-2 processors,
859 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
860 instruction set (SIMD instructions for 32-bit floating point data)
861 available on AMD's K6-2 processor and possibly others in the future.
862
863 Currently, @code{@value{AS}} does not support Intel's floating point
864 SIMD, Katmai (KNI).
865
866 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
867 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
868 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
869 floating point values. The MMX registers cannot be used at the same time
870 as the floating point stack.
871
872 See Intel and AMD documentation, keeping in mind that the operand order in
873 instructions is reversed from the Intel syntax.
874
875 @node i386-LWP
876 @section AMD's Lightweight Profiling Instructions
877
878 @cindex LWP, i386
879 @cindex LWP, x86-64
880
881 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
882 instruction set, available on AMD's Family 15h (Orochi) processors.
883
884 LWP enables applications to collect and manage performance data, and
885 react to performance events. The collection of performance data
886 requires no context switches. LWP runs in the context of a thread and
887 so several counters can be used independently across multiple threads.
888 LWP can be used in both 64-bit and legacy 32-bit modes.
889
890 For detailed information on the LWP instruction set, see the
891 @cite{AMD Lightweight Profiling Specification} available at
892 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
893
894 @node i386-BMI
895 @section Bit Manipulation Instructions
896
897 @cindex BMI, i386
898 @cindex BMI, x86-64
899
900 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
901
902 BMI instructions provide several instructions implementing individual
903 bit manipulation operations such as isolation, masking, setting, or
904 resetting.
905
906 @c Need to add a specification citation here when available.
907
908 @node i386-TBM
909 @section AMD's Trailing Bit Manipulation Instructions
910
911 @cindex TBM, i386
912 @cindex TBM, x86-64
913
914 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
915 instruction set, available on AMD's BDVER2 processors (Trinity and
916 Viperfish).
917
918 TBM instructions provide instructions implementing individual bit
919 manipulation operations such as isolating, masking, setting, resetting,
920 complementing, and operations on trailing zeros and ones.
921
922 @c Need to add a specification citation here when available.
923
924 @node i386-16bit
925 @section Writing 16-bit Code
926
927 @cindex i386 16-bit code
928 @cindex 16-bit code, i386
929 @cindex real-mode code, i386
930 @cindex @code{code16gcc} directive, i386
931 @cindex @code{code16} directive, i386
932 @cindex @code{code32} directive, i386
933 @cindex @code{code64} directive, i386
934 @cindex @code{code64} directive, x86-64
935 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
936 or 64-bit x86-64 code depending on the default configuration,
937 it also supports writing code to run in real mode or in 16-bit protected
938 mode code segments. To do this, put a @samp{.code16} or
939 @samp{.code16gcc} directive before the assembly language instructions to
940 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
941 32-bit code with the @samp{.code32} directive or 64-bit code with the
942 @samp{.code64} directive.
943
944 @samp{.code16gcc} provides experimental support for generating 16-bit
945 code from gcc, and differs from @samp{.code16} in that @samp{call},
946 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
947 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
948 default to 32-bit size. This is so that the stack pointer is
949 manipulated in the same way over function calls, allowing access to
950 function parameters at the same stack offsets as in 32-bit mode.
951 @samp{.code16gcc} also automatically adds address size prefixes where
952 necessary to use the 32-bit addressing modes that gcc generates.
953
954 The code which @code{@value{AS}} generates in 16-bit mode will not
955 necessarily run on a 16-bit pre-80386 processor. To write code that
956 runs on such a processor, you must refrain from using @emph{any} 32-bit
957 constructs which require @code{@value{AS}} to output address or operand
958 size prefixes.
959
960 Note that writing 16-bit code instructions by explicitly specifying a
961 prefix or an instruction mnemonic suffix within a 32-bit code section
962 generates different machine instructions than those generated for a
963 16-bit code segment. In a 32-bit code section, the following code
964 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
965 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
966
967 @smallexample
968 pushw $4
969 @end smallexample
970
971 The same code in a 16-bit code section would generate the machine
972 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
973 is correct since the processor default operand size is assumed to be 16
974 bits in a 16-bit code section.
975
976 @node i386-Bugs
977 @section AT&T Syntax bugs
978
979 The UnixWare assembler, and probably other AT&T derived ix86 Unix
980 assemblers, generate floating point instructions with reversed source
981 and destination registers in certain cases. Unfortunately, gcc and
982 possibly many other programs use this reversed syntax, so we're stuck
983 with it.
984
985 For example
986
987 @smallexample
988 fsub %st,%st(3)
989 @end smallexample
990 @noindent
991 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
992 than the expected @samp{%st(3) - %st}. This happens with all the
993 non-commutative arithmetic floating point operations with two register
994 operands where the source register is @samp{%st} and the destination
995 register is @samp{%st(i)}.
996
997 @node i386-Arch
998 @section Specifying CPU Architecture
999
1000 @cindex arch directive, i386
1001 @cindex i386 arch directive
1002 @cindex arch directive, x86-64
1003 @cindex x86-64 arch directive
1004
1005 @code{@value{AS}} may be told to assemble for a particular CPU
1006 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1007 directive enables a warning when gas detects an instruction that is not
1008 supported on the CPU specified. The choices for @var{cpu_type} are:
1009
1010 @multitable @columnfractions .20 .20 .20 .20
1011 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1012 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1013 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1014 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1015 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1016 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1017 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2}
1018 @item @samp{btver1} @tab @samp{btver2}
1019 @item @samp{generic32} @tab @samp{generic64}
1020 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1021 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1022 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1023 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1024 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1025 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1026 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1027 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1028 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1029 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1030 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
1031 @item @samp{.padlock}
1032 @end multitable
1033
1034 Apart from the warning, there are only two other effects on
1035 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1036 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1037 will automatically use a two byte opcode sequence. The larger three
1038 byte opcode sequence is used on the 486 (and when no architecture is
1039 specified) because it executes faster on the 486. Note that you can
1040 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1041 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1042 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1043 conditional jumps will be promoted when necessary to a two instruction
1044 sequence consisting of a conditional jump of the opposite sense around
1045 an unconditional jump to the target.
1046
1047 Following the CPU architecture (but not a sub-architecture, which are those
1048 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1049 control automatic promotion of conditional jumps. @samp{jumps} is the
1050 default, and enables jump promotion; All external jumps will be of the long
1051 variety, and file-local jumps will be promoted as necessary.
1052 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1053 byte offset jumps, and warns about file-local conditional jumps that
1054 @code{@value{AS}} promotes.
1055 Unconditional jumps are treated as for @samp{jumps}.
1056
1057 For example
1058
1059 @smallexample
1060 .arch i8086,nojumps
1061 @end smallexample
1062
1063 @node i386-Notes
1064 @section Notes
1065
1066 @cindex i386 @code{mul}, @code{imul} instructions
1067 @cindex @code{mul} instruction, i386
1068 @cindex @code{imul} instruction, i386
1069 @cindex @code{mul} instruction, x86-64
1070 @cindex @code{imul} instruction, x86-64
1071 There is some trickery concerning the @samp{mul} and @samp{imul}
1072 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1073 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1074 for @samp{imul}) can be output only in the one operand form. Thus,
1075 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1076 the expanding multiply would clobber the @samp{%edx} register, and this
1077 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1078 64-bit product in @samp{%edx:%eax}.
1079
1080 We have added a two operand form of @samp{imul} when the first operand
1081 is an immediate mode expression and the second operand is a register.
1082 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1083 example, can be done with @samp{imul $69, %eax} rather than @samp{imul
1084 $69, %eax, %eax}.
1085
This page took 0.05907 seconds and 5 git commands to generate.