1 @c Copyright (C) 1991-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics. For example,
132 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
133 @var{vmx}. The following extensions are currently supported:
186 @code{avx512_4fmaps},
187 @code{avx512_4vnniw},
188 @code{avx512_vpopcntdq},
199 @code{noavx512_4fmaps},
200 @code{noavx512_4vnniw},
201 @code{noavx512_vpopcntdq},
202 @code{noavx512_vbmi2},
239 Note that rather than extending a basic instruction set, the extension
240 mnemonics starting with @code{no} revoke the respective functionality.
242 When the @code{.arch} directive is used with @option{-march}, the
243 @code{.arch} directive will take precedent.
245 @cindex @samp{-mtune=} option, i386
246 @cindex @samp{-mtune=} option, x86-64
247 @item -mtune=@var{CPU}
248 This option specifies a processor to optimize for. When used in
249 conjunction with the @option{-march} option, only instructions
250 of the processor specified by the @option{-march} option will be
253 Valid @var{CPU} values are identical to the processor list of
254 @option{-march=@var{CPU}}.
256 @cindex @samp{-msse2avx} option, i386
257 @cindex @samp{-msse2avx} option, x86-64
259 This option specifies that the assembler should encode SSE instructions
262 @cindex @samp{-msse-check=} option, i386
263 @cindex @samp{-msse-check=} option, x86-64
264 @item -msse-check=@var{none}
265 @itemx -msse-check=@var{warning}
266 @itemx -msse-check=@var{error}
267 These options control if the assembler should check SSE instructions.
268 @option{-msse-check=@var{none}} will make the assembler not to check SSE
269 instructions, which is the default. @option{-msse-check=@var{warning}}
270 will make the assembler issue a warning for any SSE instruction.
271 @option{-msse-check=@var{error}} will make the assembler issue an error
272 for any SSE instruction.
274 @cindex @samp{-mavxscalar=} option, i386
275 @cindex @samp{-mavxscalar=} option, x86-64
276 @item -mavxscalar=@var{128}
277 @itemx -mavxscalar=@var{256}
278 These options control how the assembler should encode scalar AVX
279 instructions. @option{-mavxscalar=@var{128}} will encode scalar
280 AVX instructions with 128bit vector length, which is the default.
281 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
282 with 256bit vector length.
284 @cindex @samp{-mevexlig=} option, i386
285 @cindex @samp{-mevexlig=} option, x86-64
286 @item -mevexlig=@var{128}
287 @itemx -mevexlig=@var{256}
288 @itemx -mevexlig=@var{512}
289 These options control how the assembler should encode length-ignored
290 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
291 EVEX instructions with 128bit vector length, which is the default.
292 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
293 encode LIG EVEX instructions with 256bit and 512bit vector length,
296 @cindex @samp{-mevexwig=} option, i386
297 @cindex @samp{-mevexwig=} option, x86-64
298 @item -mevexwig=@var{0}
299 @itemx -mevexwig=@var{1}
300 These options control how the assembler should encode w-ignored (WIG)
301 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
302 EVEX instructions with evex.w = 0, which is the default.
303 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
306 @cindex @samp{-mmnemonic=} option, i386
307 @cindex @samp{-mmnemonic=} option, x86-64
308 @item -mmnemonic=@var{att}
309 @itemx -mmnemonic=@var{intel}
310 This option specifies instruction mnemonic for matching instructions.
311 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
314 @cindex @samp{-msyntax=} option, i386
315 @cindex @samp{-msyntax=} option, x86-64
316 @item -msyntax=@var{att}
317 @itemx -msyntax=@var{intel}
318 This option specifies instruction syntax when processing instructions.
319 The @code{.att_syntax} and @code{.intel_syntax} directives will
322 @cindex @samp{-mnaked-reg} option, i386
323 @cindex @samp{-mnaked-reg} option, x86-64
325 This option specifies that registers don't require a @samp{%} prefix.
326 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
328 @cindex @samp{-madd-bnd-prefix} option, i386
329 @cindex @samp{-madd-bnd-prefix} option, x86-64
330 @item -madd-bnd-prefix
331 This option forces the assembler to add BND prefix to all branches, even
332 if such prefix was not explicitly specified in the source code.
334 @cindex @samp{-mshared} option, i386
335 @cindex @samp{-mshared} option, x86-64
337 On ELF target, the assembler normally optimizes out non-PLT relocations
338 against defined non-weak global branch targets with default visibility.
339 The @samp{-mshared} option tells the assembler to generate code which
340 may go into a shared library where all non-weak global branch targets
341 with default visibility can be preempted. The resulting code is
342 slightly bigger. This option only affects the handling of branch
345 @cindex @samp{-mbig-obj} option, x86-64
347 On x86-64 PE/COFF target this option forces the use of big object file
348 format, which allows more than 32768 sections.
350 @cindex @samp{-momit-lock-prefix=} option, i386
351 @cindex @samp{-momit-lock-prefix=} option, x86-64
352 @item -momit-lock-prefix=@var{no}
353 @itemx -momit-lock-prefix=@var{yes}
354 These options control how the assembler should encode lock prefix.
355 This option is intended as a workaround for processors, that fail on
356 lock prefix. This option can only be safely used with single-core,
357 single-thread computers
358 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
359 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
360 which is the default.
362 @cindex @samp{-mfence-as-lock-add=} option, i386
363 @cindex @samp{-mfence-as-lock-add=} option, x86-64
364 @item -mfence-as-lock-add=@var{no}
365 @itemx -mfence-as-lock-add=@var{yes}
366 These options control how the assembler should encode lfence, mfence and
368 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
369 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
370 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
371 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
372 sfence as usual, which is the default.
374 @cindex @samp{-mrelax-relocations=} option, i386
375 @cindex @samp{-mrelax-relocations=} option, x86-64
376 @item -mrelax-relocations=@var{no}
377 @itemx -mrelax-relocations=@var{yes}
378 These options control whether the assembler should generate relax
379 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
380 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
381 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
382 @option{-mrelax-relocations=@var{no}} will not generate relax
383 relocations. The default can be controlled by a configure option
384 @option{--enable-x86-relax-relocations}.
386 @cindex @samp{-mevexrcig=} option, i386
387 @cindex @samp{-mevexrcig=} option, x86-64
388 @item -mevexrcig=@var{rne}
389 @itemx -mevexrcig=@var{rd}
390 @itemx -mevexrcig=@var{ru}
391 @itemx -mevexrcig=@var{rz}
392 These options control how the assembler should encode SAE-only
393 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
394 of EVEX instruction with 00, which is the default.
395 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
396 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
397 with 01, 10 and 11 RC bits, respectively.
399 @cindex @samp{-mamd64} option, x86-64
400 @cindex @samp{-mintel64} option, x86-64
403 This option specifies that the assembler should accept only AMD64 or
404 Intel64 ISA in 64-bit mode. The default is to accept both.
409 @node i386-Directives
410 @section x86 specific Directives
412 @cindex machine directives, x86
413 @cindex x86 machine directives
416 @cindex @code{lcomm} directive, COFF
417 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
418 Reserve @var{length} (an absolute expression) bytes for a local common
419 denoted by @var{symbol}. The section and value of @var{symbol} are
420 those of the new local common. The addresses are allocated in the bss
421 section, so that at run-time the bytes start off zeroed. Since
422 @var{symbol} is not declared global, it is normally not visible to
423 @code{@value{LD}}. The optional third parameter, @var{alignment},
424 specifies the desired alignment of the symbol in the bss section.
426 This directive is only available for COFF based x86 targets.
428 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
434 @section i386 Syntactical Considerations
436 * i386-Variations:: AT&T Syntax versus Intel Syntax
437 * i386-Chars:: Special Characters
440 @node i386-Variations
441 @subsection AT&T Syntax versus Intel Syntax
443 @cindex i386 intel_syntax pseudo op
444 @cindex intel_syntax pseudo op, i386
445 @cindex i386 att_syntax pseudo op
446 @cindex att_syntax pseudo op, i386
447 @cindex i386 syntax compatibility
448 @cindex syntax compatibility, i386
449 @cindex x86-64 intel_syntax pseudo op
450 @cindex intel_syntax pseudo op, x86-64
451 @cindex x86-64 att_syntax pseudo op
452 @cindex att_syntax pseudo op, x86-64
453 @cindex x86-64 syntax compatibility
454 @cindex syntax compatibility, x86-64
456 @code{@value{AS}} now supports assembly using Intel assembler syntax.
457 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
458 back to the usual AT&T mode for compatibility with the output of
459 @code{@value{GCC}}. Either of these directives may have an optional
460 argument, @code{prefix}, or @code{noprefix} specifying whether registers
461 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
462 different from Intel syntax. We mention these differences because
463 almost all 80386 documents use Intel syntax. Notable differences
464 between the two syntaxes are:
466 @cindex immediate operands, i386
467 @cindex i386 immediate operands
468 @cindex register operands, i386
469 @cindex i386 register operands
470 @cindex jump/call operands, i386
471 @cindex i386 jump/call operands
472 @cindex operand delimiters, i386
474 @cindex immediate operands, x86-64
475 @cindex x86-64 immediate operands
476 @cindex register operands, x86-64
477 @cindex x86-64 register operands
478 @cindex jump/call operands, x86-64
479 @cindex x86-64 jump/call operands
480 @cindex operand delimiters, x86-64
483 AT&T immediate operands are preceded by @samp{$}; Intel immediate
484 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
485 AT&T register operands are preceded by @samp{%}; Intel register operands
486 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
487 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
489 @cindex i386 source, destination operands
490 @cindex source, destination operands; i386
491 @cindex x86-64 source, destination operands
492 @cindex source, destination operands; x86-64
494 AT&T and Intel syntax use the opposite order for source and destination
495 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
496 @samp{source, dest} convention is maintained for compatibility with
497 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
498 instructions with 2 immediate operands, such as the @samp{enter}
499 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
501 @cindex mnemonic suffixes, i386
502 @cindex sizes operands, i386
503 @cindex i386 size suffixes
504 @cindex mnemonic suffixes, x86-64
505 @cindex sizes operands, x86-64
506 @cindex x86-64 size suffixes
508 In AT&T syntax the size of memory operands is determined from the last
509 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
510 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
511 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
512 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
513 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
514 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
517 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
518 instruction with the 64-bit displacement or immediate operand.
520 @cindex return instructions, i386
521 @cindex i386 jump, call, return
522 @cindex return instructions, x86-64
523 @cindex x86-64 jump, call, return
525 Immediate form long jumps and calls are
526 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
528 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
530 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
531 @samp{ret far @var{stack-adjust}}.
533 @cindex sections, i386
534 @cindex i386 sections
535 @cindex sections, x86-64
536 @cindex x86-64 sections
538 The AT&T assembler does not provide support for multiple section
539 programs. Unix style systems expect all programs to be single sections.
543 @subsection Special Characters
545 @cindex line comment character, i386
546 @cindex i386 line comment character
547 The presence of a @samp{#} appearing anywhere on a line indicates the
548 start of a comment that extends to the end of that line.
550 If a @samp{#} appears as the first character of a line then the whole
551 line is treated as a comment, but in this case the line can also be a
552 logical line number directive (@pxref{Comments}) or a preprocessor
553 control command (@pxref{Preprocessing}).
555 If the @option{--divide} command line option has not been specified
556 then the @samp{/} character appearing anywhere on a line also
557 introduces a line comment.
559 @cindex line separator, i386
560 @cindex statement separator, i386
561 @cindex i386 line separator
562 The @samp{;} character can be used to separate statements on the same
566 @section i386-Mnemonics
567 @subsection Instruction Naming
569 @cindex i386 instruction naming
570 @cindex instruction naming, i386
571 @cindex x86-64 instruction naming
572 @cindex instruction naming, x86-64
574 Instruction mnemonics are suffixed with one character modifiers which
575 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
576 and @samp{q} specify byte, word, long and quadruple word operands. If
577 no suffix is specified by an instruction then @code{@value{AS}} tries to
578 fill in the missing suffix based on the destination register operand
579 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
580 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
581 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
582 assembler which assumes that a missing mnemonic suffix implies long
583 operand size. (This incompatibility does not affect compiler output
584 since compilers always explicitly specify the mnemonic suffix.)
586 Almost all instructions have the same names in AT&T and Intel format.
587 There are a few exceptions. The sign extend and zero extend
588 instructions need two sizes to specify them. They need a size to
589 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
590 is accomplished by using two instruction mnemonic suffixes in AT&T
591 syntax. Base names for sign extend and zero extend are
592 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
593 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
594 are tacked on to this base name, the @emph{from} suffix before the
595 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
596 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
597 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
598 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
599 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
602 @cindex encoding options, i386
603 @cindex encoding options, x86-64
605 Different encoding options can be specified via pseudo prefixes:
609 @samp{@{disp8@}} -- prefer 8-bit displacement.
612 @samp{@{disp32@}} -- prefer 32-bit displacement.
615 @samp{@{load@}} -- prefer load-form instruction.
618 @samp{@{store@}} -- prefer store-form instruction.
621 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
624 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
627 @samp{@{evex@}} -- encode with EVEX prefix.
630 @cindex conversion instructions, i386
631 @cindex i386 conversion instructions
632 @cindex conversion instructions, x86-64
633 @cindex x86-64 conversion instructions
634 The Intel-syntax conversion instructions
638 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
641 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
644 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
647 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
650 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
654 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
655 @samp{%rdx:%rax} (x86-64 only),
659 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
660 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
663 @cindex jump instructions, i386
664 @cindex call instructions, i386
665 @cindex jump instructions, x86-64
666 @cindex call instructions, x86-64
667 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
668 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
671 @subsection AT&T Mnemonic versus Intel Mnemonic
673 @cindex i386 mnemonic compatibility
674 @cindex mnemonic compatibility, i386
676 @code{@value{AS}} supports assembly using Intel mnemonic.
677 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
678 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
679 syntax for compatibility with the output of @code{@value{GCC}}.
680 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
681 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
682 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
683 assembler with different mnemonics from those in Intel IA32 specification.
684 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
687 @section Register Naming
689 @cindex i386 registers
690 @cindex registers, i386
691 @cindex x86-64 registers
692 @cindex registers, x86-64
693 Register operands are always prefixed with @samp{%}. The 80386 registers
698 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
699 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
700 frame pointer), and @samp{%esp} (the stack pointer).
703 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
704 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
707 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
708 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
709 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
710 @samp{%cx}, and @samp{%dx})
713 the 6 section registers @samp{%cs} (code section), @samp{%ds}
714 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
718 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
719 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
722 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
723 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
726 the 2 test registers @samp{%tr6} and @samp{%tr7}.
729 the 8 floating point register stack @samp{%st} or equivalently
730 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
731 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
732 These registers are overloaded by 8 MMX registers @samp{%mm0},
733 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
734 @samp{%mm6} and @samp{%mm7}.
737 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
738 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
741 The AMD x86-64 architecture extends the register set by:
745 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
746 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
747 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
751 the 8 extended registers @samp{%r8}--@samp{%r15}.
754 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
757 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
760 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
763 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
766 the 8 debug registers: @samp{%db8}--@samp{%db15}.
769 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
772 With the AVX extensions more registers were made available:
777 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
778 available in 32-bit mode). The bottom 128 bits are overlaid with the
779 @samp{xmm0}--@samp{xmm15} registers.
783 The AVX2 extensions made in 64-bit mode more registers available:
788 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
789 registers @samp{%ymm16}--@samp{%ymm31}.
793 The AVX512 extensions added the following registers:
798 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
799 available in 32-bit mode). The bottom 128 bits are overlaid with the
800 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
801 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
804 the 8 mask registers @samp{%k0}--@samp{%k7}.
809 @section Instruction Prefixes
811 @cindex i386 instruction prefixes
812 @cindex instruction prefixes, i386
813 @cindex prefixes, i386
814 Instruction prefixes are used to modify the following instruction. They
815 are used to repeat string instructions, to provide section overrides, to
816 perform bus lock operations, and to change operand and address sizes.
817 (Most instructions that normally operate on 32-bit operands will use
818 16-bit operands if the instruction has an ``operand size'' prefix.)
819 Instruction prefixes are best written on the same line as the instruction
820 they act upon. For example, the @samp{scas} (scan string) instruction is
824 repne scas %es:(%edi),%al
827 You may also place prefixes on the lines immediately preceding the
828 instruction, but this circumvents checks that @code{@value{AS}} does
829 with prefixes, and will not work with all prefixes.
831 Here is a list of instruction prefixes:
833 @cindex section override prefixes, i386
836 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
837 @samp{fs}, @samp{gs}. These are automatically added by specifying
838 using the @var{section}:@var{memory-operand} form for memory references.
840 @cindex size prefixes, i386
842 Operand/Address size prefixes @samp{data16} and @samp{addr16}
843 change 32-bit operands/addresses into 16-bit operands/addresses,
844 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
845 @code{.code16} section) into 32-bit operands/addresses. These prefixes
846 @emph{must} appear on the same line of code as the instruction they
847 modify. For example, in a 16-bit @code{.code16} section, you might
854 @cindex bus lock prefixes, i386
855 @cindex inhibiting interrupts, i386
857 The bus lock prefix @samp{lock} inhibits interrupts during execution of
858 the instruction it precedes. (This is only valid with certain
859 instructions; see a 80386 manual for details).
861 @cindex coprocessor wait, i386
863 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
864 complete the current instruction. This should never be needed for the
865 80386/80387 combination.
867 @cindex repeat prefixes, i386
869 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
870 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
871 times if the current address size is 16-bits).
872 @cindex REX prefixes, i386
874 The @samp{rex} family of prefixes is used by x86-64 to encode
875 extensions to i386 instruction set. The @samp{rex} prefix has four
876 bits --- an operand size overwrite (@code{64}) used to change operand size
877 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
880 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
881 instruction emits @samp{rex} prefix with all the bits set. By omitting
882 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
883 prefixes as well. Normally, there is no need to write the prefixes
884 explicitly, since gas will automatically generate them based on the
885 instruction operands.
889 @section Memory References
891 @cindex i386 memory references
892 @cindex memory references, i386
893 @cindex x86-64 memory references
894 @cindex memory references, x86-64
895 An Intel syntax indirect memory reference of the form
898 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
902 is translated into the AT&T syntax
905 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
909 where @var{base} and @var{index} are the optional 32-bit base and
910 index registers, @var{disp} is the optional displacement, and
911 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
912 to calculate the address of the operand. If no @var{scale} is
913 specified, @var{scale} is taken to be 1. @var{section} specifies the
914 optional section register for the memory operand, and may override the
915 default section register (see a 80386 manual for section register
916 defaults). Note that section overrides in AT&T syntax @emph{must}
917 be preceded by a @samp{%}. If you specify a section override which
918 coincides with the default section register, @code{@value{AS}} does @emph{not}
919 output any section register override prefixes to assemble the given
920 instruction. Thus, section overrides can be specified to emphasize which
921 section register is used for a given memory operand.
923 Here are some examples of Intel and AT&T style memory references:
926 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
927 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
928 missing, and the default section is used (@samp{%ss} for addressing with
929 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
931 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
932 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
933 @samp{foo}. All other fields are missing. The section register here
934 defaults to @samp{%ds}.
936 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
937 This uses the value pointed to by @samp{foo} as a memory operand.
938 Note that @var{base} and @var{index} are both missing, but there is only
939 @emph{one} @samp{,}. This is a syntactic exception.
941 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
942 This selects the contents of the variable @samp{foo} with section
943 register @var{section} being @samp{%gs}.
946 Absolute (as opposed to PC relative) call and jump operands must be
947 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
948 always chooses PC relative addressing for jump/call labels.
950 Any instruction that has a memory operand, but no register operand,
951 @emph{must} specify its size (byte, word, long, or quadruple) with an
952 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
955 The x86-64 architecture adds an RIP (instruction pointer relative)
956 addressing. This addressing mode is specified by using @samp{rip} as a
957 base register. Only constant offsets are valid. For example:
960 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
961 Points to the address 1234 bytes past the end of the current
964 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
965 Points to the @code{symbol} in RIP relative way, this is shorter than
966 the default absolute addressing.
969 Other addressing modes remain unchanged in x86-64 architecture, except
970 registers used are 64-bit instead of 32-bit.
973 @section Handling of Jump Instructions
975 @cindex jump optimization, i386
976 @cindex i386 jump optimization
977 @cindex jump optimization, x86-64
978 @cindex x86-64 jump optimization
979 Jump instructions are always optimized to use the smallest possible
980 displacements. This is accomplished by using byte (8-bit) displacement
981 jumps whenever the target is sufficiently close. If a byte displacement
982 is insufficient a long displacement is used. We do not support
983 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
984 instruction with the @samp{data16} instruction prefix), since the 80386
985 insists upon masking @samp{%eip} to 16 bits after the word displacement
986 is added. (See also @pxref{i386-Arch})
988 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
989 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
990 displacements, so that if you use these instructions (@code{@value{GCC}} does
991 not use them) you may get an error message (and incorrect code). The AT&T
992 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1003 @section Floating Point
1005 @cindex i386 floating point
1006 @cindex floating point, i386
1007 @cindex x86-64 floating point
1008 @cindex floating point, x86-64
1009 All 80387 floating point types except packed BCD are supported.
1010 (BCD support may be added without much difficulty). These data
1011 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1012 double (64-bit), and extended (80-bit) precision floating point.
1013 Each supported type has an instruction mnemonic suffix and a constructor
1014 associated with it. Instruction mnemonic suffixes specify the operand's
1015 data type. Constructors build these data types into memory.
1017 @cindex @code{float} directive, i386
1018 @cindex @code{single} directive, i386
1019 @cindex @code{double} directive, i386
1020 @cindex @code{tfloat} directive, i386
1021 @cindex @code{float} directive, x86-64
1022 @cindex @code{single} directive, x86-64
1023 @cindex @code{double} directive, x86-64
1024 @cindex @code{tfloat} directive, x86-64
1027 Floating point constructors are @samp{.float} or @samp{.single},
1028 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1029 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1030 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1031 only supports this format via the @samp{fldt} (load 80-bit real to stack
1032 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1034 @cindex @code{word} directive, i386
1035 @cindex @code{long} directive, i386
1036 @cindex @code{int} directive, i386
1037 @cindex @code{quad} directive, i386
1038 @cindex @code{word} directive, x86-64
1039 @cindex @code{long} directive, x86-64
1040 @cindex @code{int} directive, x86-64
1041 @cindex @code{quad} directive, x86-64
1043 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1044 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1045 corresponding instruction mnemonic suffixes are @samp{s} (single),
1046 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1047 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1048 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1049 stack) instructions.
1052 Register to register operations should not use instruction mnemonic suffixes.
1053 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1054 wrote @samp{fst %st, %st(1)}, since all register to register operations
1055 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1056 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1057 then stores the result in the 4 byte location @samp{mem})
1060 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1063 @cindex 3DNow!, i386
1066 @cindex 3DNow!, x86-64
1067 @cindex SIMD, x86-64
1069 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1070 instructions for integer data), available on Intel's Pentium MMX
1071 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1072 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1073 instruction set (SIMD instructions for 32-bit floating point data)
1074 available on AMD's K6-2 processor and possibly others in the future.
1076 Currently, @code{@value{AS}} does not support Intel's floating point
1079 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1080 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1081 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1082 floating point values. The MMX registers cannot be used at the same time
1083 as the floating point stack.
1085 See Intel and AMD documentation, keeping in mind that the operand order in
1086 instructions is reversed from the Intel syntax.
1089 @section AMD's Lightweight Profiling Instructions
1094 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1095 instruction set, available on AMD's Family 15h (Orochi) processors.
1097 LWP enables applications to collect and manage performance data, and
1098 react to performance events. The collection of performance data
1099 requires no context switches. LWP runs in the context of a thread and
1100 so several counters can be used independently across multiple threads.
1101 LWP can be used in both 64-bit and legacy 32-bit modes.
1103 For detailed information on the LWP instruction set, see the
1104 @cite{AMD Lightweight Profiling Specification} available at
1105 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1108 @section Bit Manipulation Instructions
1113 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1115 BMI instructions provide several instructions implementing individual
1116 bit manipulation operations such as isolation, masking, setting, or
1119 @c Need to add a specification citation here when available.
1122 @section AMD's Trailing Bit Manipulation Instructions
1127 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1128 instruction set, available on AMD's BDVER2 processors (Trinity and
1131 TBM instructions provide instructions implementing individual bit
1132 manipulation operations such as isolating, masking, setting, resetting,
1133 complementing, and operations on trailing zeros and ones.
1135 @c Need to add a specification citation here when available.
1138 @section Writing 16-bit Code
1140 @cindex i386 16-bit code
1141 @cindex 16-bit code, i386
1142 @cindex real-mode code, i386
1143 @cindex @code{code16gcc} directive, i386
1144 @cindex @code{code16} directive, i386
1145 @cindex @code{code32} directive, i386
1146 @cindex @code{code64} directive, i386
1147 @cindex @code{code64} directive, x86-64
1148 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1149 or 64-bit x86-64 code depending on the default configuration,
1150 it also supports writing code to run in real mode or in 16-bit protected
1151 mode code segments. To do this, put a @samp{.code16} or
1152 @samp{.code16gcc} directive before the assembly language instructions to
1153 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1154 32-bit code with the @samp{.code32} directive or 64-bit code with the
1155 @samp{.code64} directive.
1157 @samp{.code16gcc} provides experimental support for generating 16-bit
1158 code from gcc, and differs from @samp{.code16} in that @samp{call},
1159 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1160 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1161 default to 32-bit size. This is so that the stack pointer is
1162 manipulated in the same way over function calls, allowing access to
1163 function parameters at the same stack offsets as in 32-bit mode.
1164 @samp{.code16gcc} also automatically adds address size prefixes where
1165 necessary to use the 32-bit addressing modes that gcc generates.
1167 The code which @code{@value{AS}} generates in 16-bit mode will not
1168 necessarily run on a 16-bit pre-80386 processor. To write code that
1169 runs on such a processor, you must refrain from using @emph{any} 32-bit
1170 constructs which require @code{@value{AS}} to output address or operand
1173 Note that writing 16-bit code instructions by explicitly specifying a
1174 prefix or an instruction mnemonic suffix within a 32-bit code section
1175 generates different machine instructions than those generated for a
1176 16-bit code segment. In a 32-bit code section, the following code
1177 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1178 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1184 The same code in a 16-bit code section would generate the machine
1185 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1186 is correct since the processor default operand size is assumed to be 16
1187 bits in a 16-bit code section.
1190 @section Specifying CPU Architecture
1192 @cindex arch directive, i386
1193 @cindex i386 arch directive
1194 @cindex arch directive, x86-64
1195 @cindex x86-64 arch directive
1197 @code{@value{AS}} may be told to assemble for a particular CPU
1198 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1199 directive enables a warning when gas detects an instruction that is not
1200 supported on the CPU specified. The choices for @var{cpu_type} are:
1202 @multitable @columnfractions .20 .20 .20 .20
1203 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1204 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1205 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1206 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1207 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1208 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1209 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1210 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1211 @item @samp{generic32} @tab @samp{generic64}
1212 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1213 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1214 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1215 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1216 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1217 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1218 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1219 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1220 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1221 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1222 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1223 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1224 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1225 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2}
1226 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.cet}
1227 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1228 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1229 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1230 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.gfni}
1234 Apart from the warning, there are only two other effects on
1235 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1236 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1237 will automatically use a two byte opcode sequence. The larger three
1238 byte opcode sequence is used on the 486 (and when no architecture is
1239 specified) because it executes faster on the 486. Note that you can
1240 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1241 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1242 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1243 conditional jumps will be promoted when necessary to a two instruction
1244 sequence consisting of a conditional jump of the opposite sense around
1245 an unconditional jump to the target.
1247 Following the CPU architecture (but not a sub-architecture, which are those
1248 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1249 control automatic promotion of conditional jumps. @samp{jumps} is the
1250 default, and enables jump promotion; All external jumps will be of the long
1251 variety, and file-local jumps will be promoted as necessary.
1252 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1253 byte offset jumps, and warns about file-local conditional jumps that
1254 @code{@value{AS}} promotes.
1255 Unconditional jumps are treated as for @samp{jumps}.
1264 @section AT&T Syntax bugs
1266 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1267 assemblers, generate floating point instructions with reversed source
1268 and destination registers in certain cases. Unfortunately, gcc and
1269 possibly many other programs use this reversed syntax, so we're stuck
1278 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1279 than the expected @samp{%st(3) - %st}. This happens with all the
1280 non-commutative arithmetic floating point operations with two register
1281 operands where the source register is @samp{%st} and the destination
1282 register is @samp{%st(i)}.
1287 @cindex i386 @code{mul}, @code{imul} instructions
1288 @cindex @code{mul} instruction, i386
1289 @cindex @code{imul} instruction, i386
1290 @cindex @code{mul} instruction, x86-64
1291 @cindex @code{imul} instruction, x86-64
1292 There is some trickery concerning the @samp{mul} and @samp{imul}
1293 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1294 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1295 for @samp{imul}) can be output only in the one operand form. Thus,
1296 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1297 the expanding multiply would clobber the @samp{%edx} register, and this
1298 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1299 64-bit product in @samp{%edx:%eax}.
1301 We have added a two operand form of @samp{imul} when the first operand
1302 is an immediate mode expression and the second operand is a register.
1303 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1304 example, can be done with @samp{imul $69, %eax} rather than @samp{imul