1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
128 In addition to the basic instruction set, the assembler can be told to
129 accept various extension mnemonics. For example,
130 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
131 @var{vmx}. The following extensions are currently supported:
194 Note that rather than extending a basic instruction set, the extension
195 mnemonics starting with @code{no} revoke the respective functionality.
197 When the @code{.arch} directive is used with @option{-march}, the
198 @code{.arch} directive will take precedent.
200 @cindex @samp{-mtune=} option, i386
201 @cindex @samp{-mtune=} option, x86-64
202 @item -mtune=@var{CPU}
203 This option specifies a processor to optimize for. When used in
204 conjunction with the @option{-march} option, only instructions
205 of the processor specified by the @option{-march} option will be
208 Valid @var{CPU} values are identical to the processor list of
209 @option{-march=@var{CPU}}.
211 @cindex @samp{-msse2avx} option, i386
212 @cindex @samp{-msse2avx} option, x86-64
214 This option specifies that the assembler should encode SSE instructions
217 @cindex @samp{-msse-check=} option, i386
218 @cindex @samp{-msse-check=} option, x86-64
219 @item -msse-check=@var{none}
220 @itemx -msse-check=@var{warning}
221 @itemx -msse-check=@var{error}
222 These options control if the assembler should check SSE instructions.
223 @option{-msse-check=@var{none}} will make the assembler not to check SSE
224 instructions, which is the default. @option{-msse-check=@var{warning}}
225 will make the assembler issue a warning for any SSE instruction.
226 @option{-msse-check=@var{error}} will make the assembler issue an error
227 for any SSE instruction.
229 @cindex @samp{-mavxscalar=} option, i386
230 @cindex @samp{-mavxscalar=} option, x86-64
231 @item -mavxscalar=@var{128}
232 @itemx -mavxscalar=@var{256}
233 These options control how the assembler should encode scalar AVX
234 instructions. @option{-mavxscalar=@var{128}} will encode scalar
235 AVX instructions with 128bit vector length, which is the default.
236 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
237 with 256bit vector length.
239 @cindex @samp{-mevexlig=} option, i386
240 @cindex @samp{-mevexlig=} option, x86-64
241 @item -mevexlig=@var{128}
242 @itemx -mevexlig=@var{256}
243 @itemx -mevexlig=@var{512}
244 These options control how the assembler should encode length-ignored
245 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
246 EVEX instructions with 128bit vector length, which is the default.
247 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
248 encode LIG EVEX instructions with 256bit and 512bit vector length,
251 @cindex @samp{-mevexwig=} option, i386
252 @cindex @samp{-mevexwig=} option, x86-64
253 @item -mevexwig=@var{0}
254 @itemx -mevexwig=@var{1}
255 These options control how the assembler should encode w-ignored (WIG)
256 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
257 EVEX instructions with evex.w = 0, which is the default.
258 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
261 @cindex @samp{-mmnemonic=} option, i386
262 @cindex @samp{-mmnemonic=} option, x86-64
263 @item -mmnemonic=@var{att}
264 @itemx -mmnemonic=@var{intel}
265 This option specifies instruction mnemonic for matching instructions.
266 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
269 @cindex @samp{-msyntax=} option, i386
270 @cindex @samp{-msyntax=} option, x86-64
271 @item -msyntax=@var{att}
272 @itemx -msyntax=@var{intel}
273 This option specifies instruction syntax when processing instructions.
274 The @code{.att_syntax} and @code{.intel_syntax} directives will
277 @cindex @samp{-mnaked-reg} option, i386
278 @cindex @samp{-mnaked-reg} option, x86-64
280 This opetion specifies that registers don't require a @samp{%} prefix.
281 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
283 @cindex @samp{-madd-bnd-prefix} option, i386
284 @cindex @samp{-madd-bnd-prefix} option, x86-64
285 @item -madd-bnd-prefix
286 This option forces the assembler to add BND prefix to all branches, even
287 if such prefix was not explicitly specified in the source code.
289 @cindex @samp{-mbig-obj} option, x86-64
291 On x86-64 PE/COFF target this option forces the use of big object file
292 format, which allows more than 32768 sections.
297 @node i386-Directives
298 @section x86 specific Directives
300 @cindex machine directives, x86
301 @cindex x86 machine directives
304 @cindex @code{lcomm} directive, COFF
305 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
306 Reserve @var{length} (an absolute expression) bytes for a local common
307 denoted by @var{symbol}. The section and value of @var{symbol} are
308 those of the new local common. The addresses are allocated in the bss
309 section, so that at run-time the bytes start off zeroed. Since
310 @var{symbol} is not declared global, it is normally not visible to
311 @code{@value{LD}}. The optional third parameter, @var{alignment},
312 specifies the desired alignment of the symbol in the bss section.
314 This directive is only available for COFF based x86 targets.
316 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
322 @section i386 Syntactical Considerations
324 * i386-Variations:: AT&T Syntax versus Intel Syntax
325 * i386-Chars:: Special Characters
328 @node i386-Variations
329 @subsection AT&T Syntax versus Intel Syntax
331 @cindex i386 intel_syntax pseudo op
332 @cindex intel_syntax pseudo op, i386
333 @cindex i386 att_syntax pseudo op
334 @cindex att_syntax pseudo op, i386
335 @cindex i386 syntax compatibility
336 @cindex syntax compatibility, i386
337 @cindex x86-64 intel_syntax pseudo op
338 @cindex intel_syntax pseudo op, x86-64
339 @cindex x86-64 att_syntax pseudo op
340 @cindex att_syntax pseudo op, x86-64
341 @cindex x86-64 syntax compatibility
342 @cindex syntax compatibility, x86-64
344 @code{@value{AS}} now supports assembly using Intel assembler syntax.
345 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
346 back to the usual AT&T mode for compatibility with the output of
347 @code{@value{GCC}}. Either of these directives may have an optional
348 argument, @code{prefix}, or @code{noprefix} specifying whether registers
349 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
350 different from Intel syntax. We mention these differences because
351 almost all 80386 documents use Intel syntax. Notable differences
352 between the two syntaxes are:
354 @cindex immediate operands, i386
355 @cindex i386 immediate operands
356 @cindex register operands, i386
357 @cindex i386 register operands
358 @cindex jump/call operands, i386
359 @cindex i386 jump/call operands
360 @cindex operand delimiters, i386
362 @cindex immediate operands, x86-64
363 @cindex x86-64 immediate operands
364 @cindex register operands, x86-64
365 @cindex x86-64 register operands
366 @cindex jump/call operands, x86-64
367 @cindex x86-64 jump/call operands
368 @cindex operand delimiters, x86-64
371 AT&T immediate operands are preceded by @samp{$}; Intel immediate
372 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
373 AT&T register operands are preceded by @samp{%}; Intel register operands
374 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
375 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
377 @cindex i386 source, destination operands
378 @cindex source, destination operands; i386
379 @cindex x86-64 source, destination operands
380 @cindex source, destination operands; x86-64
382 AT&T and Intel syntax use the opposite order for source and destination
383 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
384 @samp{source, dest} convention is maintained for compatibility with
385 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
386 instructions with 2 immediate operands, such as the @samp{enter}
387 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
389 @cindex mnemonic suffixes, i386
390 @cindex sizes operands, i386
391 @cindex i386 size suffixes
392 @cindex mnemonic suffixes, x86-64
393 @cindex sizes operands, x86-64
394 @cindex x86-64 size suffixes
396 In AT&T syntax the size of memory operands is determined from the last
397 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
398 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
399 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
400 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
401 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
402 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
405 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
406 instruction with the 64-bit displacement or immediate operand.
408 @cindex return instructions, i386
409 @cindex i386 jump, call, return
410 @cindex return instructions, x86-64
411 @cindex x86-64 jump, call, return
413 Immediate form long jumps and calls are
414 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
416 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
418 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
419 @samp{ret far @var{stack-adjust}}.
421 @cindex sections, i386
422 @cindex i386 sections
423 @cindex sections, x86-64
424 @cindex x86-64 sections
426 The AT&T assembler does not provide support for multiple section
427 programs. Unix style systems expect all programs to be single sections.
431 @subsection Special Characters
433 @cindex line comment character, i386
434 @cindex i386 line comment character
435 The presence of a @samp{#} appearing anywhere on a line indicates the
436 start of a comment that extends to the end of that line.
438 If a @samp{#} appears as the first character of a line then the whole
439 line is treated as a comment, but in this case the line can also be a
440 logical line number directive (@pxref{Comments}) or a preprocessor
441 control command (@pxref{Preprocessing}).
443 If the @option{--divide} command line option has not been specified
444 then the @samp{/} character appearing anywhere on a line also
445 introduces a line comment.
447 @cindex line separator, i386
448 @cindex statement separator, i386
449 @cindex i386 line separator
450 The @samp{;} character can be used to separate statements on the same
454 @section Instruction Naming
456 @cindex i386 instruction naming
457 @cindex instruction naming, i386
458 @cindex x86-64 instruction naming
459 @cindex instruction naming, x86-64
461 Instruction mnemonics are suffixed with one character modifiers which
462 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
463 and @samp{q} specify byte, word, long and quadruple word operands. If
464 no suffix is specified by an instruction then @code{@value{AS}} tries to
465 fill in the missing suffix based on the destination register operand
466 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
467 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
468 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
469 assembler which assumes that a missing mnemonic suffix implies long
470 operand size. (This incompatibility does not affect compiler output
471 since compilers always explicitly specify the mnemonic suffix.)
473 Almost all instructions have the same names in AT&T and Intel format.
474 There are a few exceptions. The sign extend and zero extend
475 instructions need two sizes to specify them. They need a size to
476 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
477 is accomplished by using two instruction mnemonic suffixes in AT&T
478 syntax. Base names for sign extend and zero extend are
479 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
480 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
481 are tacked on to this base name, the @emph{from} suffix before the
482 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
483 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
484 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
485 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
486 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
489 @cindex encoding options, i386
490 @cindex encoding options, x86-64
492 Different encoding options can be specified via optional mnemonic
493 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
494 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
495 prefers 8bit or 32bit displacement in encoding.
497 @cindex conversion instructions, i386
498 @cindex i386 conversion instructions
499 @cindex conversion instructions, x86-64
500 @cindex x86-64 conversion instructions
501 The Intel-syntax conversion instructions
505 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
508 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
511 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
514 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
517 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
521 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
522 @samp{%rdx:%rax} (x86-64 only),
526 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
527 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
530 @cindex jump instructions, i386
531 @cindex call instructions, i386
532 @cindex jump instructions, x86-64
533 @cindex call instructions, x86-64
534 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
535 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
538 @section AT&T Mnemonic versus Intel Mnemonic
540 @cindex i386 mnemonic compatibility
541 @cindex mnemonic compatibility, i386
543 @code{@value{AS}} supports assembly using Intel mnemonic.
544 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
545 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
546 syntax for compatibility with the output of @code{@value{GCC}}.
547 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
548 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
549 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
550 assembler with different mnemonics from those in Intel IA32 specification.
551 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
554 @section Register Naming
556 @cindex i386 registers
557 @cindex registers, i386
558 @cindex x86-64 registers
559 @cindex registers, x86-64
560 Register operands are always prefixed with @samp{%}. The 80386 registers
565 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
566 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
567 frame pointer), and @samp{%esp} (the stack pointer).
570 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
571 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
574 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
575 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
576 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
577 @samp{%cx}, and @samp{%dx})
580 the 6 section registers @samp{%cs} (code section), @samp{%ds}
581 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
585 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
589 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
590 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
593 the 2 test registers @samp{%tr6} and @samp{%tr7}.
596 the 8 floating point register stack @samp{%st} or equivalently
597 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
598 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
599 These registers are overloaded by 8 MMX registers @samp{%mm0},
600 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
601 @samp{%mm6} and @samp{%mm7}.
604 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
605 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
608 The AMD x86-64 architecture extends the register set by:
612 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
613 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
614 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
618 the 8 extended registers @samp{%r8}--@samp{%r15}.
621 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
624 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
627 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
630 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
633 the 8 debug registers: @samp{%db8}--@samp{%db15}.
636 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
640 @section Instruction Prefixes
642 @cindex i386 instruction prefixes
643 @cindex instruction prefixes, i386
644 @cindex prefixes, i386
645 Instruction prefixes are used to modify the following instruction. They
646 are used to repeat string instructions, to provide section overrides, to
647 perform bus lock operations, and to change operand and address sizes.
648 (Most instructions that normally operate on 32-bit operands will use
649 16-bit operands if the instruction has an ``operand size'' prefix.)
650 Instruction prefixes are best written on the same line as the instruction
651 they act upon. For example, the @samp{scas} (scan string) instruction is
655 repne scas %es:(%edi),%al
658 You may also place prefixes on the lines immediately preceding the
659 instruction, but this circumvents checks that @code{@value{AS}} does
660 with prefixes, and will not work with all prefixes.
662 Here is a list of instruction prefixes:
664 @cindex section override prefixes, i386
667 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
668 @samp{fs}, @samp{gs}. These are automatically added by specifying
669 using the @var{section}:@var{memory-operand} form for memory references.
671 @cindex size prefixes, i386
673 Operand/Address size prefixes @samp{data16} and @samp{addr16}
674 change 32-bit operands/addresses into 16-bit operands/addresses,
675 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
676 @code{.code16} section) into 32-bit operands/addresses. These prefixes
677 @emph{must} appear on the same line of code as the instruction they
678 modify. For example, in a 16-bit @code{.code16} section, you might
685 @cindex bus lock prefixes, i386
686 @cindex inhibiting interrupts, i386
688 The bus lock prefix @samp{lock} inhibits interrupts during execution of
689 the instruction it precedes. (This is only valid with certain
690 instructions; see a 80386 manual for details).
692 @cindex coprocessor wait, i386
694 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
695 complete the current instruction. This should never be needed for the
696 80386/80387 combination.
698 @cindex repeat prefixes, i386
700 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
701 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
702 times if the current address size is 16-bits).
703 @cindex REX prefixes, i386
705 The @samp{rex} family of prefixes is used by x86-64 to encode
706 extensions to i386 instruction set. The @samp{rex} prefix has four
707 bits --- an operand size overwrite (@code{64}) used to change operand size
708 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
711 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
712 instruction emits @samp{rex} prefix with all the bits set. By omitting
713 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
714 prefixes as well. Normally, there is no need to write the prefixes
715 explicitly, since gas will automatically generate them based on the
716 instruction operands.
720 @section Memory References
722 @cindex i386 memory references
723 @cindex memory references, i386
724 @cindex x86-64 memory references
725 @cindex memory references, x86-64
726 An Intel syntax indirect memory reference of the form
729 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
733 is translated into the AT&T syntax
736 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
740 where @var{base} and @var{index} are the optional 32-bit base and
741 index registers, @var{disp} is the optional displacement, and
742 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
743 to calculate the address of the operand. If no @var{scale} is
744 specified, @var{scale} is taken to be 1. @var{section} specifies the
745 optional section register for the memory operand, and may override the
746 default section register (see a 80386 manual for section register
747 defaults). Note that section overrides in AT&T syntax @emph{must}
748 be preceded by a @samp{%}. If you specify a section override which
749 coincides with the default section register, @code{@value{AS}} does @emph{not}
750 output any section register override prefixes to assemble the given
751 instruction. Thus, section overrides can be specified to emphasize which
752 section register is used for a given memory operand.
754 Here are some examples of Intel and AT&T style memory references:
757 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
758 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
759 missing, and the default section is used (@samp{%ss} for addressing with
760 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
762 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
763 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
764 @samp{foo}. All other fields are missing. The section register here
765 defaults to @samp{%ds}.
767 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
768 This uses the value pointed to by @samp{foo} as a memory operand.
769 Note that @var{base} and @var{index} are both missing, but there is only
770 @emph{one} @samp{,}. This is a syntactic exception.
772 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
773 This selects the contents of the variable @samp{foo} with section
774 register @var{section} being @samp{%gs}.
777 Absolute (as opposed to PC relative) call and jump operands must be
778 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
779 always chooses PC relative addressing for jump/call labels.
781 Any instruction that has a memory operand, but no register operand,
782 @emph{must} specify its size (byte, word, long, or quadruple) with an
783 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
786 The x86-64 architecture adds an RIP (instruction pointer relative)
787 addressing. This addressing mode is specified by using @samp{rip} as a
788 base register. Only constant offsets are valid. For example:
791 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
792 Points to the address 1234 bytes past the end of the current
795 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
796 Points to the @code{symbol} in RIP relative way, this is shorter than
797 the default absolute addressing.
800 Other addressing modes remain unchanged in x86-64 architecture, except
801 registers used are 64-bit instead of 32-bit.
804 @section Handling of Jump Instructions
806 @cindex jump optimization, i386
807 @cindex i386 jump optimization
808 @cindex jump optimization, x86-64
809 @cindex x86-64 jump optimization
810 Jump instructions are always optimized to use the smallest possible
811 displacements. This is accomplished by using byte (8-bit) displacement
812 jumps whenever the target is sufficiently close. If a byte displacement
813 is insufficient a long displacement is used. We do not support
814 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
815 instruction with the @samp{data16} instruction prefix), since the 80386
816 insists upon masking @samp{%eip} to 16 bits after the word displacement
817 is added. (See also @pxref{i386-Arch})
819 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
820 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
821 displacements, so that if you use these instructions (@code{@value{GCC}} does
822 not use them) you may get an error message (and incorrect code). The AT&T
823 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
834 @section Floating Point
836 @cindex i386 floating point
837 @cindex floating point, i386
838 @cindex x86-64 floating point
839 @cindex floating point, x86-64
840 All 80387 floating point types except packed BCD are supported.
841 (BCD support may be added without much difficulty). These data
842 types are 16-, 32-, and 64- bit integers, and single (32-bit),
843 double (64-bit), and extended (80-bit) precision floating point.
844 Each supported type has an instruction mnemonic suffix and a constructor
845 associated with it. Instruction mnemonic suffixes specify the operand's
846 data type. Constructors build these data types into memory.
848 @cindex @code{float} directive, i386
849 @cindex @code{single} directive, i386
850 @cindex @code{double} directive, i386
851 @cindex @code{tfloat} directive, i386
852 @cindex @code{float} directive, x86-64
853 @cindex @code{single} directive, x86-64
854 @cindex @code{double} directive, x86-64
855 @cindex @code{tfloat} directive, x86-64
858 Floating point constructors are @samp{.float} or @samp{.single},
859 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
860 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
861 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
862 only supports this format via the @samp{fldt} (load 80-bit real to stack
863 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
865 @cindex @code{word} directive, i386
866 @cindex @code{long} directive, i386
867 @cindex @code{int} directive, i386
868 @cindex @code{quad} directive, i386
869 @cindex @code{word} directive, x86-64
870 @cindex @code{long} directive, x86-64
871 @cindex @code{int} directive, x86-64
872 @cindex @code{quad} directive, x86-64
874 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
875 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
876 corresponding instruction mnemonic suffixes are @samp{s} (single),
877 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
878 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
879 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
883 Register to register operations should not use instruction mnemonic suffixes.
884 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
885 wrote @samp{fst %st, %st(1)}, since all register to register operations
886 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
887 which converts @samp{%st} from 80-bit to 64-bit floating point format,
888 then stores the result in the 4 byte location @samp{mem})
891 @section Intel's MMX and AMD's 3DNow! SIMD Operations
897 @cindex 3DNow!, x86-64
900 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
901 instructions for integer data), available on Intel's Pentium MMX
902 processors and Pentium II processors, AMD's K6 and K6-2 processors,
903 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
904 instruction set (SIMD instructions for 32-bit floating point data)
905 available on AMD's K6-2 processor and possibly others in the future.
907 Currently, @code{@value{AS}} does not support Intel's floating point
910 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
911 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
912 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
913 floating point values. The MMX registers cannot be used at the same time
914 as the floating point stack.
916 See Intel and AMD documentation, keeping in mind that the operand order in
917 instructions is reversed from the Intel syntax.
920 @section AMD's Lightweight Profiling Instructions
925 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
926 instruction set, available on AMD's Family 15h (Orochi) processors.
928 LWP enables applications to collect and manage performance data, and
929 react to performance events. The collection of performance data
930 requires no context switches. LWP runs in the context of a thread and
931 so several counters can be used independently across multiple threads.
932 LWP can be used in both 64-bit and legacy 32-bit modes.
934 For detailed information on the LWP instruction set, see the
935 @cite{AMD Lightweight Profiling Specification} available at
936 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
939 @section Bit Manipulation Instructions
944 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
946 BMI instructions provide several instructions implementing individual
947 bit manipulation operations such as isolation, masking, setting, or
950 @c Need to add a specification citation here when available.
953 @section AMD's Trailing Bit Manipulation Instructions
958 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
959 instruction set, available on AMD's BDVER2 processors (Trinity and
962 TBM instructions provide instructions implementing individual bit
963 manipulation operations such as isolating, masking, setting, resetting,
964 complementing, and operations on trailing zeros and ones.
966 @c Need to add a specification citation here when available.
969 @section Writing 16-bit Code
971 @cindex i386 16-bit code
972 @cindex 16-bit code, i386
973 @cindex real-mode code, i386
974 @cindex @code{code16gcc} directive, i386
975 @cindex @code{code16} directive, i386
976 @cindex @code{code32} directive, i386
977 @cindex @code{code64} directive, i386
978 @cindex @code{code64} directive, x86-64
979 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
980 or 64-bit x86-64 code depending on the default configuration,
981 it also supports writing code to run in real mode or in 16-bit protected
982 mode code segments. To do this, put a @samp{.code16} or
983 @samp{.code16gcc} directive before the assembly language instructions to
984 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
985 32-bit code with the @samp{.code32} directive or 64-bit code with the
986 @samp{.code64} directive.
988 @samp{.code16gcc} provides experimental support for generating 16-bit
989 code from gcc, and differs from @samp{.code16} in that @samp{call},
990 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
991 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
992 default to 32-bit size. This is so that the stack pointer is
993 manipulated in the same way over function calls, allowing access to
994 function parameters at the same stack offsets as in 32-bit mode.
995 @samp{.code16gcc} also automatically adds address size prefixes where
996 necessary to use the 32-bit addressing modes that gcc generates.
998 The code which @code{@value{AS}} generates in 16-bit mode will not
999 necessarily run on a 16-bit pre-80386 processor. To write code that
1000 runs on such a processor, you must refrain from using @emph{any} 32-bit
1001 constructs which require @code{@value{AS}} to output address or operand
1004 Note that writing 16-bit code instructions by explicitly specifying a
1005 prefix or an instruction mnemonic suffix within a 32-bit code section
1006 generates different machine instructions than those generated for a
1007 16-bit code segment. In a 32-bit code section, the following code
1008 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1009 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1015 The same code in a 16-bit code section would generate the machine
1016 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1017 is correct since the processor default operand size is assumed to be 16
1018 bits in a 16-bit code section.
1021 @section AT&T Syntax bugs
1023 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1024 assemblers, generate floating point instructions with reversed source
1025 and destination registers in certain cases. Unfortunately, gcc and
1026 possibly many other programs use this reversed syntax, so we're stuck
1035 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1036 than the expected @samp{%st(3) - %st}. This happens with all the
1037 non-commutative arithmetic floating point operations with two register
1038 operands where the source register is @samp{%st} and the destination
1039 register is @samp{%st(i)}.
1042 @section Specifying CPU Architecture
1044 @cindex arch directive, i386
1045 @cindex i386 arch directive
1046 @cindex arch directive, x86-64
1047 @cindex x86-64 arch directive
1049 @code{@value{AS}} may be told to assemble for a particular CPU
1050 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1051 directive enables a warning when gas detects an instruction that is not
1052 supported on the CPU specified. The choices for @var{cpu_type} are:
1054 @multitable @columnfractions .20 .20 .20 .20
1055 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1056 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1057 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1058 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1059 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1060 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1061 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1062 @item @samp{bdver4} @tab @samp{btver1} @tab @samp{btver2}
1063 @item @samp{generic32} @tab @samp{generic64}
1064 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1065 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1066 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1067 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1068 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1069 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1070 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1071 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1072 @item @samp{.smap} @tab @samp{.mpx}
1073 @item @samp{.smap} @tab @samp{.sha}
1074 @item @samp{.smap} @tab @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves}
1075 @item @samp{.smap} @tab @samp{.prefetchwt1}
1076 @item @samp{.smap} @tab @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq}
1077 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1078 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1079 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1080 @item @samp{.padlock}
1081 @item @samp{.smap} @tab @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er}
1082 @item @samp{.avx512pf} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a}
1083 @item @samp{.sse5} @tab @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1084 @item @samp{.abm} @tab @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
1085 @item @samp{.cx16} @tab @samp{.padlock}
1088 Apart from the warning, there are only two other effects on
1089 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1090 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1091 will automatically use a two byte opcode sequence. The larger three
1092 byte opcode sequence is used on the 486 (and when no architecture is
1093 specified) because it executes faster on the 486. Note that you can
1094 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1095 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1096 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1097 conditional jumps will be promoted when necessary to a two instruction
1098 sequence consisting of a conditional jump of the opposite sense around
1099 an unconditional jump to the target.
1101 Following the CPU architecture (but not a sub-architecture, which are those
1102 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1103 control automatic promotion of conditional jumps. @samp{jumps} is the
1104 default, and enables jump promotion; All external jumps will be of the long
1105 variety, and file-local jumps will be promoted as necessary.
1106 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1107 byte offset jumps, and warns about file-local conditional jumps that
1108 @code{@value{AS}} promotes.
1109 Unconditional jumps are treated as for @samp{jumps}.
1120 @cindex i386 @code{mul}, @code{imul} instructions
1121 @cindex @code{mul} instruction, i386
1122 @cindex @code{imul} instruction, i386
1123 @cindex @code{mul} instruction, x86-64
1124 @cindex @code{imul} instruction, x86-64
1125 There is some trickery concerning the @samp{mul} and @samp{imul}
1126 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1127 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1128 for @samp{imul}) can be output only in the one operand form. Thus,
1129 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1130 the expanding multiply would clobber the @samp{%edx} register, and this
1131 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1132 64-bit product in @samp{%edx:%eax}.
1134 We have added a two operand form of @samp{imul} when the first operand
1135 is an immediate mode expression and the second operand is a register.
1136 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1137 example, can be done with @samp{imul $69, %eax} rather than @samp{imul