1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
2 @c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
11 @chapter 80386 Dependent Features
14 @node Machine Dependencies
15 @chapter 80386 Dependent Features
19 @cindex i80386 support
20 @cindex x86-64 support
22 The i386 version @code{@value{AS}} supports both the original Intel 386
23 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
24 extending the Intel architecture to 64-bits.
27 * i386-Options:: Options
28 * i386-Directives:: X86 specific directives
29 * i386-Syntax:: Syntactical considerations
30 * i386-Mnemonics:: Instruction Naming
31 * i386-Regs:: Register Naming
32 * i386-Prefixes:: Instruction Prefixes
33 * i386-Memory:: Memory References
34 * i386-Jumps:: Handling of Jump Instructions
35 * i386-Float:: Floating Point
36 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
37 * i386-LWP:: AMD's Lightweight Profiling Instructions
38 * i386-BMI:: Bit Manipulation Instruction
39 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
40 * i386-16bit:: Writing 16-bit Code
41 * i386-Arch:: Specifying an x86 CPU architecture
42 * i386-Bugs:: AT&T Syntax bugs
49 @cindex options for i386
50 @cindex options for x86-64
52 @cindex x86-64 options
54 The i386 version of @code{@value{AS}} has a few machine
59 @cindex @samp{--32} option, i386
60 @cindex @samp{--32} option, x86-64
61 @cindex @samp{--x32} option, i386
62 @cindex @samp{--x32} option, x86-64
63 @cindex @samp{--64} option, i386
64 @cindex @samp{--64} option, x86-64
65 @item --32 | --x32 | --64
66 Select the word size, either 32 bits or 64 bits. @samp{--32}
67 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
68 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
71 These options are only available with the ELF object file format, and
72 require that the necessary BFD support has been included (on a 32-bit
73 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
74 usage and use x86-64 as target platform).
77 By default, x86 GAS replaces multiple nop instructions used for
78 alignment within code sections with multi-byte nop instructions such
79 as leal 0(%esi,1),%esi. This switch disables the optimization.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
126 In addition to the basic instruction set, the assembler can be told to
127 accept various extension mnemonics. For example,
128 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
129 @var{vmx}. The following extensions are currently supported:
176 Note that rather than extending a basic instruction set, the extension
177 mnemonics starting with @code{no} revoke the respective functionality.
179 When the @code{.arch} directive is used with @option{-march}, the
180 @code{.arch} directive will take precedent.
182 @cindex @samp{-mtune=} option, i386
183 @cindex @samp{-mtune=} option, x86-64
184 @item -mtune=@var{CPU}
185 This option specifies a processor to optimize for. When used in
186 conjunction with the @option{-march} option, only instructions
187 of the processor specified by the @option{-march} option will be
190 Valid @var{CPU} values are identical to the processor list of
191 @option{-march=@var{CPU}}.
193 @cindex @samp{-msse2avx} option, i386
194 @cindex @samp{-msse2avx} option, x86-64
196 This option specifies that the assembler should encode SSE instructions
199 @cindex @samp{-msse-check=} option, i386
200 @cindex @samp{-msse-check=} option, x86-64
201 @item -msse-check=@var{none}
202 @itemx -msse-check=@var{warning}
203 @itemx -msse-check=@var{error}
204 These options control if the assembler should check SSE intructions.
205 @option{-msse-check=@var{none}} will make the assembler not to check SSE
206 instructions, which is the default. @option{-msse-check=@var{warning}}
207 will make the assembler issue a warning for any SSE intruction.
208 @option{-msse-check=@var{error}} will make the assembler issue an error
209 for any SSE intruction.
211 @cindex @samp{-mavxscalar=} option, i386
212 @cindex @samp{-mavxscalar=} option, x86-64
213 @item -mavxscalar=@var{128}
214 @itemx -mavxscalar=@var{256}
215 These options control how the assembler should encode scalar AVX
216 instructions. @option{-mavxscalar=@var{128}} will encode scalar
217 AVX instructions with 128bit vector length, which is the default.
218 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
219 with 256bit vector length.
221 @cindex @samp{-mmnemonic=} option, i386
222 @cindex @samp{-mmnemonic=} option, x86-64
223 @item -mmnemonic=@var{att}
224 @itemx -mmnemonic=@var{intel}
225 This option specifies instruction mnemonic for matching instructions.
226 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
229 @cindex @samp{-msyntax=} option, i386
230 @cindex @samp{-msyntax=} option, x86-64
231 @item -msyntax=@var{att}
232 @itemx -msyntax=@var{intel}
233 This option specifies instruction syntax when processing instructions.
234 The @code{.att_syntax} and @code{.intel_syntax} directives will
237 @cindex @samp{-mnaked-reg} option, i386
238 @cindex @samp{-mnaked-reg} option, x86-64
240 This opetion specifies that registers don't require a @samp{%} prefix.
241 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
246 @node i386-Directives
247 @section x86 specific Directives
249 @cindex machine directives, x86
250 @cindex x86 machine directives
253 @cindex @code{lcomm} directive, COFF
254 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
255 Reserve @var{length} (an absolute expression) bytes for a local common
256 denoted by @var{symbol}. The section and value of @var{symbol} are
257 those of the new local common. The addresses are allocated in the bss
258 section, so that at run-time the bytes start off zeroed. Since
259 @var{symbol} is not declared global, it is normally not visible to
260 @code{@value{LD}}. The optional third parameter, @var{alignment},
261 specifies the desired alignment of the symbol in the bss section.
263 This directive is only available for COFF based x86 targets.
265 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
271 @section i386 Syntactical Considerations
273 * i386-Variations:: AT&T Syntax versus Intel Syntax
274 * i386-Chars:: Special Characters
277 @node i386-Variations
278 @subsection AT&T Syntax versus Intel Syntax
280 @cindex i386 intel_syntax pseudo op
281 @cindex intel_syntax pseudo op, i386
282 @cindex i386 att_syntax pseudo op
283 @cindex att_syntax pseudo op, i386
284 @cindex i386 syntax compatibility
285 @cindex syntax compatibility, i386
286 @cindex x86-64 intel_syntax pseudo op
287 @cindex intel_syntax pseudo op, x86-64
288 @cindex x86-64 att_syntax pseudo op
289 @cindex att_syntax pseudo op, x86-64
290 @cindex x86-64 syntax compatibility
291 @cindex syntax compatibility, x86-64
293 @code{@value{AS}} now supports assembly using Intel assembler syntax.
294 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
295 back to the usual AT&T mode for compatibility with the output of
296 @code{@value{GCC}}. Either of these directives may have an optional
297 argument, @code{prefix}, or @code{noprefix} specifying whether registers
298 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
299 different from Intel syntax. We mention these differences because
300 almost all 80386 documents use Intel syntax. Notable differences
301 between the two syntaxes are:
303 @cindex immediate operands, i386
304 @cindex i386 immediate operands
305 @cindex register operands, i386
306 @cindex i386 register operands
307 @cindex jump/call operands, i386
308 @cindex i386 jump/call operands
309 @cindex operand delimiters, i386
311 @cindex immediate operands, x86-64
312 @cindex x86-64 immediate operands
313 @cindex register operands, x86-64
314 @cindex x86-64 register operands
315 @cindex jump/call operands, x86-64
316 @cindex x86-64 jump/call operands
317 @cindex operand delimiters, x86-64
320 AT&T immediate operands are preceded by @samp{$}; Intel immediate
321 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
322 AT&T register operands are preceded by @samp{%}; Intel register operands
323 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
324 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
326 @cindex i386 source, destination operands
327 @cindex source, destination operands; i386
328 @cindex x86-64 source, destination operands
329 @cindex source, destination operands; x86-64
331 AT&T and Intel syntax use the opposite order for source and destination
332 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
333 @samp{source, dest} convention is maintained for compatibility with
334 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
335 instructions with 2 immediate operands, such as the @samp{enter}
336 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
338 @cindex mnemonic suffixes, i386
339 @cindex sizes operands, i386
340 @cindex i386 size suffixes
341 @cindex mnemonic suffixes, x86-64
342 @cindex sizes operands, x86-64
343 @cindex x86-64 size suffixes
345 In AT&T syntax the size of memory operands is determined from the last
346 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
347 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
348 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
349 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
350 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
351 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
354 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
355 instruction with the 64-bit displacement or immediate operand.
357 @cindex return instructions, i386
358 @cindex i386 jump, call, return
359 @cindex return instructions, x86-64
360 @cindex x86-64 jump, call, return
362 Immediate form long jumps and calls are
363 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
365 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
367 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
368 @samp{ret far @var{stack-adjust}}.
370 @cindex sections, i386
371 @cindex i386 sections
372 @cindex sections, x86-64
373 @cindex x86-64 sections
375 The AT&T assembler does not provide support for multiple section
376 programs. Unix style systems expect all programs to be single sections.
380 @subsection Special Characters
382 @cindex line comment character, i386
383 @cindex i386 line comment character
384 The presence of a @samp{#} appearing anywhere on a line indicates the
385 start of a comment that extends to the end of that line.
387 If a @samp{#} appears as the first character of a line then the whole
388 line is treated as a comment, but in this case the line can also be a
389 logical line number directive (@pxref{Comments}) or a preprocessor
390 control command (@pxref{Preprocessing}).
392 If the @option{--divide} command line option has not been specified
393 then the @samp{/} character appearing anywhere on a line also
394 introduces a line comment.
396 @cindex line separator, i386
397 @cindex statement separator, i386
398 @cindex i386 line separator
399 The @samp{;} character can be used to separate statements on the same
403 @section Instruction Naming
405 @cindex i386 instruction naming
406 @cindex instruction naming, i386
407 @cindex x86-64 instruction naming
408 @cindex instruction naming, x86-64
410 Instruction mnemonics are suffixed with one character modifiers which
411 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
412 and @samp{q} specify byte, word, long and quadruple word operands. If
413 no suffix is specified by an instruction then @code{@value{AS}} tries to
414 fill in the missing suffix based on the destination register operand
415 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
416 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
417 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
418 assembler which assumes that a missing mnemonic suffix implies long
419 operand size. (This incompatibility does not affect compiler output
420 since compilers always explicitly specify the mnemonic suffix.)
422 Almost all instructions have the same names in AT&T and Intel format.
423 There are a few exceptions. The sign extend and zero extend
424 instructions need two sizes to specify them. They need a size to
425 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
426 is accomplished by using two instruction mnemonic suffixes in AT&T
427 syntax. Base names for sign extend and zero extend are
428 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
429 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
430 are tacked on to this base name, the @emph{from} suffix before the
431 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
432 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
433 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
434 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
435 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
438 @cindex encoding options, i386
439 @cindex encoding options, x86-64
441 Different encoding options can be specified via optional mnemonic
442 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
443 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
444 prefers 8bit or 32bit displacement in encoding.
446 @cindex conversion instructions, i386
447 @cindex i386 conversion instructions
448 @cindex conversion instructions, x86-64
449 @cindex x86-64 conversion instructions
450 The Intel-syntax conversion instructions
454 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
457 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
460 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
463 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
466 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
470 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
471 @samp{%rdx:%rax} (x86-64 only),
475 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
476 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
479 @cindex jump instructions, i386
480 @cindex call instructions, i386
481 @cindex jump instructions, x86-64
482 @cindex call instructions, x86-64
483 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
484 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
487 @section AT&T Mnemonic versus Intel Mnemonic
489 @cindex i386 mnemonic compatibility
490 @cindex mnemonic compatibility, i386
492 @code{@value{AS}} supports assembly using Intel mnemonic.
493 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
494 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
495 syntax for compatibility with the output of @code{@value{GCC}}.
496 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
497 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
498 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
499 assembler with different mnemonics from those in Intel IA32 specification.
500 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
503 @section Register Naming
505 @cindex i386 registers
506 @cindex registers, i386
507 @cindex x86-64 registers
508 @cindex registers, x86-64
509 Register operands are always prefixed with @samp{%}. The 80386 registers
514 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
515 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
516 frame pointer), and @samp{%esp} (the stack pointer).
519 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
520 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
523 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
524 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
525 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
526 @samp{%cx}, and @samp{%dx})
529 the 6 section registers @samp{%cs} (code section), @samp{%ds}
530 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
534 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
538 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
539 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
542 the 2 test registers @samp{%tr6} and @samp{%tr7}.
545 the 8 floating point register stack @samp{%st} or equivalently
546 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
547 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
548 These registers are overloaded by 8 MMX registers @samp{%mm0},
549 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
550 @samp{%mm6} and @samp{%mm7}.
553 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
554 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
557 The AMD x86-64 architecture extends the register set by:
561 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
562 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
563 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
567 the 8 extended registers @samp{%r8}--@samp{%r15}.
570 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
573 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
576 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
579 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
582 the 8 debug registers: @samp{%db8}--@samp{%db15}.
585 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
589 @section Instruction Prefixes
591 @cindex i386 instruction prefixes
592 @cindex instruction prefixes, i386
593 @cindex prefixes, i386
594 Instruction prefixes are used to modify the following instruction. They
595 are used to repeat string instructions, to provide section overrides, to
596 perform bus lock operations, and to change operand and address sizes.
597 (Most instructions that normally operate on 32-bit operands will use
598 16-bit operands if the instruction has an ``operand size'' prefix.)
599 Instruction prefixes are best written on the same line as the instruction
600 they act upon. For example, the @samp{scas} (scan string) instruction is
604 repne scas %es:(%edi),%al
607 You may also place prefixes on the lines immediately preceding the
608 instruction, but this circumvents checks that @code{@value{AS}} does
609 with prefixes, and will not work with all prefixes.
611 Here is a list of instruction prefixes:
613 @cindex section override prefixes, i386
616 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
617 @samp{fs}, @samp{gs}. These are automatically added by specifying
618 using the @var{section}:@var{memory-operand} form for memory references.
620 @cindex size prefixes, i386
622 Operand/Address size prefixes @samp{data16} and @samp{addr16}
623 change 32-bit operands/addresses into 16-bit operands/addresses,
624 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
625 @code{.code16} section) into 32-bit operands/addresses. These prefixes
626 @emph{must} appear on the same line of code as the instruction they
627 modify. For example, in a 16-bit @code{.code16} section, you might
634 @cindex bus lock prefixes, i386
635 @cindex inhibiting interrupts, i386
637 The bus lock prefix @samp{lock} inhibits interrupts during execution of
638 the instruction it precedes. (This is only valid with certain
639 instructions; see a 80386 manual for details).
641 @cindex coprocessor wait, i386
643 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
644 complete the current instruction. This should never be needed for the
645 80386/80387 combination.
647 @cindex repeat prefixes, i386
649 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
650 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
651 times if the current address size is 16-bits).
652 @cindex REX prefixes, i386
654 The @samp{rex} family of prefixes is used by x86-64 to encode
655 extensions to i386 instruction set. The @samp{rex} prefix has four
656 bits --- an operand size overwrite (@code{64}) used to change operand size
657 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
660 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
661 instruction emits @samp{rex} prefix with all the bits set. By omitting
662 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
663 prefixes as well. Normally, there is no need to write the prefixes
664 explicitly, since gas will automatically generate them based on the
665 instruction operands.
669 @section Memory References
671 @cindex i386 memory references
672 @cindex memory references, i386
673 @cindex x86-64 memory references
674 @cindex memory references, x86-64
675 An Intel syntax indirect memory reference of the form
678 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
682 is translated into the AT&T syntax
685 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
689 where @var{base} and @var{index} are the optional 32-bit base and
690 index registers, @var{disp} is the optional displacement, and
691 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
692 to calculate the address of the operand. If no @var{scale} is
693 specified, @var{scale} is taken to be 1. @var{section} specifies the
694 optional section register for the memory operand, and may override the
695 default section register (see a 80386 manual for section register
696 defaults). Note that section overrides in AT&T syntax @emph{must}
697 be preceded by a @samp{%}. If you specify a section override which
698 coincides with the default section register, @code{@value{AS}} does @emph{not}
699 output any section register override prefixes to assemble the given
700 instruction. Thus, section overrides can be specified to emphasize which
701 section register is used for a given memory operand.
703 Here are some examples of Intel and AT&T style memory references:
706 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
707 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
708 missing, and the default section is used (@samp{%ss} for addressing with
709 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
711 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
712 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
713 @samp{foo}. All other fields are missing. The section register here
714 defaults to @samp{%ds}.
716 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
717 This uses the value pointed to by @samp{foo} as a memory operand.
718 Note that @var{base} and @var{index} are both missing, but there is only
719 @emph{one} @samp{,}. This is a syntactic exception.
721 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
722 This selects the contents of the variable @samp{foo} with section
723 register @var{section} being @samp{%gs}.
726 Absolute (as opposed to PC relative) call and jump operands must be
727 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
728 always chooses PC relative addressing for jump/call labels.
730 Any instruction that has a memory operand, but no register operand,
731 @emph{must} specify its size (byte, word, long, or quadruple) with an
732 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
735 The x86-64 architecture adds an RIP (instruction pointer relative)
736 addressing. This addressing mode is specified by using @samp{rip} as a
737 base register. Only constant offsets are valid. For example:
740 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
741 Points to the address 1234 bytes past the end of the current
744 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
745 Points to the @code{symbol} in RIP relative way, this is shorter than
746 the default absolute addressing.
749 Other addressing modes remain unchanged in x86-64 architecture, except
750 registers used are 64-bit instead of 32-bit.
753 @section Handling of Jump Instructions
755 @cindex jump optimization, i386
756 @cindex i386 jump optimization
757 @cindex jump optimization, x86-64
758 @cindex x86-64 jump optimization
759 Jump instructions are always optimized to use the smallest possible
760 displacements. This is accomplished by using byte (8-bit) displacement
761 jumps whenever the target is sufficiently close. If a byte displacement
762 is insufficient a long displacement is used. We do not support
763 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
764 instruction with the @samp{data16} instruction prefix), since the 80386
765 insists upon masking @samp{%eip} to 16 bits after the word displacement
766 is added. (See also @pxref{i386-Arch})
768 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
769 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
770 displacements, so that if you use these instructions (@code{@value{GCC}} does
771 not use them) you may get an error message (and incorrect code). The AT&T
772 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
783 @section Floating Point
785 @cindex i386 floating point
786 @cindex floating point, i386
787 @cindex x86-64 floating point
788 @cindex floating point, x86-64
789 All 80387 floating point types except packed BCD are supported.
790 (BCD support may be added without much difficulty). These data
791 types are 16-, 32-, and 64- bit integers, and single (32-bit),
792 double (64-bit), and extended (80-bit) precision floating point.
793 Each supported type has an instruction mnemonic suffix and a constructor
794 associated with it. Instruction mnemonic suffixes specify the operand's
795 data type. Constructors build these data types into memory.
797 @cindex @code{float} directive, i386
798 @cindex @code{single} directive, i386
799 @cindex @code{double} directive, i386
800 @cindex @code{tfloat} directive, i386
801 @cindex @code{float} directive, x86-64
802 @cindex @code{single} directive, x86-64
803 @cindex @code{double} directive, x86-64
804 @cindex @code{tfloat} directive, x86-64
807 Floating point constructors are @samp{.float} or @samp{.single},
808 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
809 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
810 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
811 only supports this format via the @samp{fldt} (load 80-bit real to stack
812 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
814 @cindex @code{word} directive, i386
815 @cindex @code{long} directive, i386
816 @cindex @code{int} directive, i386
817 @cindex @code{quad} directive, i386
818 @cindex @code{word} directive, x86-64
819 @cindex @code{long} directive, x86-64
820 @cindex @code{int} directive, x86-64
821 @cindex @code{quad} directive, x86-64
823 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
824 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
825 corresponding instruction mnemonic suffixes are @samp{s} (single),
826 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
827 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
828 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
832 Register to register operations should not use instruction mnemonic suffixes.
833 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
834 wrote @samp{fst %st, %st(1)}, since all register to register operations
835 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
836 which converts @samp{%st} from 80-bit to 64-bit floating point format,
837 then stores the result in the 4 byte location @samp{mem})
840 @section Intel's MMX and AMD's 3DNow! SIMD Operations
846 @cindex 3DNow!, x86-64
849 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
850 instructions for integer data), available on Intel's Pentium MMX
851 processors and Pentium II processors, AMD's K6 and K6-2 processors,
852 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
853 instruction set (SIMD instructions for 32-bit floating point data)
854 available on AMD's K6-2 processor and possibly others in the future.
856 Currently, @code{@value{AS}} does not support Intel's floating point
859 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
860 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
861 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
862 floating point values. The MMX registers cannot be used at the same time
863 as the floating point stack.
865 See Intel and AMD documentation, keeping in mind that the operand order in
866 instructions is reversed from the Intel syntax.
869 @section AMD's Lightweight Profiling Instructions
874 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
875 instruction set, available on AMD's Family 15h (Orochi) processors.
877 LWP enables applications to collect and manage performance data, and
878 react to performance events. The collection of performance data
879 requires no context switches. LWP runs in the context of a thread and
880 so several counters can be used independently across multiple threads.
881 LWP can be used in both 64-bit and legacy 32-bit modes.
883 For detailed information on the LWP instruction set, see the
884 @cite{AMD Lightweight Profiling Specification} available at
885 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
888 @section Bit Manipulation Instructions
893 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
895 BMI instructions provide several instructions implementing individual
896 bit manipulation operations such as isolation, masking, setting, or
899 @c Need to add a specification citation here when available.
902 @section AMD's Trailing Bit Manipulation Instructions
907 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
908 instruction set, available on AMD's BDVER2 processors (Trinity and
911 TBM instructions provide instructions implementing individual bit
912 manipulation operations such as isolating, masking, setting, resetting,
913 complementing, and operations on trailing zeros and ones.
915 @c Need to add a specification citation here when available.
918 @section Writing 16-bit Code
920 @cindex i386 16-bit code
921 @cindex 16-bit code, i386
922 @cindex real-mode code, i386
923 @cindex @code{code16gcc} directive, i386
924 @cindex @code{code16} directive, i386
925 @cindex @code{code32} directive, i386
926 @cindex @code{code64} directive, i386
927 @cindex @code{code64} directive, x86-64
928 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
929 or 64-bit x86-64 code depending on the default configuration,
930 it also supports writing code to run in real mode or in 16-bit protected
931 mode code segments. To do this, put a @samp{.code16} or
932 @samp{.code16gcc} directive before the assembly language instructions to
933 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
934 32-bit code with the @samp{.code32} directive or 64-bit code with the
935 @samp{.code64} directive.
937 @samp{.code16gcc} provides experimental support for generating 16-bit
938 code from gcc, and differs from @samp{.code16} in that @samp{call},
939 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
940 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
941 default to 32-bit size. This is so that the stack pointer is
942 manipulated in the same way over function calls, allowing access to
943 function parameters at the same stack offsets as in 32-bit mode.
944 @samp{.code16gcc} also automatically adds address size prefixes where
945 necessary to use the 32-bit addressing modes that gcc generates.
947 The code which @code{@value{AS}} generates in 16-bit mode will not
948 necessarily run on a 16-bit pre-80386 processor. To write code that
949 runs on such a processor, you must refrain from using @emph{any} 32-bit
950 constructs which require @code{@value{AS}} to output address or operand
953 Note that writing 16-bit code instructions by explicitly specifying a
954 prefix or an instruction mnemonic suffix within a 32-bit code section
955 generates different machine instructions than those generated for a
956 16-bit code segment. In a 32-bit code section, the following code
957 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
958 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
964 The same code in a 16-bit code section would generate the machine
965 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
966 is correct since the processor default operand size is assumed to be 16
967 bits in a 16-bit code section.
970 @section AT&T Syntax bugs
972 The UnixWare assembler, and probably other AT&T derived ix86 Unix
973 assemblers, generate floating point instructions with reversed source
974 and destination registers in certain cases. Unfortunately, gcc and
975 possibly many other programs use this reversed syntax, so we're stuck
984 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
985 than the expected @samp{%st(3) - %st}. This happens with all the
986 non-commutative arithmetic floating point operations with two register
987 operands where the source register is @samp{%st} and the destination
988 register is @samp{%st(i)}.
991 @section Specifying CPU Architecture
993 @cindex arch directive, i386
994 @cindex i386 arch directive
995 @cindex arch directive, x86-64
996 @cindex x86-64 arch directive
998 @code{@value{AS}} may be told to assemble for a particular CPU
999 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1000 directive enables a warning when gas detects an instruction that is not
1001 supported on the CPU specified. The choices for @var{cpu_type} are:
1003 @multitable @columnfractions .20 .20 .20 .20
1004 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1005 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1006 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1007 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1008 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1009 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1010 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2}
1011 @item @samp{generic32} @tab @samp{generic64}
1012 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1013 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1014 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1015 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1016 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1017 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1018 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
1019 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1020 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1021 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
1022 @item @samp{.padlock}
1025 Apart from the warning, there are only two other effects on
1026 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1027 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1028 will automatically use a two byte opcode sequence. The larger three
1029 byte opcode sequence is used on the 486 (and when no architecture is
1030 specified) because it executes faster on the 486. Note that you can
1031 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1032 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1033 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1034 conditional jumps will be promoted when necessary to a two instruction
1035 sequence consisting of a conditional jump of the opposite sense around
1036 an unconditional jump to the target.
1038 Following the CPU architecture (but not a sub-architecture, which are those
1039 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1040 control automatic promotion of conditional jumps. @samp{jumps} is the
1041 default, and enables jump promotion; All external jumps will be of the long
1042 variety, and file-local jumps will be promoted as necessary.
1043 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1044 byte offset jumps, and warns about file-local conditional jumps that
1045 @code{@value{AS}} promotes.
1046 Unconditional jumps are treated as for @samp{jumps}.
1057 @cindex i386 @code{mul}, @code{imul} instructions
1058 @cindex @code{mul} instruction, i386
1059 @cindex @code{imul} instruction, i386
1060 @cindex @code{mul} instruction, x86-64
1061 @cindex @code{imul} instruction, x86-64
1062 There is some trickery concerning the @samp{mul} and @samp{imul}
1063 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1064 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1065 for @samp{imul}) can be output only in the one operand form. Thus,
1066 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1067 the expanding multiply would clobber the @samp{%edx} register, and this
1068 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1069 64-bit product in @samp{%edx:%eax}.
1071 We have added a two operand form of @samp{imul} when the first operand
1072 is an immediate mode expression and the second operand is a register.
1073 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1074 example, can be done with @samp{imul $69, %eax} rather than @samp{imul