1 @c Copyright (C) 1991-2020 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-ISA:: AMD64 ISA vs. Intel64 ISA
41 * i386-Bugs:: AT&T Syntax bugs
48 @cindex options for i386
49 @cindex options for x86-64
51 @cindex x86-64 options
53 The i386 version of @code{@value{AS}} has a few machine
58 @cindex @samp{--32} option, i386
59 @cindex @samp{--32} option, x86-64
60 @cindex @samp{--x32} option, i386
61 @cindex @samp{--x32} option, x86-64
62 @cindex @samp{--64} option, i386
63 @cindex @samp{--64} option, x86-64
64 @item --32 | --x32 | --64
65 Select the word size, either 32 bits or 64 bits. @samp{--32}
66 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
67 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
70 These options are only available with the ELF object file format, and
71 require that the necessary BFD support has been included (on a 32-bit
72 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
73 usage and use x86-64 as target platform).
76 By default, x86 GAS replaces multiple nop instructions used for
77 alignment within code sections with multi-byte nop instructions such
78 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
79 byte nop (0x90) is explicitly specified as the fill byte for alignment.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
133 In addition to the basic instruction set, the assembler can be told to
134 accept various extension mnemonics. For example,
135 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
136 @var{vmx}. The following extensions are currently supported:
197 @code{avx512_4fmaps},
198 @code{avx512_4vnniw},
199 @code{avx512_vpopcntdq},
202 @code{avx512_bitalg},
213 @code{noavx512_4fmaps},
214 @code{noavx512_4vnniw},
215 @code{noavx512_vpopcntdq},
216 @code{noavx512_vbmi2},
217 @code{noavx512_vnni},
218 @code{noavx512_bitalg},
219 @code{noavx512_vp2intersect},
220 @code{noavx512_bf16},
264 Note that rather than extending a basic instruction set, the extension
265 mnemonics starting with @code{no} revoke the respective functionality.
267 When the @code{.arch} directive is used with @option{-march}, the
268 @code{.arch} directive will take precedent.
270 @cindex @samp{-mtune=} option, i386
271 @cindex @samp{-mtune=} option, x86-64
272 @item -mtune=@var{CPU}
273 This option specifies a processor to optimize for. When used in
274 conjunction with the @option{-march} option, only instructions
275 of the processor specified by the @option{-march} option will be
278 Valid @var{CPU} values are identical to the processor list of
279 @option{-march=@var{CPU}}.
281 @cindex @samp{-msse2avx} option, i386
282 @cindex @samp{-msse2avx} option, x86-64
284 This option specifies that the assembler should encode SSE instructions
287 @cindex @samp{-msse-check=} option, i386
288 @cindex @samp{-msse-check=} option, x86-64
289 @item -msse-check=@var{none}
290 @itemx -msse-check=@var{warning}
291 @itemx -msse-check=@var{error}
292 These options control if the assembler should check SSE instructions.
293 @option{-msse-check=@var{none}} will make the assembler not to check SSE
294 instructions, which is the default. @option{-msse-check=@var{warning}}
295 will make the assembler issue a warning for any SSE instruction.
296 @option{-msse-check=@var{error}} will make the assembler issue an error
297 for any SSE instruction.
299 @cindex @samp{-mavxscalar=} option, i386
300 @cindex @samp{-mavxscalar=} option, x86-64
301 @item -mavxscalar=@var{128}
302 @itemx -mavxscalar=@var{256}
303 These options control how the assembler should encode scalar AVX
304 instructions. @option{-mavxscalar=@var{128}} will encode scalar
305 AVX instructions with 128bit vector length, which is the default.
306 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
307 with 256bit vector length.
309 WARNING: Don't use this for production code - due to CPU errata the
310 resulting code may not work on certain models.
312 @cindex @samp{-mvexwig=} option, i386
313 @cindex @samp{-mvexwig=} option, x86-64
314 @item -mvexwig=@var{0}
315 @itemx -mvexwig=@var{1}
316 These options control how the assembler should encode VEX.W-ignored (WIG)
317 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
318 instructions with vex.w = 0, which is the default.
319 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
322 WARNING: Don't use this for production code - due to CPU errata the
323 resulting code may not work on certain models.
325 @cindex @samp{-mevexlig=} option, i386
326 @cindex @samp{-mevexlig=} option, x86-64
327 @item -mevexlig=@var{128}
328 @itemx -mevexlig=@var{256}
329 @itemx -mevexlig=@var{512}
330 These options control how the assembler should encode length-ignored
331 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
332 EVEX instructions with 128bit vector length, which is the default.
333 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
334 encode LIG EVEX instructions with 256bit and 512bit vector length,
337 @cindex @samp{-mevexwig=} option, i386
338 @cindex @samp{-mevexwig=} option, x86-64
339 @item -mevexwig=@var{0}
340 @itemx -mevexwig=@var{1}
341 These options control how the assembler should encode w-ignored (WIG)
342 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
343 EVEX instructions with evex.w = 0, which is the default.
344 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
347 @cindex @samp{-mmnemonic=} option, i386
348 @cindex @samp{-mmnemonic=} option, x86-64
349 @item -mmnemonic=@var{att}
350 @itemx -mmnemonic=@var{intel}
351 This option specifies instruction mnemonic for matching instructions.
352 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
355 @cindex @samp{-msyntax=} option, i386
356 @cindex @samp{-msyntax=} option, x86-64
357 @item -msyntax=@var{att}
358 @itemx -msyntax=@var{intel}
359 This option specifies instruction syntax when processing instructions.
360 The @code{.att_syntax} and @code{.intel_syntax} directives will
363 @cindex @samp{-mnaked-reg} option, i386
364 @cindex @samp{-mnaked-reg} option, x86-64
366 This option specifies that registers don't require a @samp{%} prefix.
367 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
369 @cindex @samp{-madd-bnd-prefix} option, i386
370 @cindex @samp{-madd-bnd-prefix} option, x86-64
371 @item -madd-bnd-prefix
372 This option forces the assembler to add BND prefix to all branches, even
373 if such prefix was not explicitly specified in the source code.
375 @cindex @samp{-mshared} option, i386
376 @cindex @samp{-mshared} option, x86-64
378 On ELF target, the assembler normally optimizes out non-PLT relocations
379 against defined non-weak global branch targets with default visibility.
380 The @samp{-mshared} option tells the assembler to generate code which
381 may go into a shared library where all non-weak global branch targets
382 with default visibility can be preempted. The resulting code is
383 slightly bigger. This option only affects the handling of branch
386 @cindex @samp{-mbig-obj} option, x86-64
388 On x86-64 PE/COFF target this option forces the use of big object file
389 format, which allows more than 32768 sections.
391 @cindex @samp{-momit-lock-prefix=} option, i386
392 @cindex @samp{-momit-lock-prefix=} option, x86-64
393 @item -momit-lock-prefix=@var{no}
394 @itemx -momit-lock-prefix=@var{yes}
395 These options control how the assembler should encode lock prefix.
396 This option is intended as a workaround for processors, that fail on
397 lock prefix. This option can only be safely used with single-core,
398 single-thread computers
399 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
400 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
401 which is the default.
403 @cindex @samp{-mfence-as-lock-add=} option, i386
404 @cindex @samp{-mfence-as-lock-add=} option, x86-64
405 @item -mfence-as-lock-add=@var{no}
406 @itemx -mfence-as-lock-add=@var{yes}
407 These options control how the assembler should encode lfence, mfence and
409 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
410 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
411 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
412 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
413 sfence as usual, which is the default.
415 @cindex @samp{-mrelax-relocations=} option, i386
416 @cindex @samp{-mrelax-relocations=} option, x86-64
417 @item -mrelax-relocations=@var{no}
418 @itemx -mrelax-relocations=@var{yes}
419 These options control whether the assembler should generate relax
420 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
421 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
422 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
423 @option{-mrelax-relocations=@var{no}} will not generate relax
424 relocations. The default can be controlled by a configure option
425 @option{--enable-x86-relax-relocations}.
427 @cindex @samp{-malign-branch-boundary=} option, i386
428 @cindex @samp{-malign-branch-boundary=} option, x86-64
429 @item -malign-branch-boundary=@var{NUM}
430 This option controls how the assembler should align branches with segment
431 prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or
432 no less than 16. Branches will be aligned within @var{NUM} byte
433 boundary. @option{-malign-branch-boundary=0}, which is the default,
434 doesn't align branches.
436 @cindex @samp{-malign-branch=} option, i386
437 @cindex @samp{-malign-branch=} option, x86-64
438 @item -malign-branch=@var{TYPE}[+@var{TYPE}...]
439 This option specifies types of branches to align. @var{TYPE} is
440 combination of @samp{jcc}, which aligns conditional jumps,
441 @samp{fused}, which aligns fused conditional jumps, @samp{jmp},
442 which aligns unconditional jumps, @samp{call} which aligns calls,
443 @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect
444 jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}.
446 @cindex @samp{-malign-branch-prefix-size=} option, i386
447 @cindex @samp{-malign-branch-prefix-size=} option, x86-64
448 @item -malign-branch-prefix-size=@var{NUM}
449 This option specifies the maximum number of prefixes on an instruction
450 to align branches. @var{NUM} should be between 0 and 5. The default
453 @cindex @samp{-mbranches-within-32B-boundaries} option, i386
454 @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64
455 @item -mbranches-within-32B-boundaries
456 This option aligns conditional jumps, fused conditional jumps and
457 unconditional jumps within 32 byte boundary with up to 5 segment prefixes
458 on an instruction. It is equivalent to
459 @option{-malign-branch-boundary=32}
460 @option{-malign-branch=jcc+fused+jmp}
461 @option{-malign-branch-prefix-size=5}.
462 The default doesn't align branches.
464 @cindex @samp{-mx86-used-note=} option, i386
465 @cindex @samp{-mx86-used-note=} option, x86-64
466 @item -mx86-used-note=@var{no}
467 @itemx -mx86-used-note=@var{yes}
468 These options control whether the assembler should generate
469 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
470 GNU property notes. The default can be controlled by the
471 @option{--enable-x86-used-note} configure option.
473 @cindex @samp{-mevexrcig=} option, i386
474 @cindex @samp{-mevexrcig=} option, x86-64
475 @item -mevexrcig=@var{rne}
476 @itemx -mevexrcig=@var{rd}
477 @itemx -mevexrcig=@var{ru}
478 @itemx -mevexrcig=@var{rz}
479 These options control how the assembler should encode SAE-only
480 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
481 of EVEX instruction with 00, which is the default.
482 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
483 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
484 with 01, 10 and 11 RC bits, respectively.
486 @cindex @samp{-mamd64} option, x86-64
487 @cindex @samp{-mintel64} option, x86-64
490 This option specifies that the assembler should accept only AMD64 or
491 Intel64 ISA in 64-bit mode. The default is to accept both.
493 @cindex @samp{-O0} option, i386
494 @cindex @samp{-O0} option, x86-64
495 @cindex @samp{-O} option, i386
496 @cindex @samp{-O} option, x86-64
497 @cindex @samp{-O1} option, i386
498 @cindex @samp{-O1} option, x86-64
499 @cindex @samp{-O2} option, i386
500 @cindex @samp{-O2} option, x86-64
501 @cindex @samp{-Os} option, i386
502 @cindex @samp{-Os} option, x86-64
503 @item -O0 | -O | -O1 | -O2 | -Os
504 Optimize instruction encoding with smaller instruction size. @samp{-O}
505 and @samp{-O1} encode 64-bit register load instructions with 64-bit
506 immediate as 32-bit register load instructions with 31-bit or 32-bits
507 immediates, encode 64-bit register clearing instructions with 32-bit
508 register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
509 register clearing instructions with 128-bit VEX vector register
510 clearing instructions, encode 128-bit/256-bit EVEX vector
511 register load/store instructions with VEX vector register load/store
512 instructions, and encode 128-bit/256-bit EVEX packed integer logical
513 instructions with 128-bit/256-bit VEX packed integer logical.
515 @samp{-O2} includes @samp{-O1} optimization plus encodes
516 256-bit/512-bit EVEX vector register clearing instructions with 128-bit
517 EVEX vector register clearing instructions. In 64-bit mode VEX encoded
518 instructions with commutative source operands will also have their
519 source operands swapped if this allows using the 2-byte VEX prefix form
520 instead of the 3-byte one. Certain forms of AND as well as OR with the
521 same (register) operand specified twice will also be changed to TEST.
523 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
524 and 64-bit register tests with immediate as 8-bit register test with
525 immediate. @samp{-O0} turns off this optimization.
530 @node i386-Directives
531 @section x86 specific Directives
533 @cindex machine directives, x86
534 @cindex x86 machine directives
537 @cindex @code{lcomm} directive, COFF
538 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
539 Reserve @var{length} (an absolute expression) bytes for a local common
540 denoted by @var{symbol}. The section and value of @var{symbol} are
541 those of the new local common. The addresses are allocated in the bss
542 section, so that at run-time the bytes start off zeroed. Since
543 @var{symbol} is not declared global, it is normally not visible to
544 @code{@value{LD}}. The optional third parameter, @var{alignment},
545 specifies the desired alignment of the symbol in the bss section.
547 This directive is only available for COFF based x86 targets.
549 @cindex @code{largecomm} directive, ELF
550 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
551 This directive behaves in the same way as the @code{comm} directive
552 except that the data is placed into the @var{.lbss} section instead of
553 the @var{.bss} section @ref{Comm}.
555 The directive is intended to be used for data which requires a large
556 amount of space, and it is only available for ELF based x86_64
559 @cindex @code{value} directive
560 @item .value @var{expression} [, @var{expression}]
561 This directive behaves in the same way as the @code{.short} directive,
562 taking a series of comma separated expressions and storing them as
563 two-byte wide values into the current section.
565 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
570 @section i386 Syntactical Considerations
572 * i386-Variations:: AT&T Syntax versus Intel Syntax
573 * i386-Chars:: Special Characters
576 @node i386-Variations
577 @subsection AT&T Syntax versus Intel Syntax
579 @cindex i386 intel_syntax pseudo op
580 @cindex intel_syntax pseudo op, i386
581 @cindex i386 att_syntax pseudo op
582 @cindex att_syntax pseudo op, i386
583 @cindex i386 syntax compatibility
584 @cindex syntax compatibility, i386
585 @cindex x86-64 intel_syntax pseudo op
586 @cindex intel_syntax pseudo op, x86-64
587 @cindex x86-64 att_syntax pseudo op
588 @cindex att_syntax pseudo op, x86-64
589 @cindex x86-64 syntax compatibility
590 @cindex syntax compatibility, x86-64
592 @code{@value{AS}} now supports assembly using Intel assembler syntax.
593 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
594 back to the usual AT&T mode for compatibility with the output of
595 @code{@value{GCC}}. Either of these directives may have an optional
596 argument, @code{prefix}, or @code{noprefix} specifying whether registers
597 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
598 different from Intel syntax. We mention these differences because
599 almost all 80386 documents use Intel syntax. Notable differences
600 between the two syntaxes are:
602 @cindex immediate operands, i386
603 @cindex i386 immediate operands
604 @cindex register operands, i386
605 @cindex i386 register operands
606 @cindex jump/call operands, i386
607 @cindex i386 jump/call operands
608 @cindex operand delimiters, i386
610 @cindex immediate operands, x86-64
611 @cindex x86-64 immediate operands
612 @cindex register operands, x86-64
613 @cindex x86-64 register operands
614 @cindex jump/call operands, x86-64
615 @cindex x86-64 jump/call operands
616 @cindex operand delimiters, x86-64
619 AT&T immediate operands are preceded by @samp{$}; Intel immediate
620 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
621 AT&T register operands are preceded by @samp{%}; Intel register operands
622 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
623 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
625 @cindex i386 source, destination operands
626 @cindex source, destination operands; i386
627 @cindex x86-64 source, destination operands
628 @cindex source, destination operands; x86-64
630 AT&T and Intel syntax use the opposite order for source and destination
631 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
632 @samp{source, dest} convention is maintained for compatibility with
633 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
634 instructions with 2 immediate operands, such as the @samp{enter}
635 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
637 @cindex mnemonic suffixes, i386
638 @cindex sizes operands, i386
639 @cindex i386 size suffixes
640 @cindex mnemonic suffixes, x86-64
641 @cindex sizes operands, x86-64
642 @cindex x86-64 size suffixes
644 In AT&T syntax the size of memory operands is determined from the last
645 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
646 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
647 (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
648 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
649 (256-bit vector) and zmm (512-bit vector) memory references, only when there's
650 no other way to disambiguate an instruction. Intel syntax accomplishes this by
651 prefixing memory operands (@emph{not} the instruction mnemonics) with
652 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
653 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
654 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
655 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
656 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
658 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
659 instruction with the 64-bit displacement or immediate operand.
661 @cindex return instructions, i386
662 @cindex i386 jump, call, return
663 @cindex return instructions, x86-64
664 @cindex x86-64 jump, call, return
666 Immediate form long jumps and calls are
667 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
669 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
671 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
672 @samp{ret far @var{stack-adjust}}.
674 @cindex sections, i386
675 @cindex i386 sections
676 @cindex sections, x86-64
677 @cindex x86-64 sections
679 The AT&T assembler does not provide support for multiple section
680 programs. Unix style systems expect all programs to be single sections.
684 @subsection Special Characters
686 @cindex line comment character, i386
687 @cindex i386 line comment character
688 The presence of a @samp{#} appearing anywhere on a line indicates the
689 start of a comment that extends to the end of that line.
691 If a @samp{#} appears as the first character of a line then the whole
692 line is treated as a comment, but in this case the line can also be a
693 logical line number directive (@pxref{Comments}) or a preprocessor
694 control command (@pxref{Preprocessing}).
696 If the @option{--divide} command-line option has not been specified
697 then the @samp{/} character appearing anywhere on a line also
698 introduces a line comment.
700 @cindex line separator, i386
701 @cindex statement separator, i386
702 @cindex i386 line separator
703 The @samp{;} character can be used to separate statements on the same
707 @section i386-Mnemonics
708 @subsection Instruction Naming
710 @cindex i386 instruction naming
711 @cindex instruction naming, i386
712 @cindex x86-64 instruction naming
713 @cindex instruction naming, x86-64
715 Instruction mnemonics are suffixed with one character modifiers which
716 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
717 and @samp{q} specify byte, word, long and quadruple word operands. If
718 no suffix is specified by an instruction then @code{@value{AS}} tries to
719 fill in the missing suffix based on the destination register operand
720 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
721 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
722 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
723 assembler which assumes that a missing mnemonic suffix implies long
724 operand size. (This incompatibility does not affect compiler output
725 since compilers always explicitly specify the mnemonic suffix.)
727 When there is no sizing suffix and no (suitable) register operands to
728 deduce the size of memory operands, with a few exceptions and where long
729 operand size is possible in the first place, operand size will default
730 to long in 32- and 64-bit modes. Similarly it will default to short in
731 16-bit mode. Noteworthy exceptions are
735 Instructions with an implicit on-stack operand as well as branches,
736 which default to quad in 64-bit mode.
739 Sign- and zero-extending moves, which default to byte size source
743 Floating point insns with integer operands, which default to short (for
744 perhaps historical reasons).
747 CRC32 with a 64-bit destination, which defaults to a quad source
752 Almost all instructions have the same names in AT&T and Intel format.
753 There are a few exceptions. The sign extend and zero extend
754 instructions need two sizes to specify them. They need a size to
755 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
756 is accomplished by using two instruction mnemonic suffixes in AT&T
757 syntax. Base names for sign extend and zero extend are
758 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
759 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
760 are tacked on to this base name, the @emph{from} suffix before the
761 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
762 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
763 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
764 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
765 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
768 @cindex encoding options, i386
769 @cindex encoding options, x86-64
771 Different encoding options can be specified via pseudo prefixes:
775 @samp{@{disp8@}} -- prefer 8-bit displacement.
778 @samp{@{disp32@}} -- prefer 32-bit displacement.
781 @samp{@{load@}} -- prefer load-form instruction.
784 @samp{@{store@}} -- prefer store-form instruction.
787 @samp{@{vex@}} -- encode with VEX prefix.
790 @samp{@{vex3@}} -- encode with 3-byte VEX prefix.
793 @samp{@{evex@}} -- encode with EVEX prefix.
796 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
797 instructions (x86-64 only). Note that this differs from the @samp{rex}
798 prefix which generates REX prefix unconditionally.
801 @samp{@{nooptimize@}} -- disable instruction size optimization.
804 @cindex conversion instructions, i386
805 @cindex i386 conversion instructions
806 @cindex conversion instructions, x86-64
807 @cindex x86-64 conversion instructions
808 The Intel-syntax conversion instructions
812 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
815 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
818 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
821 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
824 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
828 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
829 @samp{%rdx:%rax} (x86-64 only),
833 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
834 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
837 @cindex jump instructions, i386
838 @cindex call instructions, i386
839 @cindex jump instructions, x86-64
840 @cindex call instructions, x86-64
841 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
842 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
845 @subsection AT&T Mnemonic versus Intel Mnemonic
847 @cindex i386 mnemonic compatibility
848 @cindex mnemonic compatibility, i386
850 @code{@value{AS}} supports assembly using Intel mnemonic.
851 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
852 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
853 syntax for compatibility with the output of @code{@value{GCC}}.
854 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
855 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
856 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
857 assembler with different mnemonics from those in Intel IA32 specification.
858 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
861 @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination
862 register. @samp{movsxd} should be used to encode 16-bit or 32-bit
863 destination register with both AT&T and Intel mnemonics.
867 @section Register Naming
869 @cindex i386 registers
870 @cindex registers, i386
871 @cindex x86-64 registers
872 @cindex registers, x86-64
873 Register operands are always prefixed with @samp{%}. The 80386 registers
878 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
879 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
880 frame pointer), and @samp{%esp} (the stack pointer).
883 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
884 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
887 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
888 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
889 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
890 @samp{%cx}, and @samp{%dx})
893 the 6 section registers @samp{%cs} (code section), @samp{%ds}
894 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
898 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
899 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
902 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
903 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
906 the 2 test registers @samp{%tr6} and @samp{%tr7}.
909 the 8 floating point register stack @samp{%st} or equivalently
910 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
911 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
912 These registers are overloaded by 8 MMX registers @samp{%mm0},
913 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
914 @samp{%mm6} and @samp{%mm7}.
917 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
918 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
921 The AMD x86-64 architecture extends the register set by:
925 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
926 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
927 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
931 the 8 extended registers @samp{%r8}--@samp{%r15}.
934 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
937 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
940 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
943 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
946 the 8 debug registers: @samp{%db8}--@samp{%db15}.
949 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
952 With the AVX extensions more registers were made available:
957 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
958 available in 32-bit mode). The bottom 128 bits are overlaid with the
959 @samp{xmm0}--@samp{xmm15} registers.
963 The AVX2 extensions made in 64-bit mode more registers available:
968 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
969 registers @samp{%ymm16}--@samp{%ymm31}.
973 The AVX512 extensions added the following registers:
978 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
979 available in 32-bit mode). The bottom 128 bits are overlaid with the
980 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
981 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
984 the 8 mask registers @samp{%k0}--@samp{%k7}.
989 @section Instruction Prefixes
991 @cindex i386 instruction prefixes
992 @cindex instruction prefixes, i386
993 @cindex prefixes, i386
994 Instruction prefixes are used to modify the following instruction. They
995 are used to repeat string instructions, to provide section overrides, to
996 perform bus lock operations, and to change operand and address sizes.
997 (Most instructions that normally operate on 32-bit operands will use
998 16-bit operands if the instruction has an ``operand size'' prefix.)
999 Instruction prefixes are best written on the same line as the instruction
1000 they act upon. For example, the @samp{scas} (scan string) instruction is
1004 repne scas %es:(%edi),%al
1007 You may also place prefixes on the lines immediately preceding the
1008 instruction, but this circumvents checks that @code{@value{AS}} does
1009 with prefixes, and will not work with all prefixes.
1011 Here is a list of instruction prefixes:
1013 @cindex section override prefixes, i386
1016 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
1017 @samp{fs}, @samp{gs}. These are automatically added by specifying
1018 using the @var{section}:@var{memory-operand} form for memory references.
1020 @cindex size prefixes, i386
1022 Operand/Address size prefixes @samp{data16} and @samp{addr16}
1023 change 32-bit operands/addresses into 16-bit operands/addresses,
1024 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
1025 @code{.code16} section) into 32-bit operands/addresses. These prefixes
1026 @emph{must} appear on the same line of code as the instruction they
1027 modify. For example, in a 16-bit @code{.code16} section, you might
1034 @cindex bus lock prefixes, i386
1035 @cindex inhibiting interrupts, i386
1037 The bus lock prefix @samp{lock} inhibits interrupts during execution of
1038 the instruction it precedes. (This is only valid with certain
1039 instructions; see a 80386 manual for details).
1041 @cindex coprocessor wait, i386
1043 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
1044 complete the current instruction. This should never be needed for the
1045 80386/80387 combination.
1047 @cindex repeat prefixes, i386
1049 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
1050 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
1051 times if the current address size is 16-bits).
1052 @cindex REX prefixes, i386
1054 The @samp{rex} family of prefixes is used by x86-64 to encode
1055 extensions to i386 instruction set. The @samp{rex} prefix has four
1056 bits --- an operand size overwrite (@code{64}) used to change operand size
1057 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
1060 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
1061 instruction emits @samp{rex} prefix with all the bits set. By omitting
1062 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
1063 prefixes as well. Normally, there is no need to write the prefixes
1064 explicitly, since gas will automatically generate them based on the
1065 instruction operands.
1069 @section Memory References
1071 @cindex i386 memory references
1072 @cindex memory references, i386
1073 @cindex x86-64 memory references
1074 @cindex memory references, x86-64
1075 An Intel syntax indirect memory reference of the form
1078 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
1082 is translated into the AT&T syntax
1085 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
1089 where @var{base} and @var{index} are the optional 32-bit base and
1090 index registers, @var{disp} is the optional displacement, and
1091 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
1092 to calculate the address of the operand. If no @var{scale} is
1093 specified, @var{scale} is taken to be 1. @var{section} specifies the
1094 optional section register for the memory operand, and may override the
1095 default section register (see a 80386 manual for section register
1096 defaults). Note that section overrides in AT&T syntax @emph{must}
1097 be preceded by a @samp{%}. If you specify a section override which
1098 coincides with the default section register, @code{@value{AS}} does @emph{not}
1099 output any section register override prefixes to assemble the given
1100 instruction. Thus, section overrides can be specified to emphasize which
1101 section register is used for a given memory operand.
1103 Here are some examples of Intel and AT&T style memory references:
1106 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1107 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1108 missing, and the default section is used (@samp{%ss} for addressing with
1109 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1111 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1112 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1113 @samp{foo}. All other fields are missing. The section register here
1114 defaults to @samp{%ds}.
1116 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1117 This uses the value pointed to by @samp{foo} as a memory operand.
1118 Note that @var{base} and @var{index} are both missing, but there is only
1119 @emph{one} @samp{,}. This is a syntactic exception.
1121 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1122 This selects the contents of the variable @samp{foo} with section
1123 register @var{section} being @samp{%gs}.
1126 Absolute (as opposed to PC relative) call and jump operands must be
1127 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1128 always chooses PC relative addressing for jump/call labels.
1130 Any instruction that has a memory operand, but no register operand,
1131 @emph{must} specify its size (byte, word, long, or quadruple) with an
1132 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1135 The x86-64 architecture adds an RIP (instruction pointer relative)
1136 addressing. This addressing mode is specified by using @samp{rip} as a
1137 base register. Only constant offsets are valid. For example:
1140 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1141 Points to the address 1234 bytes past the end of the current
1144 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1145 Points to the @code{symbol} in RIP relative way, this is shorter than
1146 the default absolute addressing.
1149 Other addressing modes remain unchanged in x86-64 architecture, except
1150 registers used are 64-bit instead of 32-bit.
1153 @section Handling of Jump Instructions
1155 @cindex jump optimization, i386
1156 @cindex i386 jump optimization
1157 @cindex jump optimization, x86-64
1158 @cindex x86-64 jump optimization
1159 Jump instructions are always optimized to use the smallest possible
1160 displacements. This is accomplished by using byte (8-bit) displacement
1161 jumps whenever the target is sufficiently close. If a byte displacement
1162 is insufficient a long displacement is used. We do not support
1163 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1164 instruction with the @samp{data16} instruction prefix), since the 80386
1165 insists upon masking @samp{%eip} to 16 bits after the word displacement
1166 is added. (See also @pxref{i386-Arch})
1168 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1169 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1170 displacements, so that if you use these instructions (@code{@value{GCC}} does
1171 not use them) you may get an error message (and incorrect code). The AT&T
1172 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1183 @section Floating Point
1185 @cindex i386 floating point
1186 @cindex floating point, i386
1187 @cindex x86-64 floating point
1188 @cindex floating point, x86-64
1189 All 80387 floating point types except packed BCD are supported.
1190 (BCD support may be added without much difficulty). These data
1191 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1192 double (64-bit), and extended (80-bit) precision floating point.
1193 Each supported type has an instruction mnemonic suffix and a constructor
1194 associated with it. Instruction mnemonic suffixes specify the operand's
1195 data type. Constructors build these data types into memory.
1197 @cindex @code{float} directive, i386
1198 @cindex @code{single} directive, i386
1199 @cindex @code{double} directive, i386
1200 @cindex @code{tfloat} directive, i386
1201 @cindex @code{float} directive, x86-64
1202 @cindex @code{single} directive, x86-64
1203 @cindex @code{double} directive, x86-64
1204 @cindex @code{tfloat} directive, x86-64
1207 Floating point constructors are @samp{.float} or @samp{.single},
1208 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1209 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1210 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1211 only supports this format via the @samp{fldt} (load 80-bit real to stack
1212 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1214 @cindex @code{word} directive, i386
1215 @cindex @code{long} directive, i386
1216 @cindex @code{int} directive, i386
1217 @cindex @code{quad} directive, i386
1218 @cindex @code{word} directive, x86-64
1219 @cindex @code{long} directive, x86-64
1220 @cindex @code{int} directive, x86-64
1221 @cindex @code{quad} directive, x86-64
1223 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1224 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1225 corresponding instruction mnemonic suffixes are @samp{s} (single),
1226 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1227 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1228 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1229 stack) instructions.
1232 Register to register operations should not use instruction mnemonic suffixes.
1233 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1234 wrote @samp{fst %st, %st(1)}, since all register to register operations
1235 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1236 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1237 then stores the result in the 4 byte location @samp{mem})
1240 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1243 @cindex 3DNow!, i386
1246 @cindex 3DNow!, x86-64
1247 @cindex SIMD, x86-64
1249 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1250 instructions for integer data), available on Intel's Pentium MMX
1251 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1252 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1253 instruction set (SIMD instructions for 32-bit floating point data)
1254 available on AMD's K6-2 processor and possibly others in the future.
1256 Currently, @code{@value{AS}} does not support Intel's floating point
1259 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1260 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1261 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1262 floating point values. The MMX registers cannot be used at the same time
1263 as the floating point stack.
1265 See Intel and AMD documentation, keeping in mind that the operand order in
1266 instructions is reversed from the Intel syntax.
1269 @section AMD's Lightweight Profiling Instructions
1274 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1275 instruction set, available on AMD's Family 15h (Orochi) processors.
1277 LWP enables applications to collect and manage performance data, and
1278 react to performance events. The collection of performance data
1279 requires no context switches. LWP runs in the context of a thread and
1280 so several counters can be used independently across multiple threads.
1281 LWP can be used in both 64-bit and legacy 32-bit modes.
1283 For detailed information on the LWP instruction set, see the
1284 @cite{AMD Lightweight Profiling Specification} available at
1285 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1288 @section Bit Manipulation Instructions
1293 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1295 BMI instructions provide several instructions implementing individual
1296 bit manipulation operations such as isolation, masking, setting, or
1299 @c Need to add a specification citation here when available.
1302 @section AMD's Trailing Bit Manipulation Instructions
1307 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1308 instruction set, available on AMD's BDVER2 processors (Trinity and
1311 TBM instructions provide instructions implementing individual bit
1312 manipulation operations such as isolating, masking, setting, resetting,
1313 complementing, and operations on trailing zeros and ones.
1315 @c Need to add a specification citation here when available.
1318 @section Writing 16-bit Code
1320 @cindex i386 16-bit code
1321 @cindex 16-bit code, i386
1322 @cindex real-mode code, i386
1323 @cindex @code{code16gcc} directive, i386
1324 @cindex @code{code16} directive, i386
1325 @cindex @code{code32} directive, i386
1326 @cindex @code{code64} directive, i386
1327 @cindex @code{code64} directive, x86-64
1328 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1329 or 64-bit x86-64 code depending on the default configuration,
1330 it also supports writing code to run in real mode or in 16-bit protected
1331 mode code segments. To do this, put a @samp{.code16} or
1332 @samp{.code16gcc} directive before the assembly language instructions to
1333 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1334 32-bit code with the @samp{.code32} directive or 64-bit code with the
1335 @samp{.code64} directive.
1337 @samp{.code16gcc} provides experimental support for generating 16-bit
1338 code from gcc, and differs from @samp{.code16} in that @samp{call},
1339 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1340 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1341 default to 32-bit size. This is so that the stack pointer is
1342 manipulated in the same way over function calls, allowing access to
1343 function parameters at the same stack offsets as in 32-bit mode.
1344 @samp{.code16gcc} also automatically adds address size prefixes where
1345 necessary to use the 32-bit addressing modes that gcc generates.
1347 The code which @code{@value{AS}} generates in 16-bit mode will not
1348 necessarily run on a 16-bit pre-80386 processor. To write code that
1349 runs on such a processor, you must refrain from using @emph{any} 32-bit
1350 constructs which require @code{@value{AS}} to output address or operand
1353 Note that writing 16-bit code instructions by explicitly specifying a
1354 prefix or an instruction mnemonic suffix within a 32-bit code section
1355 generates different machine instructions than those generated for a
1356 16-bit code segment. In a 32-bit code section, the following code
1357 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1358 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1364 The same code in a 16-bit code section would generate the machine
1365 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1366 is correct since the processor default operand size is assumed to be 16
1367 bits in a 16-bit code section.
1370 @section Specifying CPU Architecture
1372 @cindex arch directive, i386
1373 @cindex i386 arch directive
1374 @cindex arch directive, x86-64
1375 @cindex x86-64 arch directive
1377 @code{@value{AS}} may be told to assemble for a particular CPU
1378 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1379 directive enables a warning when gas detects an instruction that is not
1380 supported on the CPU specified. The choices for @var{cpu_type} are:
1382 @multitable @columnfractions .20 .20 .20 .20
1383 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1384 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1385 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1386 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1387 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1388 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1389 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1390 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1391 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1392 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1393 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1394 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1395 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1396 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1397 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1398 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1399 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1400 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1401 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1402 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1403 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1404 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1405 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1406 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1407 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1408 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1409 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1410 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1411 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
1412 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1413 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1414 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1415 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
1416 @item @samp{.mcommit}
1419 Apart from the warning, there are only two other effects on
1420 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1421 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1422 will automatically use a two byte opcode sequence. The larger three
1423 byte opcode sequence is used on the 486 (and when no architecture is
1424 specified) because it executes faster on the 486. Note that you can
1425 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1426 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1427 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1428 conditional jumps will be promoted when necessary to a two instruction
1429 sequence consisting of a conditional jump of the opposite sense around
1430 an unconditional jump to the target.
1432 Following the CPU architecture (but not a sub-architecture, which are those
1433 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1434 control automatic promotion of conditional jumps. @samp{jumps} is the
1435 default, and enables jump promotion; All external jumps will be of the long
1436 variety, and file-local jumps will be promoted as necessary.
1437 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1438 byte offset jumps, and warns about file-local conditional jumps that
1439 @code{@value{AS}} promotes.
1440 Unconditional jumps are treated as for @samp{jumps}.
1449 @section AMD64 ISA vs. Intel64 ISA
1451 There are some discrepancies between AMD64 and Intel64 ISAs.
1454 @item For @samp{movsxd} with 16-bit destination register, AMD64
1455 supports 32-bit source operand and Intel64 supports 16-bit source
1460 @section AT&T Syntax bugs
1462 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1463 assemblers, generate floating point instructions with reversed source
1464 and destination registers in certain cases. Unfortunately, gcc and
1465 possibly many other programs use this reversed syntax, so we're stuck
1474 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1475 than the expected @samp{%st(3) - %st}. This happens with all the
1476 non-commutative arithmetic floating point operations with two register
1477 operands where the source register is @samp{%st} and the destination
1478 register is @samp{%st(i)}.
1483 @cindex i386 @code{mul}, @code{imul} instructions
1484 @cindex @code{mul} instruction, i386
1485 @cindex @code{imul} instruction, i386
1486 @cindex @code{mul} instruction, x86-64
1487 @cindex @code{imul} instruction, x86-64
1488 There is some trickery concerning the @samp{mul} and @samp{imul}
1489 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1490 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1491 for @samp{imul}) can be output only in the one operand form. Thus,
1492 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1493 the expanding multiply would clobber the @samp{%edx} register, and this
1494 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1495 64-bit product in @samp{%edx:%eax}.
1497 We have added a two operand form of @samp{imul} when the first operand
1498 is an immediate mode expression and the second operand is a register.
1499 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1500 example, can be done with @samp{imul $69, %eax} rather than @samp{imul