Enable Intel CLDEMOTE instruction.
[deliverable/binutils-gdb.git] / gas / doc / c-i386.texi
1 @c Copyright (C) 1991-2018 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
4 @c man end
5
6 @ifset GENERIC
7 @page
8 @node i386-Dependent
9 @chapter 80386 Dependent Features
10 @end ifset
11 @ifclear GENERIC
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
14 @end ifclear
15
16 @cindex i386 support
17 @cindex i80386 support
18 @cindex x86-64 support
19
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
23
24 @menu
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
41 * i386-Notes:: Notes
42 @end menu
43
44 @node i386-Options
45 @section Options
46
47 @cindex options for i386
48 @cindex options for x86-64
49 @cindex i386 options
50 @cindex x86-64 options
51
52 The i386 version of @code{@value{AS}} has a few machine
53 dependent options:
54
55 @c man begin OPTIONS
56 @table @gcctabopt
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
67 respectively.
68
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
73
74 @item -n
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78 byte nop (0x90) is explicitly specified as the fill byte for alignment.
79
80 @cindex @samp{--divide} option, i386
81 @item --divide
82 On SVR4-derived platforms, the character @samp{/} is treated as a comment
83 character, which means that it cannot be used in expressions. The
84 @samp{--divide} option turns @samp{/} into a normal character. This does
85 not disable @samp{/} at the beginning of a line starting a comment, or
86 affect using @samp{#} for starting a comment.
87
88 @cindex @samp{-march=} option, i386
89 @cindex @samp{-march=} option, x86-64
90 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91 This option specifies the target processor. The assembler will
92 issue an error message if an attempt is made to assemble an instruction
93 which will not execute on the target processor. The following
94 processor names are recognized:
95 @code{i8086},
96 @code{i186},
97 @code{i286},
98 @code{i386},
99 @code{i486},
100 @code{i586},
101 @code{i686},
102 @code{pentium},
103 @code{pentiumpro},
104 @code{pentiumii},
105 @code{pentiumiii},
106 @code{pentium4},
107 @code{prescott},
108 @code{nocona},
109 @code{core},
110 @code{core2},
111 @code{corei7},
112 @code{l1om},
113 @code{k1om},
114 @code{iamcu},
115 @code{k6},
116 @code{k6_2},
117 @code{athlon},
118 @code{opteron},
119 @code{k8},
120 @code{amdfam10},
121 @code{bdver1},
122 @code{bdver2},
123 @code{bdver3},
124 @code{bdver4},
125 @code{znver1},
126 @code{btver1},
127 @code{btver2},
128 @code{generic32} and
129 @code{generic64}.
130
131 In addition to the basic instruction set, the assembler can be told to
132 accept various extension mnemonics. For example,
133 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
134 @var{vmx}. The following extensions are currently supported:
135 @code{8087},
136 @code{287},
137 @code{387},
138 @code{687},
139 @code{no87},
140 @code{no287},
141 @code{no387},
142 @code{no687},
143 @code{mmx},
144 @code{nommx},
145 @code{sse},
146 @code{sse2},
147 @code{sse3},
148 @code{ssse3},
149 @code{sse4.1},
150 @code{sse4.2},
151 @code{sse4},
152 @code{nosse},
153 @code{nosse2},
154 @code{nosse3},
155 @code{nossse3},
156 @code{nosse4.1},
157 @code{nosse4.2},
158 @code{nosse4},
159 @code{avx},
160 @code{avx2},
161 @code{noavx},
162 @code{noavx2},
163 @code{adx},
164 @code{rdseed},
165 @code{prfchw},
166 @code{smap},
167 @code{mpx},
168 @code{sha},
169 @code{rdpid},
170 @code{ptwrite},
171 @code{cet},
172 @code{gfni},
173 @code{vaes},
174 @code{vpclmulqdq},
175 @code{prefetchwt1},
176 @code{clflushopt},
177 @code{se1},
178 @code{clwb},
179 @code{avx512f},
180 @code{avx512cd},
181 @code{avx512er},
182 @code{avx512pf},
183 @code{avx512vl},
184 @code{avx512bw},
185 @code{avx512dq},
186 @code{avx512ifma},
187 @code{avx512vbmi},
188 @code{avx512_4fmaps},
189 @code{avx512_4vnniw},
190 @code{avx512_vpopcntdq},
191 @code{avx512_vbmi2},
192 @code{avx512_vnni},
193 @code{avx512_bitalg},
194 @code{noavx512f},
195 @code{noavx512cd},
196 @code{noavx512er},
197 @code{noavx512pf},
198 @code{noavx512vl},
199 @code{noavx512bw},
200 @code{noavx512dq},
201 @code{noavx512ifma},
202 @code{noavx512vbmi},
203 @code{noavx512_4fmaps},
204 @code{noavx512_4vnniw},
205 @code{noavx512_vpopcntdq},
206 @code{noavx512_vbmi2},
207 @code{noavx512_vnni},
208 @code{noavx512_bitalg},
209 @code{vmx},
210 @code{vmfunc},
211 @code{smx},
212 @code{xsave},
213 @code{xsaveopt},
214 @code{xsavec},
215 @code{xsaves},
216 @code{aes},
217 @code{pclmul},
218 @code{fsgsbase},
219 @code{rdrnd},
220 @code{f16c},
221 @code{bmi2},
222 @code{fma},
223 @code{movbe},
224 @code{ept},
225 @code{lzcnt},
226 @code{hle},
227 @code{rtm},
228 @code{invpcid},
229 @code{clflush},
230 @code{mwaitx},
231 @code{clzero},
232 @code{wbnoinvd},
233 @code{pconfig},
234 @code{waitpkg},
235 @code{cldemote},
236 @code{lwp},
237 @code{fma4},
238 @code{xop},
239 @code{cx16},
240 @code{syscall},
241 @code{rdtscp},
242 @code{3dnow},
243 @code{3dnowa},
244 @code{sse4a},
245 @code{sse5},
246 @code{svme},
247 @code{abm} and
248 @code{padlock}.
249 Note that rather than extending a basic instruction set, the extension
250 mnemonics starting with @code{no} revoke the respective functionality.
251
252 When the @code{.arch} directive is used with @option{-march}, the
253 @code{.arch} directive will take precedent.
254
255 @cindex @samp{-mtune=} option, i386
256 @cindex @samp{-mtune=} option, x86-64
257 @item -mtune=@var{CPU}
258 This option specifies a processor to optimize for. When used in
259 conjunction with the @option{-march} option, only instructions
260 of the processor specified by the @option{-march} option will be
261 generated.
262
263 Valid @var{CPU} values are identical to the processor list of
264 @option{-march=@var{CPU}}.
265
266 @cindex @samp{-msse2avx} option, i386
267 @cindex @samp{-msse2avx} option, x86-64
268 @item -msse2avx
269 This option specifies that the assembler should encode SSE instructions
270 with VEX prefix.
271
272 @cindex @samp{-msse-check=} option, i386
273 @cindex @samp{-msse-check=} option, x86-64
274 @item -msse-check=@var{none}
275 @itemx -msse-check=@var{warning}
276 @itemx -msse-check=@var{error}
277 These options control if the assembler should check SSE instructions.
278 @option{-msse-check=@var{none}} will make the assembler not to check SSE
279 instructions, which is the default. @option{-msse-check=@var{warning}}
280 will make the assembler issue a warning for any SSE instruction.
281 @option{-msse-check=@var{error}} will make the assembler issue an error
282 for any SSE instruction.
283
284 @cindex @samp{-mavxscalar=} option, i386
285 @cindex @samp{-mavxscalar=} option, x86-64
286 @item -mavxscalar=@var{128}
287 @itemx -mavxscalar=@var{256}
288 These options control how the assembler should encode scalar AVX
289 instructions. @option{-mavxscalar=@var{128}} will encode scalar
290 AVX instructions with 128bit vector length, which is the default.
291 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
292 with 256bit vector length.
293
294 @cindex @samp{-mevexlig=} option, i386
295 @cindex @samp{-mevexlig=} option, x86-64
296 @item -mevexlig=@var{128}
297 @itemx -mevexlig=@var{256}
298 @itemx -mevexlig=@var{512}
299 These options control how the assembler should encode length-ignored
300 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
301 EVEX instructions with 128bit vector length, which is the default.
302 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
303 encode LIG EVEX instructions with 256bit and 512bit vector length,
304 respectively.
305
306 @cindex @samp{-mevexwig=} option, i386
307 @cindex @samp{-mevexwig=} option, x86-64
308 @item -mevexwig=@var{0}
309 @itemx -mevexwig=@var{1}
310 These options control how the assembler should encode w-ignored (WIG)
311 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
312 EVEX instructions with evex.w = 0, which is the default.
313 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
314 evex.w = 1.
315
316 @cindex @samp{-mmnemonic=} option, i386
317 @cindex @samp{-mmnemonic=} option, x86-64
318 @item -mmnemonic=@var{att}
319 @itemx -mmnemonic=@var{intel}
320 This option specifies instruction mnemonic for matching instructions.
321 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
322 take precedent.
323
324 @cindex @samp{-msyntax=} option, i386
325 @cindex @samp{-msyntax=} option, x86-64
326 @item -msyntax=@var{att}
327 @itemx -msyntax=@var{intel}
328 This option specifies instruction syntax when processing instructions.
329 The @code{.att_syntax} and @code{.intel_syntax} directives will
330 take precedent.
331
332 @cindex @samp{-mnaked-reg} option, i386
333 @cindex @samp{-mnaked-reg} option, x86-64
334 @item -mnaked-reg
335 This option specifies that registers don't require a @samp{%} prefix.
336 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
337
338 @cindex @samp{-madd-bnd-prefix} option, i386
339 @cindex @samp{-madd-bnd-prefix} option, x86-64
340 @item -madd-bnd-prefix
341 This option forces the assembler to add BND prefix to all branches, even
342 if such prefix was not explicitly specified in the source code.
343
344 @cindex @samp{-mshared} option, i386
345 @cindex @samp{-mshared} option, x86-64
346 @item -mno-shared
347 On ELF target, the assembler normally optimizes out non-PLT relocations
348 against defined non-weak global branch targets with default visibility.
349 The @samp{-mshared} option tells the assembler to generate code which
350 may go into a shared library where all non-weak global branch targets
351 with default visibility can be preempted. The resulting code is
352 slightly bigger. This option only affects the handling of branch
353 instructions.
354
355 @cindex @samp{-mbig-obj} option, x86-64
356 @item -mbig-obj
357 On x86-64 PE/COFF target this option forces the use of big object file
358 format, which allows more than 32768 sections.
359
360 @cindex @samp{-momit-lock-prefix=} option, i386
361 @cindex @samp{-momit-lock-prefix=} option, x86-64
362 @item -momit-lock-prefix=@var{no}
363 @itemx -momit-lock-prefix=@var{yes}
364 These options control how the assembler should encode lock prefix.
365 This option is intended as a workaround for processors, that fail on
366 lock prefix. This option can only be safely used with single-core,
367 single-thread computers
368 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
369 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
370 which is the default.
371
372 @cindex @samp{-mfence-as-lock-add=} option, i386
373 @cindex @samp{-mfence-as-lock-add=} option, x86-64
374 @item -mfence-as-lock-add=@var{no}
375 @itemx -mfence-as-lock-add=@var{yes}
376 These options control how the assembler should encode lfence, mfence and
377 sfence.
378 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
379 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
380 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
381 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
382 sfence as usual, which is the default.
383
384 @cindex @samp{-mrelax-relocations=} option, i386
385 @cindex @samp{-mrelax-relocations=} option, x86-64
386 @item -mrelax-relocations=@var{no}
387 @itemx -mrelax-relocations=@var{yes}
388 These options control whether the assembler should generate relax
389 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
390 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
391 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
392 @option{-mrelax-relocations=@var{no}} will not generate relax
393 relocations. The default can be controlled by a configure option
394 @option{--enable-x86-relax-relocations}.
395
396 @cindex @samp{-mevexrcig=} option, i386
397 @cindex @samp{-mevexrcig=} option, x86-64
398 @item -mevexrcig=@var{rne}
399 @itemx -mevexrcig=@var{rd}
400 @itemx -mevexrcig=@var{ru}
401 @itemx -mevexrcig=@var{rz}
402 These options control how the assembler should encode SAE-only
403 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
404 of EVEX instruction with 00, which is the default.
405 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
406 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
407 with 01, 10 and 11 RC bits, respectively.
408
409 @cindex @samp{-mamd64} option, x86-64
410 @cindex @samp{-mintel64} option, x86-64
411 @item -mamd64
412 @itemx -mintel64
413 This option specifies that the assembler should accept only AMD64 or
414 Intel64 ISA in 64-bit mode. The default is to accept both.
415
416 @cindex @samp{-O0} option, i386
417 @cindex @samp{-O0} option, x86-64
418 @cindex @samp{-O} option, i386
419 @cindex @samp{-O} option, x86-64
420 @cindex @samp{-O1} option, i386
421 @cindex @samp{-O1} option, x86-64
422 @cindex @samp{-O2} option, i386
423 @cindex @samp{-O2} option, x86-64
424 @cindex @samp{-Os} option, i386
425 @cindex @samp{-Os} option, x86-64
426 @item -O0 | -O | -O1 | -O2 | -Os
427 Optimize instruction encoding with smaller instruction size. @samp{-O}
428 and @samp{-O1} encode 64-bit register load instructions with 64-bit
429 immediate as 32-bit register load instructions with 31-bit or 32-bits
430 immediates and encode 64-bit register clearing instructions with 32-bit
431 register clearing instructions. @samp{-O2} includes @samp{-O1}
432 optimization plus encodes 256-bit and 512-bit vector register clearing
433 instructions with 128-bit vector register clearing instructions.
434 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
435 and 64-bit register tests with immediate as 8-bit register test with
436 immediate. @samp{-O0} turns off this optimization.
437
438 @end table
439 @c man end
440
441 @node i386-Directives
442 @section x86 specific Directives
443
444 @cindex machine directives, x86
445 @cindex x86 machine directives
446 @table @code
447
448 @cindex @code{lcomm} directive, COFF
449 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
450 Reserve @var{length} (an absolute expression) bytes for a local common
451 denoted by @var{symbol}. The section and value of @var{symbol} are
452 those of the new local common. The addresses are allocated in the bss
453 section, so that at run-time the bytes start off zeroed. Since
454 @var{symbol} is not declared global, it is normally not visible to
455 @code{@value{LD}}. The optional third parameter, @var{alignment},
456 specifies the desired alignment of the symbol in the bss section.
457
458 This directive is only available for COFF based x86 targets.
459
460 @cindex @code{largecomm} directive, ELF
461 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
462 This directive behaves in the same way as the @code{comm} directive
463 except that the data is placed into the @var{.lbss} section instead of
464 the @var{.bss} section @ref{Comm}.
465
466 The directive is intended to be used for data which requires a large
467 amount of space, and it is only available for ELF based x86_64
468 targets.
469
470 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
471
472 @end table
473
474 @node i386-Syntax
475 @section i386 Syntactical Considerations
476 @menu
477 * i386-Variations:: AT&T Syntax versus Intel Syntax
478 * i386-Chars:: Special Characters
479 @end menu
480
481 @node i386-Variations
482 @subsection AT&T Syntax versus Intel Syntax
483
484 @cindex i386 intel_syntax pseudo op
485 @cindex intel_syntax pseudo op, i386
486 @cindex i386 att_syntax pseudo op
487 @cindex att_syntax pseudo op, i386
488 @cindex i386 syntax compatibility
489 @cindex syntax compatibility, i386
490 @cindex x86-64 intel_syntax pseudo op
491 @cindex intel_syntax pseudo op, x86-64
492 @cindex x86-64 att_syntax pseudo op
493 @cindex att_syntax pseudo op, x86-64
494 @cindex x86-64 syntax compatibility
495 @cindex syntax compatibility, x86-64
496
497 @code{@value{AS}} now supports assembly using Intel assembler syntax.
498 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
499 back to the usual AT&T mode for compatibility with the output of
500 @code{@value{GCC}}. Either of these directives may have an optional
501 argument, @code{prefix}, or @code{noprefix} specifying whether registers
502 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
503 different from Intel syntax. We mention these differences because
504 almost all 80386 documents use Intel syntax. Notable differences
505 between the two syntaxes are:
506
507 @cindex immediate operands, i386
508 @cindex i386 immediate operands
509 @cindex register operands, i386
510 @cindex i386 register operands
511 @cindex jump/call operands, i386
512 @cindex i386 jump/call operands
513 @cindex operand delimiters, i386
514
515 @cindex immediate operands, x86-64
516 @cindex x86-64 immediate operands
517 @cindex register operands, x86-64
518 @cindex x86-64 register operands
519 @cindex jump/call operands, x86-64
520 @cindex x86-64 jump/call operands
521 @cindex operand delimiters, x86-64
522 @itemize @bullet
523 @item
524 AT&T immediate operands are preceded by @samp{$}; Intel immediate
525 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
526 AT&T register operands are preceded by @samp{%}; Intel register operands
527 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
528 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
529
530 @cindex i386 source, destination operands
531 @cindex source, destination operands; i386
532 @cindex x86-64 source, destination operands
533 @cindex source, destination operands; x86-64
534 @item
535 AT&T and Intel syntax use the opposite order for source and destination
536 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
537 @samp{source, dest} convention is maintained for compatibility with
538 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
539 instructions with 2 immediate operands, such as the @samp{enter}
540 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
541
542 @cindex mnemonic suffixes, i386
543 @cindex sizes operands, i386
544 @cindex i386 size suffixes
545 @cindex mnemonic suffixes, x86-64
546 @cindex sizes operands, x86-64
547 @cindex x86-64 size suffixes
548 @item
549 In AT&T syntax the size of memory operands is determined from the last
550 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
551 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
552 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
553 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
554 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
555 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
556 syntax.
557
558 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
559 instruction with the 64-bit displacement or immediate operand.
560
561 @cindex return instructions, i386
562 @cindex i386 jump, call, return
563 @cindex return instructions, x86-64
564 @cindex x86-64 jump, call, return
565 @item
566 Immediate form long jumps and calls are
567 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
568 Intel syntax is
569 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
570 instruction
571 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
572 @samp{ret far @var{stack-adjust}}.
573
574 @cindex sections, i386
575 @cindex i386 sections
576 @cindex sections, x86-64
577 @cindex x86-64 sections
578 @item
579 The AT&T assembler does not provide support for multiple section
580 programs. Unix style systems expect all programs to be single sections.
581 @end itemize
582
583 @node i386-Chars
584 @subsection Special Characters
585
586 @cindex line comment character, i386
587 @cindex i386 line comment character
588 The presence of a @samp{#} appearing anywhere on a line indicates the
589 start of a comment that extends to the end of that line.
590
591 If a @samp{#} appears as the first character of a line then the whole
592 line is treated as a comment, but in this case the line can also be a
593 logical line number directive (@pxref{Comments}) or a preprocessor
594 control command (@pxref{Preprocessing}).
595
596 If the @option{--divide} command line option has not been specified
597 then the @samp{/} character appearing anywhere on a line also
598 introduces a line comment.
599
600 @cindex line separator, i386
601 @cindex statement separator, i386
602 @cindex i386 line separator
603 The @samp{;} character can be used to separate statements on the same
604 line.
605
606 @node i386-Mnemonics
607 @section i386-Mnemonics
608 @subsection Instruction Naming
609
610 @cindex i386 instruction naming
611 @cindex instruction naming, i386
612 @cindex x86-64 instruction naming
613 @cindex instruction naming, x86-64
614
615 Instruction mnemonics are suffixed with one character modifiers which
616 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
617 and @samp{q} specify byte, word, long and quadruple word operands. If
618 no suffix is specified by an instruction then @code{@value{AS}} tries to
619 fill in the missing suffix based on the destination register operand
620 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
621 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
622 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
623 assembler which assumes that a missing mnemonic suffix implies long
624 operand size. (This incompatibility does not affect compiler output
625 since compilers always explicitly specify the mnemonic suffix.)
626
627 Almost all instructions have the same names in AT&T and Intel format.
628 There are a few exceptions. The sign extend and zero extend
629 instructions need two sizes to specify them. They need a size to
630 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
631 is accomplished by using two instruction mnemonic suffixes in AT&T
632 syntax. Base names for sign extend and zero extend are
633 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
634 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
635 are tacked on to this base name, the @emph{from} suffix before the
636 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
637 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
638 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
639 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
640 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
641 quadruple word).
642
643 @cindex encoding options, i386
644 @cindex encoding options, x86-64
645
646 Different encoding options can be specified via pseudo prefixes:
647
648 @itemize @bullet
649 @item
650 @samp{@{disp8@}} -- prefer 8-bit displacement.
651
652 @item
653 @samp{@{disp32@}} -- prefer 32-bit displacement.
654
655 @item
656 @samp{@{load@}} -- prefer load-form instruction.
657
658 @item
659 @samp{@{store@}} -- prefer store-form instruction.
660
661 @item
662 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
663
664 @item
665 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
666
667 @item
668 @samp{@{evex@}} -- encode with EVEX prefix.
669
670 @item
671 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
672 instructions (x86-64 only). Note that this differs from the @samp{rex}
673 prefix which generates REX prefix unconditionally.
674
675 @item
676 @samp{@{nooptimize@}} -- disable instruction size optimization.
677 @end itemize
678
679 @cindex conversion instructions, i386
680 @cindex i386 conversion instructions
681 @cindex conversion instructions, x86-64
682 @cindex x86-64 conversion instructions
683 The Intel-syntax conversion instructions
684
685 @itemize @bullet
686 @item
687 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
688
689 @item
690 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
691
692 @item
693 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
694
695 @item
696 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
697
698 @item
699 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
700 (x86-64 only),
701
702 @item
703 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
704 @samp{%rdx:%rax} (x86-64 only),
705 @end itemize
706
707 @noindent
708 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
709 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
710 instructions.
711
712 @cindex jump instructions, i386
713 @cindex call instructions, i386
714 @cindex jump instructions, x86-64
715 @cindex call instructions, x86-64
716 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
717 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
718 convention.
719
720 @subsection AT&T Mnemonic versus Intel Mnemonic
721
722 @cindex i386 mnemonic compatibility
723 @cindex mnemonic compatibility, i386
724
725 @code{@value{AS}} supports assembly using Intel mnemonic.
726 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
727 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
728 syntax for compatibility with the output of @code{@value{GCC}}.
729 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
730 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
731 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
732 assembler with different mnemonics from those in Intel IA32 specification.
733 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
734
735 @node i386-Regs
736 @section Register Naming
737
738 @cindex i386 registers
739 @cindex registers, i386
740 @cindex x86-64 registers
741 @cindex registers, x86-64
742 Register operands are always prefixed with @samp{%}. The 80386 registers
743 consist of
744
745 @itemize @bullet
746 @item
747 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
748 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
749 frame pointer), and @samp{%esp} (the stack pointer).
750
751 @item
752 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
753 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
754
755 @item
756 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
757 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
758 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
759 @samp{%cx}, and @samp{%dx})
760
761 @item
762 the 6 section registers @samp{%cs} (code section), @samp{%ds}
763 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
764 and @samp{%gs}.
765
766 @item
767 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
768 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
769
770 @item
771 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
772 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
773
774 @item
775 the 2 test registers @samp{%tr6} and @samp{%tr7}.
776
777 @item
778 the 8 floating point register stack @samp{%st} or equivalently
779 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
780 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
781 These registers are overloaded by 8 MMX registers @samp{%mm0},
782 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
783 @samp{%mm6} and @samp{%mm7}.
784
785 @item
786 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
787 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
788 @end itemize
789
790 The AMD x86-64 architecture extends the register set by:
791
792 @itemize @bullet
793 @item
794 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
795 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
796 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
797 pointer)
798
799 @item
800 the 8 extended registers @samp{%r8}--@samp{%r15}.
801
802 @item
803 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
804
805 @item
806 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
807
808 @item
809 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
810
811 @item
812 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
813
814 @item
815 the 8 debug registers: @samp{%db8}--@samp{%db15}.
816
817 @item
818 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
819 @end itemize
820
821 With the AVX extensions more registers were made available:
822
823 @itemize @bullet
824
825 @item
826 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
827 available in 32-bit mode). The bottom 128 bits are overlaid with the
828 @samp{xmm0}--@samp{xmm15} registers.
829
830 @end itemize
831
832 The AVX2 extensions made in 64-bit mode more registers available:
833
834 @itemize @bullet
835
836 @item
837 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
838 registers @samp{%ymm16}--@samp{%ymm31}.
839
840 @end itemize
841
842 The AVX512 extensions added the following registers:
843
844 @itemize @bullet
845
846 @item
847 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
848 available in 32-bit mode). The bottom 128 bits are overlaid with the
849 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
850 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
851
852 @item
853 the 8 mask registers @samp{%k0}--@samp{%k7}.
854
855 @end itemize
856
857 @node i386-Prefixes
858 @section Instruction Prefixes
859
860 @cindex i386 instruction prefixes
861 @cindex instruction prefixes, i386
862 @cindex prefixes, i386
863 Instruction prefixes are used to modify the following instruction. They
864 are used to repeat string instructions, to provide section overrides, to
865 perform bus lock operations, and to change operand and address sizes.
866 (Most instructions that normally operate on 32-bit operands will use
867 16-bit operands if the instruction has an ``operand size'' prefix.)
868 Instruction prefixes are best written on the same line as the instruction
869 they act upon. For example, the @samp{scas} (scan string) instruction is
870 repeated with:
871
872 @smallexample
873 repne scas %es:(%edi),%al
874 @end smallexample
875
876 You may also place prefixes on the lines immediately preceding the
877 instruction, but this circumvents checks that @code{@value{AS}} does
878 with prefixes, and will not work with all prefixes.
879
880 Here is a list of instruction prefixes:
881
882 @cindex section override prefixes, i386
883 @itemize @bullet
884 @item
885 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
886 @samp{fs}, @samp{gs}. These are automatically added by specifying
887 using the @var{section}:@var{memory-operand} form for memory references.
888
889 @cindex size prefixes, i386
890 @item
891 Operand/Address size prefixes @samp{data16} and @samp{addr16}
892 change 32-bit operands/addresses into 16-bit operands/addresses,
893 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
894 @code{.code16} section) into 32-bit operands/addresses. These prefixes
895 @emph{must} appear on the same line of code as the instruction they
896 modify. For example, in a 16-bit @code{.code16} section, you might
897 write:
898
899 @smallexample
900 addr32 jmpl *(%ebx)
901 @end smallexample
902
903 @cindex bus lock prefixes, i386
904 @cindex inhibiting interrupts, i386
905 @item
906 The bus lock prefix @samp{lock} inhibits interrupts during execution of
907 the instruction it precedes. (This is only valid with certain
908 instructions; see a 80386 manual for details).
909
910 @cindex coprocessor wait, i386
911 @item
912 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
913 complete the current instruction. This should never be needed for the
914 80386/80387 combination.
915
916 @cindex repeat prefixes, i386
917 @item
918 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
919 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
920 times if the current address size is 16-bits).
921 @cindex REX prefixes, i386
922 @item
923 The @samp{rex} family of prefixes is used by x86-64 to encode
924 extensions to i386 instruction set. The @samp{rex} prefix has four
925 bits --- an operand size overwrite (@code{64}) used to change operand size
926 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
927 register set.
928
929 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
930 instruction emits @samp{rex} prefix with all the bits set. By omitting
931 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
932 prefixes as well. Normally, there is no need to write the prefixes
933 explicitly, since gas will automatically generate them based on the
934 instruction operands.
935 @end itemize
936
937 @node i386-Memory
938 @section Memory References
939
940 @cindex i386 memory references
941 @cindex memory references, i386
942 @cindex x86-64 memory references
943 @cindex memory references, x86-64
944 An Intel syntax indirect memory reference of the form
945
946 @smallexample
947 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
948 @end smallexample
949
950 @noindent
951 is translated into the AT&T syntax
952
953 @smallexample
954 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
955 @end smallexample
956
957 @noindent
958 where @var{base} and @var{index} are the optional 32-bit base and
959 index registers, @var{disp} is the optional displacement, and
960 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
961 to calculate the address of the operand. If no @var{scale} is
962 specified, @var{scale} is taken to be 1. @var{section} specifies the
963 optional section register for the memory operand, and may override the
964 default section register (see a 80386 manual for section register
965 defaults). Note that section overrides in AT&T syntax @emph{must}
966 be preceded by a @samp{%}. If you specify a section override which
967 coincides with the default section register, @code{@value{AS}} does @emph{not}
968 output any section register override prefixes to assemble the given
969 instruction. Thus, section overrides can be specified to emphasize which
970 section register is used for a given memory operand.
971
972 Here are some examples of Intel and AT&T style memory references:
973
974 @table @asis
975 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
976 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
977 missing, and the default section is used (@samp{%ss} for addressing with
978 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
979
980 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
981 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
982 @samp{foo}. All other fields are missing. The section register here
983 defaults to @samp{%ds}.
984
985 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
986 This uses the value pointed to by @samp{foo} as a memory operand.
987 Note that @var{base} and @var{index} are both missing, but there is only
988 @emph{one} @samp{,}. This is a syntactic exception.
989
990 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
991 This selects the contents of the variable @samp{foo} with section
992 register @var{section} being @samp{%gs}.
993 @end table
994
995 Absolute (as opposed to PC relative) call and jump operands must be
996 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
997 always chooses PC relative addressing for jump/call labels.
998
999 Any instruction that has a memory operand, but no register operand,
1000 @emph{must} specify its size (byte, word, long, or quadruple) with an
1001 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1002 respectively).
1003
1004 The x86-64 architecture adds an RIP (instruction pointer relative)
1005 addressing. This addressing mode is specified by using @samp{rip} as a
1006 base register. Only constant offsets are valid. For example:
1007
1008 @table @asis
1009 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1010 Points to the address 1234 bytes past the end of the current
1011 instruction.
1012
1013 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1014 Points to the @code{symbol} in RIP relative way, this is shorter than
1015 the default absolute addressing.
1016 @end table
1017
1018 Other addressing modes remain unchanged in x86-64 architecture, except
1019 registers used are 64-bit instead of 32-bit.
1020
1021 @node i386-Jumps
1022 @section Handling of Jump Instructions
1023
1024 @cindex jump optimization, i386
1025 @cindex i386 jump optimization
1026 @cindex jump optimization, x86-64
1027 @cindex x86-64 jump optimization
1028 Jump instructions are always optimized to use the smallest possible
1029 displacements. This is accomplished by using byte (8-bit) displacement
1030 jumps whenever the target is sufficiently close. If a byte displacement
1031 is insufficient a long displacement is used. We do not support
1032 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1033 instruction with the @samp{data16} instruction prefix), since the 80386
1034 insists upon masking @samp{%eip} to 16 bits after the word displacement
1035 is added. (See also @pxref{i386-Arch})
1036
1037 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1038 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1039 displacements, so that if you use these instructions (@code{@value{GCC}} does
1040 not use them) you may get an error message (and incorrect code). The AT&T
1041 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1042 to
1043
1044 @smallexample
1045 jcxz cx_zero
1046 jmp cx_nonzero
1047 cx_zero: jmp foo
1048 cx_nonzero:
1049 @end smallexample
1050
1051 @node i386-Float
1052 @section Floating Point
1053
1054 @cindex i386 floating point
1055 @cindex floating point, i386
1056 @cindex x86-64 floating point
1057 @cindex floating point, x86-64
1058 All 80387 floating point types except packed BCD are supported.
1059 (BCD support may be added without much difficulty). These data
1060 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1061 double (64-bit), and extended (80-bit) precision floating point.
1062 Each supported type has an instruction mnemonic suffix and a constructor
1063 associated with it. Instruction mnemonic suffixes specify the operand's
1064 data type. Constructors build these data types into memory.
1065
1066 @cindex @code{float} directive, i386
1067 @cindex @code{single} directive, i386
1068 @cindex @code{double} directive, i386
1069 @cindex @code{tfloat} directive, i386
1070 @cindex @code{float} directive, x86-64
1071 @cindex @code{single} directive, x86-64
1072 @cindex @code{double} directive, x86-64
1073 @cindex @code{tfloat} directive, x86-64
1074 @itemize @bullet
1075 @item
1076 Floating point constructors are @samp{.float} or @samp{.single},
1077 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1078 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1079 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1080 only supports this format via the @samp{fldt} (load 80-bit real to stack
1081 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1082
1083 @cindex @code{word} directive, i386
1084 @cindex @code{long} directive, i386
1085 @cindex @code{int} directive, i386
1086 @cindex @code{quad} directive, i386
1087 @cindex @code{word} directive, x86-64
1088 @cindex @code{long} directive, x86-64
1089 @cindex @code{int} directive, x86-64
1090 @cindex @code{quad} directive, x86-64
1091 @item
1092 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1093 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1094 corresponding instruction mnemonic suffixes are @samp{s} (single),
1095 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1096 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1097 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1098 stack) instructions.
1099 @end itemize
1100
1101 Register to register operations should not use instruction mnemonic suffixes.
1102 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1103 wrote @samp{fst %st, %st(1)}, since all register to register operations
1104 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1105 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1106 then stores the result in the 4 byte location @samp{mem})
1107
1108 @node i386-SIMD
1109 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1110
1111 @cindex MMX, i386
1112 @cindex 3DNow!, i386
1113 @cindex SIMD, i386
1114 @cindex MMX, x86-64
1115 @cindex 3DNow!, x86-64
1116 @cindex SIMD, x86-64
1117
1118 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1119 instructions for integer data), available on Intel's Pentium MMX
1120 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1121 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1122 instruction set (SIMD instructions for 32-bit floating point data)
1123 available on AMD's K6-2 processor and possibly others in the future.
1124
1125 Currently, @code{@value{AS}} does not support Intel's floating point
1126 SIMD, Katmai (KNI).
1127
1128 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1129 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1130 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1131 floating point values. The MMX registers cannot be used at the same time
1132 as the floating point stack.
1133
1134 See Intel and AMD documentation, keeping in mind that the operand order in
1135 instructions is reversed from the Intel syntax.
1136
1137 @node i386-LWP
1138 @section AMD's Lightweight Profiling Instructions
1139
1140 @cindex LWP, i386
1141 @cindex LWP, x86-64
1142
1143 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1144 instruction set, available on AMD's Family 15h (Orochi) processors.
1145
1146 LWP enables applications to collect and manage performance data, and
1147 react to performance events. The collection of performance data
1148 requires no context switches. LWP runs in the context of a thread and
1149 so several counters can be used independently across multiple threads.
1150 LWP can be used in both 64-bit and legacy 32-bit modes.
1151
1152 For detailed information on the LWP instruction set, see the
1153 @cite{AMD Lightweight Profiling Specification} available at
1154 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1155
1156 @node i386-BMI
1157 @section Bit Manipulation Instructions
1158
1159 @cindex BMI, i386
1160 @cindex BMI, x86-64
1161
1162 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1163
1164 BMI instructions provide several instructions implementing individual
1165 bit manipulation operations such as isolation, masking, setting, or
1166 resetting.
1167
1168 @c Need to add a specification citation here when available.
1169
1170 @node i386-TBM
1171 @section AMD's Trailing Bit Manipulation Instructions
1172
1173 @cindex TBM, i386
1174 @cindex TBM, x86-64
1175
1176 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1177 instruction set, available on AMD's BDVER2 processors (Trinity and
1178 Viperfish).
1179
1180 TBM instructions provide instructions implementing individual bit
1181 manipulation operations such as isolating, masking, setting, resetting,
1182 complementing, and operations on trailing zeros and ones.
1183
1184 @c Need to add a specification citation here when available.
1185
1186 @node i386-16bit
1187 @section Writing 16-bit Code
1188
1189 @cindex i386 16-bit code
1190 @cindex 16-bit code, i386
1191 @cindex real-mode code, i386
1192 @cindex @code{code16gcc} directive, i386
1193 @cindex @code{code16} directive, i386
1194 @cindex @code{code32} directive, i386
1195 @cindex @code{code64} directive, i386
1196 @cindex @code{code64} directive, x86-64
1197 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1198 or 64-bit x86-64 code depending on the default configuration,
1199 it also supports writing code to run in real mode or in 16-bit protected
1200 mode code segments. To do this, put a @samp{.code16} or
1201 @samp{.code16gcc} directive before the assembly language instructions to
1202 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1203 32-bit code with the @samp{.code32} directive or 64-bit code with the
1204 @samp{.code64} directive.
1205
1206 @samp{.code16gcc} provides experimental support for generating 16-bit
1207 code from gcc, and differs from @samp{.code16} in that @samp{call},
1208 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1209 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1210 default to 32-bit size. This is so that the stack pointer is
1211 manipulated in the same way over function calls, allowing access to
1212 function parameters at the same stack offsets as in 32-bit mode.
1213 @samp{.code16gcc} also automatically adds address size prefixes where
1214 necessary to use the 32-bit addressing modes that gcc generates.
1215
1216 The code which @code{@value{AS}} generates in 16-bit mode will not
1217 necessarily run on a 16-bit pre-80386 processor. To write code that
1218 runs on such a processor, you must refrain from using @emph{any} 32-bit
1219 constructs which require @code{@value{AS}} to output address or operand
1220 size prefixes.
1221
1222 Note that writing 16-bit code instructions by explicitly specifying a
1223 prefix or an instruction mnemonic suffix within a 32-bit code section
1224 generates different machine instructions than those generated for a
1225 16-bit code segment. In a 32-bit code section, the following code
1226 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1227 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1228
1229 @smallexample
1230 pushw $4
1231 @end smallexample
1232
1233 The same code in a 16-bit code section would generate the machine
1234 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1235 is correct since the processor default operand size is assumed to be 16
1236 bits in a 16-bit code section.
1237
1238 @node i386-Arch
1239 @section Specifying CPU Architecture
1240
1241 @cindex arch directive, i386
1242 @cindex i386 arch directive
1243 @cindex arch directive, x86-64
1244 @cindex x86-64 arch directive
1245
1246 @code{@value{AS}} may be told to assemble for a particular CPU
1247 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1248 directive enables a warning when gas detects an instruction that is not
1249 supported on the CPU specified. The choices for @var{cpu_type} are:
1250
1251 @multitable @columnfractions .20 .20 .20 .20
1252 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1253 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1254 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1255 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1256 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
1257 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1258 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1259 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
1260 @item @samp{generic32} @tab @samp{generic64}
1261 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1262 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1263 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1264 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1265 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1266 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1267 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1268 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1269 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1270 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1271 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1272 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1273 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1274 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1275 @item @samp{.avx512_bitalg}
1276 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1277 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1278 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1279 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1280 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1281 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1282 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1283 @end multitable
1284
1285 Apart from the warning, there are only two other effects on
1286 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1287 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1288 will automatically use a two byte opcode sequence. The larger three
1289 byte opcode sequence is used on the 486 (and when no architecture is
1290 specified) because it executes faster on the 486. Note that you can
1291 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1292 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1293 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1294 conditional jumps will be promoted when necessary to a two instruction
1295 sequence consisting of a conditional jump of the opposite sense around
1296 an unconditional jump to the target.
1297
1298 Following the CPU architecture (but not a sub-architecture, which are those
1299 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1300 control automatic promotion of conditional jumps. @samp{jumps} is the
1301 default, and enables jump promotion; All external jumps will be of the long
1302 variety, and file-local jumps will be promoted as necessary.
1303 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1304 byte offset jumps, and warns about file-local conditional jumps that
1305 @code{@value{AS}} promotes.
1306 Unconditional jumps are treated as for @samp{jumps}.
1307
1308 For example
1309
1310 @smallexample
1311 .arch i8086,nojumps
1312 @end smallexample
1313
1314 @node i386-Bugs
1315 @section AT&T Syntax bugs
1316
1317 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1318 assemblers, generate floating point instructions with reversed source
1319 and destination registers in certain cases. Unfortunately, gcc and
1320 possibly many other programs use this reversed syntax, so we're stuck
1321 with it.
1322
1323 For example
1324
1325 @smallexample
1326 fsub %st,%st(3)
1327 @end smallexample
1328 @noindent
1329 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1330 than the expected @samp{%st(3) - %st}. This happens with all the
1331 non-commutative arithmetic floating point operations with two register
1332 operands where the source register is @samp{%st} and the destination
1333 register is @samp{%st(i)}.
1334
1335 @node i386-Notes
1336 @section Notes
1337
1338 @cindex i386 @code{mul}, @code{imul} instructions
1339 @cindex @code{mul} instruction, i386
1340 @cindex @code{imul} instruction, i386
1341 @cindex @code{mul} instruction, x86-64
1342 @cindex @code{imul} instruction, x86-64
1343 There is some trickery concerning the @samp{mul} and @samp{imul}
1344 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1345 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1346 for @samp{imul}) can be output only in the one operand form. Thus,
1347 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1348 the expanding multiply would clobber the @samp{%edx} register, and this
1349 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1350 64-bit product in @samp{%edx:%eax}.
1351
1352 We have added a two operand form of @samp{imul} when the first operand
1353 is an immediate mode expression and the second operand is a register.
1354 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1355 example, can be done with @samp{imul $69, %eax} rather than @samp{imul
1356 $69, %eax, %eax}.
1357
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