1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
2 @c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
11 @chapter 80386 Dependent Features
14 @node Machine Dependencies
15 @chapter 80386 Dependent Features
19 @cindex i80386 support
20 @cindex x86-64 support
22 The i386 version @code{@value{AS}} supports both the original Intel 386
23 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
24 extending the Intel architecture to 64-bits.
27 * i386-Options:: Options
28 * i386-Directives:: X86 specific directives
29 * i386-Syntax:: Syntactical considerations
30 * i386-Mnemonics:: Instruction Naming
31 * i386-Regs:: Register Naming
32 * i386-Prefixes:: Instruction Prefixes
33 * i386-Memory:: Memory References
34 * i386-Jumps:: Handling of Jump Instructions
35 * i386-Float:: Floating Point
36 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
37 * i386-LWP:: AMD's Lightweight Profiling Instructions
38 * i386-BMI:: Bit Manipulation Instruction
39 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
40 * i386-16bit:: Writing 16-bit Code
41 * i386-Arch:: Specifying an x86 CPU architecture
42 * i386-Bugs:: AT&T Syntax bugs
49 @cindex options for i386
50 @cindex options for x86-64
52 @cindex x86-64 options
54 The i386 version of @code{@value{AS}} has a few machine
59 @cindex @samp{--32} option, i386
60 @cindex @samp{--32} option, x86-64
61 @cindex @samp{--x32} option, i386
62 @cindex @samp{--x32} option, x86-64
63 @cindex @samp{--64} option, i386
64 @cindex @samp{--64} option, x86-64
65 @item --32 | --x32 | --64
66 Select the word size, either 32 bits or 64 bits. @samp{--32}
67 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
68 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
71 These options are only available with the ELF object file format, and
72 require that the necessary BFD support has been included (on a 32-bit
73 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
74 usage and use x86-64 as target platform).
77 By default, x86 GAS replaces multiple nop instructions used for
78 alignment within code sections with multi-byte nop instructions such
79 as leal 0(%esi,1),%esi. This switch disables the optimization.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
126 In addition to the basic instruction set, the assembler can be told to
127 accept various extension mnemonics. For example,
128 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
129 @var{vmx}. The following extensions are currently supported:
181 Note that rather than extending a basic instruction set, the extension
182 mnemonics starting with @code{no} revoke the respective functionality.
184 When the @code{.arch} directive is used with @option{-march}, the
185 @code{.arch} directive will take precedent.
187 @cindex @samp{-mtune=} option, i386
188 @cindex @samp{-mtune=} option, x86-64
189 @item -mtune=@var{CPU}
190 This option specifies a processor to optimize for. When used in
191 conjunction with the @option{-march} option, only instructions
192 of the processor specified by the @option{-march} option will be
195 Valid @var{CPU} values are identical to the processor list of
196 @option{-march=@var{CPU}}.
198 @cindex @samp{-msse2avx} option, i386
199 @cindex @samp{-msse2avx} option, x86-64
201 This option specifies that the assembler should encode SSE instructions
204 @cindex @samp{-msse-check=} option, i386
205 @cindex @samp{-msse-check=} option, x86-64
206 @item -msse-check=@var{none}
207 @itemx -msse-check=@var{warning}
208 @itemx -msse-check=@var{error}
209 These options control if the assembler should check SSE intructions.
210 @option{-msse-check=@var{none}} will make the assembler not to check SSE
211 instructions, which is the default. @option{-msse-check=@var{warning}}
212 will make the assembler issue a warning for any SSE intruction.
213 @option{-msse-check=@var{error}} will make the assembler issue an error
214 for any SSE intruction.
216 @cindex @samp{-mavxscalar=} option, i386
217 @cindex @samp{-mavxscalar=} option, x86-64
218 @item -mavxscalar=@var{128}
219 @itemx -mavxscalar=@var{256}
220 These options control how the assembler should encode scalar AVX
221 instructions. @option{-mavxscalar=@var{128}} will encode scalar
222 AVX instructions with 128bit vector length, which is the default.
223 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
224 with 256bit vector length.
226 @cindex @samp{-mmnemonic=} option, i386
227 @cindex @samp{-mmnemonic=} option, x86-64
228 @item -mmnemonic=@var{att}
229 @itemx -mmnemonic=@var{intel}
230 This option specifies instruction mnemonic for matching instructions.
231 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
234 @cindex @samp{-msyntax=} option, i386
235 @cindex @samp{-msyntax=} option, x86-64
236 @item -msyntax=@var{att}
237 @itemx -msyntax=@var{intel}
238 This option specifies instruction syntax when processing instructions.
239 The @code{.att_syntax} and @code{.intel_syntax} directives will
242 @cindex @samp{-mnaked-reg} option, i386
243 @cindex @samp{-mnaked-reg} option, x86-64
245 This opetion specifies that registers don't require a @samp{%} prefix.
246 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
251 @node i386-Directives
252 @section x86 specific Directives
254 @cindex machine directives, x86
255 @cindex x86 machine directives
258 @cindex @code{lcomm} directive, COFF
259 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
260 Reserve @var{length} (an absolute expression) bytes for a local common
261 denoted by @var{symbol}. The section and value of @var{symbol} are
262 those of the new local common. The addresses are allocated in the bss
263 section, so that at run-time the bytes start off zeroed. Since
264 @var{symbol} is not declared global, it is normally not visible to
265 @code{@value{LD}}. The optional third parameter, @var{alignment},
266 specifies the desired alignment of the symbol in the bss section.
268 This directive is only available for COFF based x86 targets.
270 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
276 @section i386 Syntactical Considerations
278 * i386-Variations:: AT&T Syntax versus Intel Syntax
279 * i386-Chars:: Special Characters
282 @node i386-Variations
283 @subsection AT&T Syntax versus Intel Syntax
285 @cindex i386 intel_syntax pseudo op
286 @cindex intel_syntax pseudo op, i386
287 @cindex i386 att_syntax pseudo op
288 @cindex att_syntax pseudo op, i386
289 @cindex i386 syntax compatibility
290 @cindex syntax compatibility, i386
291 @cindex x86-64 intel_syntax pseudo op
292 @cindex intel_syntax pseudo op, x86-64
293 @cindex x86-64 att_syntax pseudo op
294 @cindex att_syntax pseudo op, x86-64
295 @cindex x86-64 syntax compatibility
296 @cindex syntax compatibility, x86-64
298 @code{@value{AS}} now supports assembly using Intel assembler syntax.
299 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
300 back to the usual AT&T mode for compatibility with the output of
301 @code{@value{GCC}}. Either of these directives may have an optional
302 argument, @code{prefix}, or @code{noprefix} specifying whether registers
303 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
304 different from Intel syntax. We mention these differences because
305 almost all 80386 documents use Intel syntax. Notable differences
306 between the two syntaxes are:
308 @cindex immediate operands, i386
309 @cindex i386 immediate operands
310 @cindex register operands, i386
311 @cindex i386 register operands
312 @cindex jump/call operands, i386
313 @cindex i386 jump/call operands
314 @cindex operand delimiters, i386
316 @cindex immediate operands, x86-64
317 @cindex x86-64 immediate operands
318 @cindex register operands, x86-64
319 @cindex x86-64 register operands
320 @cindex jump/call operands, x86-64
321 @cindex x86-64 jump/call operands
322 @cindex operand delimiters, x86-64
325 AT&T immediate operands are preceded by @samp{$}; Intel immediate
326 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
327 AT&T register operands are preceded by @samp{%}; Intel register operands
328 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
329 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
331 @cindex i386 source, destination operands
332 @cindex source, destination operands; i386
333 @cindex x86-64 source, destination operands
334 @cindex source, destination operands; x86-64
336 AT&T and Intel syntax use the opposite order for source and destination
337 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
338 @samp{source, dest} convention is maintained for compatibility with
339 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
340 instructions with 2 immediate operands, such as the @samp{enter}
341 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
343 @cindex mnemonic suffixes, i386
344 @cindex sizes operands, i386
345 @cindex i386 size suffixes
346 @cindex mnemonic suffixes, x86-64
347 @cindex sizes operands, x86-64
348 @cindex x86-64 size suffixes
350 In AT&T syntax the size of memory operands is determined from the last
351 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
352 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
353 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
354 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
355 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
356 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
359 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
360 instruction with the 64-bit displacement or immediate operand.
362 @cindex return instructions, i386
363 @cindex i386 jump, call, return
364 @cindex return instructions, x86-64
365 @cindex x86-64 jump, call, return
367 Immediate form long jumps and calls are
368 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
370 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
372 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
373 @samp{ret far @var{stack-adjust}}.
375 @cindex sections, i386
376 @cindex i386 sections
377 @cindex sections, x86-64
378 @cindex x86-64 sections
380 The AT&T assembler does not provide support for multiple section
381 programs. Unix style systems expect all programs to be single sections.
385 @subsection Special Characters
387 @cindex line comment character, i386
388 @cindex i386 line comment character
389 The presence of a @samp{#} appearing anywhere on a line indicates the
390 start of a comment that extends to the end of that line.
392 If a @samp{#} appears as the first character of a line then the whole
393 line is treated as a comment, but in this case the line can also be a
394 logical line number directive (@pxref{Comments}) or a preprocessor
395 control command (@pxref{Preprocessing}).
397 If the @option{--divide} command line option has not been specified
398 then the @samp{/} character appearing anywhere on a line also
399 introduces a line comment.
401 @cindex line separator, i386
402 @cindex statement separator, i386
403 @cindex i386 line separator
404 The @samp{;} character can be used to separate statements on the same
408 @section Instruction Naming
410 @cindex i386 instruction naming
411 @cindex instruction naming, i386
412 @cindex x86-64 instruction naming
413 @cindex instruction naming, x86-64
415 Instruction mnemonics are suffixed with one character modifiers which
416 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
417 and @samp{q} specify byte, word, long and quadruple word operands. If
418 no suffix is specified by an instruction then @code{@value{AS}} tries to
419 fill in the missing suffix based on the destination register operand
420 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
421 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
422 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
423 assembler which assumes that a missing mnemonic suffix implies long
424 operand size. (This incompatibility does not affect compiler output
425 since compilers always explicitly specify the mnemonic suffix.)
427 Almost all instructions have the same names in AT&T and Intel format.
428 There are a few exceptions. The sign extend and zero extend
429 instructions need two sizes to specify them. They need a size to
430 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
431 is accomplished by using two instruction mnemonic suffixes in AT&T
432 syntax. Base names for sign extend and zero extend are
433 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
434 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
435 are tacked on to this base name, the @emph{from} suffix before the
436 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
437 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
438 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
439 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
440 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
443 @cindex encoding options, i386
444 @cindex encoding options, x86-64
446 Different encoding options can be specified via optional mnemonic
447 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
448 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
449 prefers 8bit or 32bit displacement in encoding.
451 @cindex conversion instructions, i386
452 @cindex i386 conversion instructions
453 @cindex conversion instructions, x86-64
454 @cindex x86-64 conversion instructions
455 The Intel-syntax conversion instructions
459 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
462 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
465 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
468 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
471 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
475 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
476 @samp{%rdx:%rax} (x86-64 only),
480 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
481 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
484 @cindex jump instructions, i386
485 @cindex call instructions, i386
486 @cindex jump instructions, x86-64
487 @cindex call instructions, x86-64
488 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
489 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
492 @section AT&T Mnemonic versus Intel Mnemonic
494 @cindex i386 mnemonic compatibility
495 @cindex mnemonic compatibility, i386
497 @code{@value{AS}} supports assembly using Intel mnemonic.
498 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
499 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
500 syntax for compatibility with the output of @code{@value{GCC}}.
501 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
502 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
503 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
504 assembler with different mnemonics from those in Intel IA32 specification.
505 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
508 @section Register Naming
510 @cindex i386 registers
511 @cindex registers, i386
512 @cindex x86-64 registers
513 @cindex registers, x86-64
514 Register operands are always prefixed with @samp{%}. The 80386 registers
519 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
520 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
521 frame pointer), and @samp{%esp} (the stack pointer).
524 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
525 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
528 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
529 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
530 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
531 @samp{%cx}, and @samp{%dx})
534 the 6 section registers @samp{%cs} (code section), @samp{%ds}
535 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
539 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
543 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
544 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
547 the 2 test registers @samp{%tr6} and @samp{%tr7}.
550 the 8 floating point register stack @samp{%st} or equivalently
551 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
552 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
553 These registers are overloaded by 8 MMX registers @samp{%mm0},
554 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
555 @samp{%mm6} and @samp{%mm7}.
558 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
559 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
562 The AMD x86-64 architecture extends the register set by:
566 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
567 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
568 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
572 the 8 extended registers @samp{%r8}--@samp{%r15}.
575 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
578 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
581 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
584 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
587 the 8 debug registers: @samp{%db8}--@samp{%db15}.
590 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
594 @section Instruction Prefixes
596 @cindex i386 instruction prefixes
597 @cindex instruction prefixes, i386
598 @cindex prefixes, i386
599 Instruction prefixes are used to modify the following instruction. They
600 are used to repeat string instructions, to provide section overrides, to
601 perform bus lock operations, and to change operand and address sizes.
602 (Most instructions that normally operate on 32-bit operands will use
603 16-bit operands if the instruction has an ``operand size'' prefix.)
604 Instruction prefixes are best written on the same line as the instruction
605 they act upon. For example, the @samp{scas} (scan string) instruction is
609 repne scas %es:(%edi),%al
612 You may also place prefixes on the lines immediately preceding the
613 instruction, but this circumvents checks that @code{@value{AS}} does
614 with prefixes, and will not work with all prefixes.
616 Here is a list of instruction prefixes:
618 @cindex section override prefixes, i386
621 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
622 @samp{fs}, @samp{gs}. These are automatically added by specifying
623 using the @var{section}:@var{memory-operand} form for memory references.
625 @cindex size prefixes, i386
627 Operand/Address size prefixes @samp{data16} and @samp{addr16}
628 change 32-bit operands/addresses into 16-bit operands/addresses,
629 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
630 @code{.code16} section) into 32-bit operands/addresses. These prefixes
631 @emph{must} appear on the same line of code as the instruction they
632 modify. For example, in a 16-bit @code{.code16} section, you might
639 @cindex bus lock prefixes, i386
640 @cindex inhibiting interrupts, i386
642 The bus lock prefix @samp{lock} inhibits interrupts during execution of
643 the instruction it precedes. (This is only valid with certain
644 instructions; see a 80386 manual for details).
646 @cindex coprocessor wait, i386
648 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
649 complete the current instruction. This should never be needed for the
650 80386/80387 combination.
652 @cindex repeat prefixes, i386
654 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
655 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
656 times if the current address size is 16-bits).
657 @cindex REX prefixes, i386
659 The @samp{rex} family of prefixes is used by x86-64 to encode
660 extensions to i386 instruction set. The @samp{rex} prefix has four
661 bits --- an operand size overwrite (@code{64}) used to change operand size
662 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
665 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
666 instruction emits @samp{rex} prefix with all the bits set. By omitting
667 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
668 prefixes as well. Normally, there is no need to write the prefixes
669 explicitly, since gas will automatically generate them based on the
670 instruction operands.
674 @section Memory References
676 @cindex i386 memory references
677 @cindex memory references, i386
678 @cindex x86-64 memory references
679 @cindex memory references, x86-64
680 An Intel syntax indirect memory reference of the form
683 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
687 is translated into the AT&T syntax
690 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
694 where @var{base} and @var{index} are the optional 32-bit base and
695 index registers, @var{disp} is the optional displacement, and
696 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
697 to calculate the address of the operand. If no @var{scale} is
698 specified, @var{scale} is taken to be 1. @var{section} specifies the
699 optional section register for the memory operand, and may override the
700 default section register (see a 80386 manual for section register
701 defaults). Note that section overrides in AT&T syntax @emph{must}
702 be preceded by a @samp{%}. If you specify a section override which
703 coincides with the default section register, @code{@value{AS}} does @emph{not}
704 output any section register override prefixes to assemble the given
705 instruction. Thus, section overrides can be specified to emphasize which
706 section register is used for a given memory operand.
708 Here are some examples of Intel and AT&T style memory references:
711 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
712 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
713 missing, and the default section is used (@samp{%ss} for addressing with
714 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
716 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
717 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
718 @samp{foo}. All other fields are missing. The section register here
719 defaults to @samp{%ds}.
721 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
722 This uses the value pointed to by @samp{foo} as a memory operand.
723 Note that @var{base} and @var{index} are both missing, but there is only
724 @emph{one} @samp{,}. This is a syntactic exception.
726 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
727 This selects the contents of the variable @samp{foo} with section
728 register @var{section} being @samp{%gs}.
731 Absolute (as opposed to PC relative) call and jump operands must be
732 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
733 always chooses PC relative addressing for jump/call labels.
735 Any instruction that has a memory operand, but no register operand,
736 @emph{must} specify its size (byte, word, long, or quadruple) with an
737 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
740 The x86-64 architecture adds an RIP (instruction pointer relative)
741 addressing. This addressing mode is specified by using @samp{rip} as a
742 base register. Only constant offsets are valid. For example:
745 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
746 Points to the address 1234 bytes past the end of the current
749 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
750 Points to the @code{symbol} in RIP relative way, this is shorter than
751 the default absolute addressing.
754 Other addressing modes remain unchanged in x86-64 architecture, except
755 registers used are 64-bit instead of 32-bit.
758 @section Handling of Jump Instructions
760 @cindex jump optimization, i386
761 @cindex i386 jump optimization
762 @cindex jump optimization, x86-64
763 @cindex x86-64 jump optimization
764 Jump instructions are always optimized to use the smallest possible
765 displacements. This is accomplished by using byte (8-bit) displacement
766 jumps whenever the target is sufficiently close. If a byte displacement
767 is insufficient a long displacement is used. We do not support
768 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
769 instruction with the @samp{data16} instruction prefix), since the 80386
770 insists upon masking @samp{%eip} to 16 bits after the word displacement
771 is added. (See also @pxref{i386-Arch})
773 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
774 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
775 displacements, so that if you use these instructions (@code{@value{GCC}} does
776 not use them) you may get an error message (and incorrect code). The AT&T
777 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
788 @section Floating Point
790 @cindex i386 floating point
791 @cindex floating point, i386
792 @cindex x86-64 floating point
793 @cindex floating point, x86-64
794 All 80387 floating point types except packed BCD are supported.
795 (BCD support may be added without much difficulty). These data
796 types are 16-, 32-, and 64- bit integers, and single (32-bit),
797 double (64-bit), and extended (80-bit) precision floating point.
798 Each supported type has an instruction mnemonic suffix and a constructor
799 associated with it. Instruction mnemonic suffixes specify the operand's
800 data type. Constructors build these data types into memory.
802 @cindex @code{float} directive, i386
803 @cindex @code{single} directive, i386
804 @cindex @code{double} directive, i386
805 @cindex @code{tfloat} directive, i386
806 @cindex @code{float} directive, x86-64
807 @cindex @code{single} directive, x86-64
808 @cindex @code{double} directive, x86-64
809 @cindex @code{tfloat} directive, x86-64
812 Floating point constructors are @samp{.float} or @samp{.single},
813 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
814 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
815 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
816 only supports this format via the @samp{fldt} (load 80-bit real to stack
817 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
819 @cindex @code{word} directive, i386
820 @cindex @code{long} directive, i386
821 @cindex @code{int} directive, i386
822 @cindex @code{quad} directive, i386
823 @cindex @code{word} directive, x86-64
824 @cindex @code{long} directive, x86-64
825 @cindex @code{int} directive, x86-64
826 @cindex @code{quad} directive, x86-64
828 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
829 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
830 corresponding instruction mnemonic suffixes are @samp{s} (single),
831 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
832 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
833 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
837 Register to register operations should not use instruction mnemonic suffixes.
838 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
839 wrote @samp{fst %st, %st(1)}, since all register to register operations
840 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
841 which converts @samp{%st} from 80-bit to 64-bit floating point format,
842 then stores the result in the 4 byte location @samp{mem})
845 @section Intel's MMX and AMD's 3DNow! SIMD Operations
851 @cindex 3DNow!, x86-64
854 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
855 instructions for integer data), available on Intel's Pentium MMX
856 processors and Pentium II processors, AMD's K6 and K6-2 processors,
857 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
858 instruction set (SIMD instructions for 32-bit floating point data)
859 available on AMD's K6-2 processor and possibly others in the future.
861 Currently, @code{@value{AS}} does not support Intel's floating point
864 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
865 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
866 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
867 floating point values. The MMX registers cannot be used at the same time
868 as the floating point stack.
870 See Intel and AMD documentation, keeping in mind that the operand order in
871 instructions is reversed from the Intel syntax.
874 @section AMD's Lightweight Profiling Instructions
879 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
880 instruction set, available on AMD's Family 15h (Orochi) processors.
882 LWP enables applications to collect and manage performance data, and
883 react to performance events. The collection of performance data
884 requires no context switches. LWP runs in the context of a thread and
885 so several counters can be used independently across multiple threads.
886 LWP can be used in both 64-bit and legacy 32-bit modes.
888 For detailed information on the LWP instruction set, see the
889 @cite{AMD Lightweight Profiling Specification} available at
890 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
893 @section Bit Manipulation Instructions
898 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
900 BMI instructions provide several instructions implementing individual
901 bit manipulation operations such as isolation, masking, setting, or
904 @c Need to add a specification citation here when available.
907 @section AMD's Trailing Bit Manipulation Instructions
912 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
913 instruction set, available on AMD's BDVER2 processors (Trinity and
916 TBM instructions provide instructions implementing individual bit
917 manipulation operations such as isolating, masking, setting, resetting,
918 complementing, and operations on trailing zeros and ones.
920 @c Need to add a specification citation here when available.
923 @section Writing 16-bit Code
925 @cindex i386 16-bit code
926 @cindex 16-bit code, i386
927 @cindex real-mode code, i386
928 @cindex @code{code16gcc} directive, i386
929 @cindex @code{code16} directive, i386
930 @cindex @code{code32} directive, i386
931 @cindex @code{code64} directive, i386
932 @cindex @code{code64} directive, x86-64
933 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
934 or 64-bit x86-64 code depending on the default configuration,
935 it also supports writing code to run in real mode or in 16-bit protected
936 mode code segments. To do this, put a @samp{.code16} or
937 @samp{.code16gcc} directive before the assembly language instructions to
938 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
939 32-bit code with the @samp{.code32} directive or 64-bit code with the
940 @samp{.code64} directive.
942 @samp{.code16gcc} provides experimental support for generating 16-bit
943 code from gcc, and differs from @samp{.code16} in that @samp{call},
944 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
945 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
946 default to 32-bit size. This is so that the stack pointer is
947 manipulated in the same way over function calls, allowing access to
948 function parameters at the same stack offsets as in 32-bit mode.
949 @samp{.code16gcc} also automatically adds address size prefixes where
950 necessary to use the 32-bit addressing modes that gcc generates.
952 The code which @code{@value{AS}} generates in 16-bit mode will not
953 necessarily run on a 16-bit pre-80386 processor. To write code that
954 runs on such a processor, you must refrain from using @emph{any} 32-bit
955 constructs which require @code{@value{AS}} to output address or operand
958 Note that writing 16-bit code instructions by explicitly specifying a
959 prefix or an instruction mnemonic suffix within a 32-bit code section
960 generates different machine instructions than those generated for a
961 16-bit code segment. In a 32-bit code section, the following code
962 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
963 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
969 The same code in a 16-bit code section would generate the machine
970 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
971 is correct since the processor default operand size is assumed to be 16
972 bits in a 16-bit code section.
975 @section AT&T Syntax bugs
977 The UnixWare assembler, and probably other AT&T derived ix86 Unix
978 assemblers, generate floating point instructions with reversed source
979 and destination registers in certain cases. Unfortunately, gcc and
980 possibly many other programs use this reversed syntax, so we're stuck
989 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
990 than the expected @samp{%st(3) - %st}. This happens with all the
991 non-commutative arithmetic floating point operations with two register
992 operands where the source register is @samp{%st} and the destination
993 register is @samp{%st(i)}.
996 @section Specifying CPU Architecture
998 @cindex arch directive, i386
999 @cindex i386 arch directive
1000 @cindex arch directive, x86-64
1001 @cindex x86-64 arch directive
1003 @code{@value{AS}} may be told to assemble for a particular CPU
1004 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1005 directive enables a warning when gas detects an instruction that is not
1006 supported on the CPU specified. The choices for @var{cpu_type} are:
1008 @multitable @columnfractions .20 .20 .20 .20
1009 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1010 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1011 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1012 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1013 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1014 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1015 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2}
1016 @item @samp{generic32} @tab @samp{generic64}
1017 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1018 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1019 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1020 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1021 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1022 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1023 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1024 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1025 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1026 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1027 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
1028 @item @samp{.padlock}
1031 Apart from the warning, there are only two other effects on
1032 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1033 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1034 will automatically use a two byte opcode sequence. The larger three
1035 byte opcode sequence is used on the 486 (and when no architecture is
1036 specified) because it executes faster on the 486. Note that you can
1037 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1038 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1039 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1040 conditional jumps will be promoted when necessary to a two instruction
1041 sequence consisting of a conditional jump of the opposite sense around
1042 an unconditional jump to the target.
1044 Following the CPU architecture (but not a sub-architecture, which are those
1045 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1046 control automatic promotion of conditional jumps. @samp{jumps} is the
1047 default, and enables jump promotion; All external jumps will be of the long
1048 variety, and file-local jumps will be promoted as necessary.
1049 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1050 byte offset jumps, and warns about file-local conditional jumps that
1051 @code{@value{AS}} promotes.
1052 Unconditional jumps are treated as for @samp{jumps}.
1063 @cindex i386 @code{mul}, @code{imul} instructions
1064 @cindex @code{mul} instruction, i386
1065 @cindex @code{imul} instruction, i386
1066 @cindex @code{mul} instruction, x86-64
1067 @cindex @code{imul} instruction, x86-64
1068 There is some trickery concerning the @samp{mul} and @samp{imul}
1069 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1070 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1071 for @samp{imul}) can be output only in the one operand form. Thus,
1072 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1073 the expanding multiply would clobber the @samp{%edx} register, and this
1074 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1075 64-bit product in @samp{%edx:%eax}.
1077 We have added a two operand form of @samp{imul} when the first operand
1078 is an immediate mode expression and the second operand is a register.
1079 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1080 example, can be done with @samp{imul $69, %eax} rather than @samp{imul