gas/doc/c-i860.texi

   1 @c Copyright 2000, 2003 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4 @ifset GENERIC
   5 @page
   6 @node i860-Dependent
   7 @chapter Intel i860 Dependent Features
   8 @end ifset
   9 @ifclear GENERIC
  10 @node Machine Dependencies
  11 @chapter Intel i860 Dependent Features
  12 @end ifclear
  13
  14 @ignore
  15 @c FIXME: This is basically a stub for i860. There is tons more information
  16 that I will add later (jle@cygnus.com). The assembler is still being
  17 written. The i860 assembler that existed previously was never finished
  18 and doesn't even build. Further, its not BFD_ASSEMBLER and it doesn't
  19 do ELF (it doesn't do anything, but you get the point).
  20 @end ignore
  21
  22 @cindex i860 support
  23 @menu
  24 * Notes-i860::                  i860 Notes
  25 * Options-i860::                i860 Command-line Options
  26 * Directives-i860::             i860 Machine Directives
  27 * Opcodes for i860::            i860 Opcodes
  28 @end menu
  29
  30 @node Notes-i860
  31 @section i860 Notes
  32 This is a fairly complete i860 assembler which is compatible with the
  33 UNIX System V/860 Release 4 assembler. However, it does not currently
  34 support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}).
  35
  36 Like the SVR4/860 assembler, the output object format is ELF32. Currently,
  37 this is the only supported object format. If there is sufficient interest,
  38 other formats such as COFF may be implemented.
  39 @node Options-i860
  40 @section i860 Command-line Options
  41 @subsection SVR4 compatibility options
  42 @table @code
  43 @item -V
  44 Print assembler version.
  45 @item -Qy
  46 Ignored.
  47 @item -Qn
  48 Ignored.
  49 @end table
  50 @subsection Other options
  51 @table @code
  52 @item -EL
  53 Select little endian output (this is the default).
  54 @item -EB
  55 Select big endian output. Note that the i860 always reads instructions
  56 as little endian data, so this option only effects data and not
  57 instructions.
  58 @item -mwarn-expand
  59 Emit a warning message if any pseudo-instruction expansions occurred.
  60 For example, a @code{or} instruction with an immediate larger than 16-bits
  61 will be expanded into two instructions. This is a very undesirable feature to
  62 rely on, so this flag can help detect any code where it happens. One
  63 use of it, for instance, has been to find and eliminate any place
  64 where @code{gcc} may emit these pseudo-instructions.
  65 @item -mxp
  66 Enable support for the i860XP instructions and control registers.  By default,
  67 this option is disabled so that only the base instruction set (i.e., i860XR)
  68 is supported.
  69 @end table
  70
  71 @node Directives-i860
  72 @section i860 Machine Directives
  73
  74 @cindex machine directives, i860
  75 @cindex i860 machine directives
  76
  77 @table @code
  78 @cindex @code{dual} directive, i860
  79 @item .dual
  80 Enter dual instruction mode. While this directive is supported, the
  81 preferred way to use dual instruction mode is to explicitly code
  82 the dual bit with the @code{d.} prefix.
  83 @end table
  84
  85 @table @code
  86 @cindex @code{enddual} directive, i860
  87 @item .enddual
  88 Exit dual instruction mode. While this directive is supported, the
  89 preferred way to use dual instruction mode is to explicitly code
  90 the dual bit with the @code{d.} prefix.
  91 @end table
  92
  93 @table @code
  94 @cindex @code{atmp} directive, i860
  95 @item .atmp
  96 Change the temporary register used when expanding pseudo operations. The
  97 default register is @code{r31}.
  98 @end table
  99
 100 @node Opcodes for i860
 101 @section i860 Opcodes
 102
 103 @cindex opcodes, i860
 104 @cindex i860 opcodes
 105 All of the Intel i860XR and i860XP machine instructions are supported. Please see
 106 either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information.
 107 @subsection Other instruction support (pseudo-instructions)
 108 For compatibility with some other i860 assemblers, a number of
 109 pseudo-instructions are supported. While these are supported, they are
 110 a very undesirable feature that should be avoided -- in particular, when
 111 they result in an expansion to multiple actual i860 instructions. Below
 112 are the pseudo-instructions that result in expansions.
 113 @itemize @bullet
 114 @item Load large immediate into general register:
 115
 116 The pseudo-instruction @code{mov imm,%rn} (where the immediate does
 117 not fit within a signed 16-bit field) will be expanded into:
 118 @smallexample
 119 orh large_imm@@h,%r0,%rn
 120 or large_imm@@l,%rn,%rn
 121 @end smallexample
 122 @item Load/store with relocatable address expression:
 123
 124 For example, the pseudo-instruction @code{ld.b addr,%rn}
 125 will be expanded into:
 126 @smallexample
 127 orh addr_exp@@ha,%r0,%r31
 128 ld.l addr_exp@@l(%r31),%rn
 129 @end smallexample
 130
 131 The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well.
 132 @item Signed large immediate with add/subtract:
 133
 134 If any of the arithmetic operations @code{adds, addu, subs, subu} are used
 135 with an immediate larger than 16-bits (signed), then they will be expanded.
 136 For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
 137 @smallexample
 138 orh large_imm@@h,%r0,%r31
 139 or large_imm@@l,%r31,%r31
 140 adds %r31,%rx,%rn
 141 @end smallexample
 142 @item Unsigned large immediate with logical operations:
 143
 144 Logical operations (@code{or, andnot, or, xor}) also result in expansions.
 145 The pseudo-instruction @code{or large_imm,%rx,%rn} results in:
 146 @smallexample
 147 orh large_imm@@h,%rx,%r31
 148 or large_imm@@l,%r31,%rn
 149 @end smallexample
 150
 151 Similarly for the others, except for @code{and} which expands to:
 152 @smallexample
 153 andnot (-1 - large_imm)@@h,%rx,%r31
 154 andnot (-1 - large_imm)@@l,%r31,%rn
 155 @end smallexample
 156 @end itemize
 157